EE141- Spring 2003

Lecture 25

Interconnect Effects
Input-Output

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Dealing with Capacitive Cross Talk

Avoid floating nodes

Protect sensitive nodes

Make rise and fall times as large as possible

Differential signaling

Do not run wires together for a long distance

Use shielding wires

Use shielding layers

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 Delay Degradation

- Impact of neighboring signal

activity on switching delay
Cc
- When neighboring lines switch
in opposite direction of victim
line, delay increases

Miller Effect
- Both terminals of capacitor are switched in opposite directions
(0 → Vdd, Vdd → 0)
- Effective voltage is doubled and additional charge is needed
(from Q=CV)
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Impact of Cross Talk on Delay

r is ratio between capacitance to GND and to neighbor

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 Interconnect Projections
Low-k dielectrics

Both delay and power are reduced by dropping interconnect

capacitance

Types of low-k materials include: inorganic (SiO2), organic
(Polyimides) and aerogels (ultra low-k)

The numbers below are on the
conservative side of the NRTS roadmap ε

Generation 0.25 0.18 0.13 0.1 0.07 0.05

µm µm µm µm µm µm
Dielectric 3.3 2.7 2.3 2.0 1.8 1.5
Constant
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How to Battle Capacitive

Crosstalk

Shielding
Avoid large crosstalk cap’s

wire
Avoid floating nodes
GND
Isolate sensitive nodes
Shielding
Control rise/fall times
VDD layer
Shield!
GND
Differential signaling

Substrate (GND)

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 Driving Large Capacitances
V DD

V in V out

CL

• Transistor Sizing
• Cascaded Buffers

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Using Cascaded Buffers

In Out

1 2 N CL = 20 pF

0.25 µ m process F = CL/Cin = 8000

Cin = 2.5 fF fopt = 3.6 N = 7
tp0 = 30 ps tp = 0.76 ns

(See Chapter 5)

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 Output Driver Design

Trade off Performance for Area and Energy

Given tpmax find N and f

Area
f −1 F −1
= (1 + f + f + ... + f )A =
N
N −1
A A =
2
A
f −1 f −1
driver min min min

Energy
F −1
(
Edriver = 1 + f + f 2 + ... + f N −1 CiVDD
2
)=
f −1
2
CiVDD
C
≈ L VDD
f −1
2

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Delay as a Function of F and N

10,000
F = 10,000

p
1000
t

/
tp/tp0

100
F = 1000 F = 100

10
1 3 5 7 9 11

Number of buffer stages N

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 Output Driver Design

0.25 µm process, CL = 20 pF

Transistor Sizes for optimally-sized cascaded buffer tp = 0.76 ns

Transistor Sizes of redesigned cascaded buffer tp = 1.8 ns

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How to Design Large Transistors

D(rain)

Multiple
Reduces diffusion capacitance
Contacts

S(ource)

G(ate)

small transistors in parallel

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 Bonding Pad Design
Bonding Pad GND

100 µm
Out

VDD Out
In GND
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ESD Protection

When a chip is connected to a board, there is

unknown (potentially large) static voltage
difference

Equalizing potentials requires (large) charge
flow through the pads

Diodes sink this charge into the substrate –
need guard rings to pick it up.

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 ESD Protection
VDD

R D1
PAD X
D2

Diode

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Chip Packaging
Bonding wire
•Bond wires (~25µm) are used
to connect the package to the chip
Chip
L
Mounting
cavity • Pads are arranged in a frame
around the chip
Lead
L´ frame
• Pads are relatively large
(~100µm in 0.25µm technology),
with large pitch (100µm)
Pin

•Many chips areas are ‘pad limited’

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 Pad Frame
Layout Die Photo

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Chip Packaging

An alternative is ‘flip-chip’:
» Pads are distributed around the chip
» The soldering balls are placed on pads
» The chip is ‘flipped’ onto the package
» Can have many more pads

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 INTERCONNECT

Dealing with Resistance

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Impact of Resistance

Impact of resistance is commonly seen in

power supply distribution:
» IR drop
» Voltage variations

Power supply is distributed to minimize the IR
drop and the change in current due to
switching of gates

How to drive long RC wires
» Major impact on performance in today’s ICs

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 RI Introduced Noise

VD D I

φpre R’ VDD - ∆V’

I ∆V
∆V

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Power and Ground Distribution

VDD GND

Logic Logic

VDD VDD

GND GND

(a) Finger-shaped network (b) Network with multiple supply pins

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 Resistance and the Power
Distribution Problem
Before After

• Requires fast and accurate peak current prediction

• Heavily influenced by packaging technology Source: Simplex
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Power Distribution

Low-level distribution is in Metal 1

Power has to be ‘strapped’ in higher layers of
metal.

The spacing is set by IR drop,
electromigration, inductive effects

Always use multiple contacts on straps

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 Electromigration (1)

Limits dc-current to 1 mA/µm

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Electromigration (2)

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 The Impact of Resistivity
Tr

The distributed rc-

rc-line
R1 R2 RN-1 RN

C1 C2 CN-1 CN
Vin

2 .5
2 .5

x= L/ 10
x= L/ 10
Diffused signal 2
2

x = L/4

propagation x = L/4
vo ltag e (V)

1 .5
vo ltag e (V)

1 .5
x = L/ 2
x = L/ 2
1
1
x= L

Delay ~ L2
x= L
0 .5
0 .5

0
00 0.5 1 1 .5 2 2 .5 3 3 .5 4 4 .5 5
0 0.5 1 1 .5 2 2 .5 3 3 .5 4 4 .5 5
EE141 tim e (n se c)
tim e (n se c)

The Global Wire Problem

Td = 0.377R w C w + 0.693(R d Cout + R d C w + R w Cout )

Challenges

No further improvements to be expected after the
introduction of Copper (superconducting, optical?)

Design solutions
» Use of fat wires
» Insert repeaters — but might become prohibitive (power, area)
» Efficient chip floorplanning

Towards “communication-based” design
» How to deal with latency?
» Is synchronicity an absolute necessity?

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 Interconnect:
# of Wiring Layers
# of metal layers is steadily increasing due to:
ρ = 2.2 M6
µΩ-cm
µΩ • Increasing die size and device count: we need
more wires and longer wires to connect
Tins
everything
M5 • Rising need for a hierarchical wiring network;
local wires with high density and global wires with
W
S low RC
M4 Minimum Widths (Relative) Minimum Spacing (Relative)
H 3.5 4.0

3.0 3.5

3.0
2.5
M3
2.5
2.0 M5 M5
2.0
M4 M4
M2
1.5
M3 1.5 M3
1.0 M2 M2
M1
M1
1.0 M1
poly
0.5 Poly 0.5 Poly
substrate

0.25 µm wiring stack 0.0 0.0

1.0µ 0.8µ 0.6µ 0.35µ 0.25µ 1.0µ 0.8µ 0.6µ 0.35µ 0.25µ
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Interconnect Projections:
Copper

Copper is planned in full sub-0.25
µm process flows and large-scale
designs (IBM, Motorola, IEDM97)

With cladding and other effects, Cu
~ 2.2 µΩ-cm vs. 3.5 for Al(Cu) ⇒
40% reduction in resistance

Electromigration improvement;
100X longer lifetime (IBM,
IEDM97)
» Electromigration is a limiting factor Vias
beyond 0.18 µm if Al is used (HP,
IEDM95)

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 Diagonal Wiring
destination

diagonal
y

source
x
Manhattan

• 20+% Interconnect length reduction

• Clock speed
Signal integrity
Power integrity
• 15+% Smaller chips
plus 30+% via reduction

EE141 Courtesy Cadence X-initiative

Using Bypasses
Driver
WL Polysilicon word line

Metal word line

Driving a word line from both sides

Metal bypass

WL K cells Polysilicon word line

Using a metal bypass

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 Reducing RC-delay

Repeater

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Repeater Insertion (Revisited)

Taking the repeater loading into account

For a given technology and a given interconnect layer, there exists

exists
an optimal length of the wire segments between repeaters. The
delay of these wire segments is independent of the routing layer!

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 INTERCONNECT

Dealing with Inductance

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L di/dt

VDD
Impact of inductance
on supply voltages:
L i(t) • Change in current induces
V’DD
the change in voltage
• Longer supply lines have
Vout larger L
Vin

CL

GND’

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 L di/dt: Simulation
5.0
vout 4.0
5V tfall = 4 nsec
3.0

Vout(V)
2.0
tfall = 0.5 nsec
t 1.0
0.0

iL
40mA 20

IL (mA)
20mA
10
t

0
vL 0.5
0.2V 0.3

VL(V)
t 0.1

-0.1

-0.3
2 4 6 8 10
t (nsec)

Signals Waveforms for Output Driver connected To Bonding Pads

(a) vout ; (b) i L and (c) v L.
The Results of an Actual Simulation are Shown on the Right Side.

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Choosing the Right Pin

Bonding wire

Chip
L
Mounting
cavity

Lead
L´ frame

Pin

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 Decoupling Capacitors

Board Bonding
wiring wire
⫹

SUPPLY Cd CHIP

Decoupling
capacitor

Decoupling capacitors are added:

• on the board (right under the supply pins)
• on the chip (under the supply straps, near large buffers)

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De-coupling Capacitor Ratios

EV4
» total effective switching capacitance = 12.5nF
» 128nF of de-coupling capacitance
» de-coupling/switching capacitance ~ 10x

EV5
» 13.9nF of switching capacitance
» 160nF of de-coupling capacitance

EV6
» 34nF of effective switching capacitance
» 320nF of de-coupling capacitance -- not enough!
Source: B. Herrick (Compaq)
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 EV6 De-coupling Capacitance
Design for ∆Idd= 25 A @ Vdd = 2.2 V, f = 600
MHz
» 0.32-µF of on-chip de-coupling capacitance was
added
– Under major busses and around major gridded clock drivers
– Occupies 15-20% of die area
» 1-µF 2-cm2 Wirebond Attached Chip Capacitor
(WACC) significantly increases “Near-Chip” de-
coupling
– 160 Vdd/Vss bondwire pairs on the WACC minimize
inductance

Source: B. Herrick (Compaq)

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EV6 WACC

389 Signal - 198 VDD/VSS Pins

389 Signal Bondwires
395 VDD/VSS Bondwires
320 VDD/VSS Bondwires

WACC
Microprocessor
Heat Slug
587 IPGA
Source: B. Herrick (Compaq)
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 Design Techniques to address L di/dt

Separate power pins for I/O pads and chip core

Multiple power and ground pins

Position of power and ground pins on package

Increase tr and tf

Advanced packaging technologies

Decoupling capacitances on chip and on board

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