Integrated Circuit Passive Components: Objective

IC Passive Components (1/13/00) Page 1 -1
INTEGRATED CIRCUIT PASSIVE COMPONENTS

INTRODUCTION
Objective
The objective of this presentation is:
1.) Show the passive components that are compatible with BJT and CMOS technologies
2.) Modifications to the standard BJT and CMOS processes
3.) Physical influence on passive components
Outline
• Capacitors
• Resistors
• Inductors
• Modifications to the standard BJT and CMOS processes
• Diodes
• Summary
ECE 6421 - Analog IC Design  P.E. Allen and J.A. Connelly 2000
INTEGRATED CIRCUIT CAPACITORS

PN Junction
Concept:
Metallurgical Junction
p-type semiconductor n-type semiconductor
iD
+vD -
Depletion
region
p-type n-type
semicon- semicon-
ductor ductor
iD
+vD -
xd
xp xn x
0
1. Doped atoms near the metallurgical junction lose their free carriers by diffusion.
2. As these fixed atoms lose their free carriers, they build up an electric field which opposes the diffusion
mechanism.
3. Equilibrium conditions are reached when:
Current due to diffusion = Current due to electric field
PN Junction Characterization
Cross section of an ideal pn junction: Impurity concentration (cm-3)

xd ND
xp xn
0 x
p-type n-type
semi- semi-
con- con- -NA
ductor ductor
iD Depletion charge concentration (cm-3)

+vD - qND
xp
0 xn x
-qNA
Electric Field (V/cm)
E0
Potential (V)
φ0− vD
x
Fig. 2.3-2A
xd
Summary of PN Junction Analysis

Barrier potential-
kT NAND  NAND
φo = φB = ln  = V t  n2 
ln
q  ni2   i 
Depletion region widths-
xn =
2εsi(φo-vD)NA 

qND(NA+ND) 1
x ∝
N
xp =
2εsi(φo-vD)ND
qND(NA+ND) 
Depletion capacitance- Cj
εsiqNAND 1 Cj0
Cj = A =
2(NA+ND) φo-vD vD Cj0
1- φ
o
Fig. 2.3-3B 0 φ0 vD
Breakdown voltage-
εsi(NA+ND) 2 1
BV = E max ∝
2qNAND N
Summary of PN Junction Analysis - Continued

Graded junction:
Impurity Concentration (cm-3)
ND
x
0
NA PC00
Above expressions become:
Depletion region widths-
3
 2εsi(φo-vD)NA m
x n =  qN (N +N )  
 D A D   1 m
 2εsi(φo-vD)ND m
 x ∝ 
 N
2.5
x p =  qN (N +N )   2
 D A D 
Cj
Depletion capacitance- 1.5
Cj0
 εsiqNAND  m 1 Cj0
1
Cj = A2(N +N ) =
 A D  ( φo-vD) m  v D m m=0.333
1 -
 φ o  0.5
m=0.5
where 0.33 ≤m ≤ 0.5. (Note that m = MJ) 0
-10 -8 -6 -4 -2 0 2
vD PC01A
φ0
Summary of PN Junction Analysis - Continued

Current-Voltage Relationship-
2  -VGO
  vD   Dppno D n n p o qAD ni
iD = Isexp  - 1 where I s = qA +  ≈ = KT 3 exp 
  Vt    Lp Ln  L N  Vt 
25
20
iD 15
Is 10
5
0
-5
-4 -3 -2 -1 0 1 2 3 4
vD/Vt
10 x1016
8 x1016
16
iD 6 x10
Is
4 x1016
2 x1016
0
-40 -30 -20 -10 0 10 20 30 40
vD/Vt

Cross-Section of an NPN BJT
All passive components must be compatible with this structure.
Substrate Collector Base Emitter
p p
n+ n+
n-epitaxial layer
n+ buried layer
p- substrate
Heavily Lightly Intrinsic Lightly Heavily Metal

Doped p Doped p Doping Doped n Doped n BJTNPN

Collector-Base Capacitance (C µ )
Illustration:
Substrate Collector Base
p p
n+
n-epitaxial layer
n+ buried layer
p- substrate
Model: Sidewall contribution:

CCB = Cµ
C B π
Asidewall = P·d 2
CCS
where
Substrate P = perimeter of the capacitor
PC02
d = depth of the diffusion
Values:
Includes the bottom plus sidewall capacitance.
Cµ ≈ 1fF/µm2 (dependent on the reverse bias voltage)
Can also have base-emitter capacitance and collector-substrate capacitance
MOS Capacitors
Polysilicon-Oxide-Channel for Enhancement MOSFETs
Bulk connected to V SS
G D,S VDG =VGS >V T

VSS
Gate
VSS VGS>VT
Source Drain
Bulk Poly CGS
Channel
p+ n+ n+
p- Substrate/Bulk
Comments:
• Capacitance = CGS ≈ CoxW·L
• Channel must be formed, therefore VGS > VT
• With VGS > VT and VDS = 0, the transistor is in the active region.
MOS Capacitors - Continued

Bulk tuning of the polysilicon-oxide-channel capacitor (0.35µm CMOS)
1.0
CG
0.8
Volts or pF
VT
-0.65V 0.6
CG vB 0.4
0.2
0.0
Fig. 2.5-3 -1.5 -1.4 -1.3 -1.2 -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5
vB (Volts)
Cmax/Cmin ≈ 4

Bulk connected to Source-Drain
VDG =VGS >V T
G D,S
Gate
VGS>VT
Source Drain
Bulk Poly CGS
Channel
p+ n+ n+
CGB
p- Substrate/Bulk
CG-D,S
CG-D,S = CGS(oxide) + CGB(depletion)
CGS CBG
Comments:
VG-D,S
• Capacitance is more constant as a function of VG-D,S VT
• Still not a good capacitor for large voltage swings

Accumulation-Mode Capacitor12

=
CG-D,S
Drain Substrate
Source
Oxide Polysilicon
n+ n+
Source n+ p+
Channel
n-well
Fig. 2.5-4
Comments:
• ±30% tuning range (Tuned by the voltage across the capacitor terminals)
• Q ≈ 25 for 3.1pF at 1.8 GHz (optimization leads to Qs of 200 or greater)
1
T. Soorapanth, et. al., “Analysis and Optimization of Accumulation-Mode Varactor for RF ICs,” Proc. 1998 Symposium on VLSI Circuits, Digest of
Papers, pp. 32-33, 1998.
2
R. Castello, et. al., “A ±30% Tuning Range Varactor Compatible with future Scaled Technologies,” Proc. 1998 Symposium on VLSI Circuits,
Digest of Papers, pp. 34-35, 1998.

Polysilicon-Oxide Diffusion/Active for Enhanced MOSFETs
A B
A B
IOX IOX
IOX
poly
FOX FOX
n-active
poly
n-well
p-substrate
n-active
n-well
p-substrate
Unit capacitance ≈ 1.2 fF/µm2

Voltage dependence:
C(V) ≈ C(0) + a1V + a2V2, where a1 ≈ 0 and a2 ≈ 210 ppm/V2
(Not as good linearity as poly-poly capacitors)

Polysilicon-Oxide-Polysilicon (Poly-Poly)
A B
IOX
Polysilicon II IOX
IOX Polysilicon I
FOX FOX
substrate
Best possible capacitor for analog circuits

Less parasitics
Voltage independent
Approach for increasing the voltage linearity:
Top Plate Top Plate
Bottom Plate Bottom Plate
Implementation of Capacitors using Available Metal and Poly Interconnect Layers

M3
M2
T
M1
B Poly
M3 T
M2
T B
M1
M2 B
M1
B T
Poly
M2
T
M1
B Fig. 2.5-8
Fractal Capacitors
Capacitance between conductors on the same level and use lateral flux..
Fringing Capacitance
Top View of a Lateral Flux Capacitor
PC10
These capacitors are called fractal capacitors because the fractal patterns are structures that enclose a finite
area with an infinite perimeter.
In certain cases, the capacitor/area can be increased by a factor of 10 over vertical flux capacitors.
Capacitor Errors
1.) Oxide gradients
2.) Edge effects
3.) Parasitics
4.) Voltage dependence
5.) Temperature dependence
Capacitor Errors - Oxide Gradients

Error due to a variation in oxide thickness across the wafer.
No common centroid
A1 A2 B
layout
Common centroid
A1 B A2 layout
x1 x2 x1
Only good for one-dimensional errors.
An alternate approach is to layout numerous repetitions and connect them randomly to achieve a statistical
error balanced over the entire area of interest.
A B C A B C A B C
C A B C A B C A B
B C A B C A B C A
0.2% matching of poly resistors was achieved using an array of 50 unit resistors.
Capacitor Errors - Edge Effects

There will always be a randomness on the definition of the edge.
However, etching can be influenced by the presence of adjacent structures.
For example,
Matching of A and B are disturbed by the presence of C.
C
A B
Improved matching achieve by matching the surroundings of A and B.
C
A B
Capacitor Errors - Area/Periphery Ratio

The best match between two structures occurs when their area-to-periphery ratios are identical.
Let C’1 = C1 ± ∆C1 and C’2 = C2 ± ∆C2
where
C’ = the actual capacitance
C = the desired capacitance (which is proportional to area)
∆C = edge uncertainty (which is proportional to the periphery)
Solve for the ratio of C’2/C’1,
∆C2
C’2 C 2Ê± ∆ C 2 C2 
1 ± C2 

C’1 = C 1Ê± ∆ C 1 = C1  ∆ C 1
 C 
1 ±
1
C2  ∆ C 2  ∆ C 1  C2  ∆ C 2 ∆ C 1
≈ C 1 ± C  1 +- C  ≈ C 1 ± C +- C 
1 2   1  1 2 1 
∆C2 ∆C1 C’ 2 C 2
If C = C , then C’ = C
2 1 1 1
Therefore, the best matching results are obtained when the area/periphery ratio of C2 is equal to the
area/periphery ratio of C1.
Capacitor Errors - Relative Accuracy

Capacitor relative accuracy is proportional to the area of the capacitors and inversely proportional to the
difference in values between the two capacitors.
For example,
0.04
Unit Capacitance = 0.5pF

Relative Accuracy 0.03
Unit Capacitance = 1pF
0.02
0.01
Unit Capacitance = 4pF
0.00
1 2 4 8 16 32 64
Ratio of Capacitors
Capacitor Errors - Parasitics

Parasitics are normally from the top and bottom plate to ac ground which is typically the substrate.
Top Plate
Top Desired
plate Capacitor
parasitic
Bottom
plate
Bottom Plate
parasitic
Top plate parasitic is 0.01 to 0.001 of Cdesired

Bottom plate parasitic is 0.05 to 0.2 Cdesired
Other Considerations on Capacitor Accuracy

Decreasing Sensitivity to Edge Variation:
A A' A A'
B B' B B'
Sensitive to edge variation in Sensitive to edge varation in
both upper andlower plates upper plate only. Fig. 2.6-13
A structure that minimizes the ratio of perimeter to area (circle is best).
Top Plate
of Capacitor
Bottom plate
of capacitor
Fig. 2.6-14
Capacitor Errors - Temperature and Voltage Dependence

Polysilicon-Oxide-Semiconductor Capacitors
Absolute accuracy ≈ ±10%
Relative accuracy ≈ ±0.2%
Temperature coefficient ≈ +25 ppm/C°
Voltage coefficient ≈ -50ppm/V
Polysilicon-Oxide-Polysilicon Capacitors
Absolute accuracy ≈ ±10%
Relative accuracy ≈ ±0.2%
Temperature coefficient ≈ +25 ppm/C°
Voltage coefficient ≈ -20ppm/V
Accuracies depend upon the size of the capacitors.
Capacitor Layout
Double-polysilicon capacitor Triple-level metal capacitor.

Metal Polysilicon 2
Metal 3 Metal 2 Metal 1
FOX
,,,,
Substrate FOX
Polysilicon gate Substrate
,,,, Metal 3 Metal 2 Metal 1 Metal 3
,,,,
Polysilicon gate Via 2
Polysilicon 2
,,,,
Via 2
Cut Cut Metal 2
,,,,
Via 1
Metal 1
,,,,
Metal 1
Fig. 2.6-17
INTEGRATED CIRCUIT RESISTORS

Resistor Layout
Direction of current flow
T
Area, A
L Fig. 2.6-15
Resistance of a conductive sheet is expressed in terms of

ρL ρL
R = A = W T (Ω)
where
ρ = resistivity in Ω-m
Ohms/square:
ρ  L L
R=  = ρ S W (Ω)
T  W
where
ρS is a sheet resistivity and has the units of ohms/square

Base and Emitter Diffused Resistors
Cross-section of a Base Resistor:
Substrate Collector A B
RAB
A B
p p
n+ Cj Cj
n-epitaxial layer
2 2
n+ buried layer Collector

p- substrate
PC03
Comments:
Sheet resistance ≈ 100 Ω/ to 200 Ω/
TCR = +1500ppm/¡C
Note:
1% 104
=
¡C ¡C
Emitter Resistor:
Sheet resistance ≈ 52 Ω/ to 10 Ω/ (Generally too small to make sufficient resistance in reasonable
area)
TCR = +600ppm/¡C

Base Pinched Resistor
Good for large value of sheet resistance.
Cross-section:
Substrate A B
p p
n+ n+
n-epitaxial layer
p- substrate
PC06
IV Curves and Model:

iAB
Pinched operation RAB
A B
vAB Collector PC05

Comments:
Sheet resistance is 5 to 15kΩ/
Voltage across the resistor is limited to 6V or less because of breakdown
TCR ≈ 2500ppm/¡C

Epitaxial Pinched Resistors
Cross section:
Substrate A B
p p
n+
n-epitaxial layer
p- substrate
PC06
Sheet resistance ≈ 1-10kΩ/

Top View:
A B
PC07
MOS Resistors - Source/Drain Resistor

Metal
SiO2 p+
FOX FOX
n- well
p- substrate
Fig. 2.5-16
Diffusion: Ion Implanted:

10-100 ohms/square 500-2000 ohms/square
Absolute accuracy = ±35% Absolute accuracy = ±15%
Relative accuracy = 2% (5 µm), 0.2% (50 µm) Relative accuracy = 2% (5 µm), 0.15% (50 µm)
Temperature coefficient = +1500 ppm/°C Temperature coefficient = +400 ppm/°C
Voltage coefficient ≈ -200 ppm/V Voltage coefficient ≈ -800 ppm/V
Comments:
• Parasitic capacitance to well is voltage dependent.
• Piezoresistance effects occur due to chip strain from mounting.
Polysilicon Resistor
,,,,,
Metal
Polysilicon resistor
,, p- substrate
FOX
Fig. 2.5-17
30-100 ohms/square (unshielded)

100-500 ohms/square (shielded)
Absolute accuracy = ±30%
Relative accuracy = 2% (5 µm)
Temperature coefficient = 500-1000 ppm/°C
Voltage coefficient ≈ -100 ppm/V
Comments:
• Used for fuzes and laser trimming
• Good general resistor with low parasitics
N-well Resistor
Metal
n+
FOX FOX FOX

n- well
p- substrate
Fig. 2.5-18
1000-5000 ohms/square
Absolute accuracy = ±40%
Relative accuracy ≈ 5%
Temperature coefficient = 4000 ppm/°C
Voltage coefficient is large ≈ +8000 ppm/V
Comments:
• Good when large values of resistance are needed.
• Parasitics are large and resistance is voltage dependent
Example of Resistor Layouts

Metal Metal
FOX FOX FOX FOX FOX

Substrate Substrate
Active area (diffusion) Active area (diffusion) Well diffusion
Active area W
Contact Well diffusion
Active area or Polysilicon W Contact
Cut Cut
L
Metal 1 Metal 1
L
Diffusion or polysilicon resistor Well resistor Fig. 2.6-16
Corner corrections:
0.5
1.45 1.25
Fig. 2.6-16B
Example 2.6-1 Resistance Calculation

Given a polysilicon resistor like that drawn above with W=0.8µm and L=20µm, calculate ρs (in Ω/❑), the
number of squares of resistance, and the resistance value. Assume that ρ for polysilicon is 9 × 10-4 Ω-
cm and polysilicon is 3000 Å thick. Ignore any contact resistance.
Solution
First calculate ρs.
ρ 9 × 10 -4 Ω - c m
ρs = T = = 30 Ω/❑
3000 × 10 -8 c m
The number of squares of resistance, N, is
L 20µm
N = W = 0.8µm = 25
giving the total resistance as
R = ρs × Ν = 30 × 25 = 750 Ω
Integrated Circuit Passive Component Performance Summary
Component Type Range of Values Absolute Relative Temperature Voltage

Accuracy Accuracy Coefficient Coefficient
Poly-oxide-semicond- 0.35-1.0 fF/µm2 10% 0.1% 20ppm/°C ±20ppm/V
uctor Capacitor
Poly-Poly Capacitor 0.3-1.0 fF/µm2 20% 0.1% 25ppm/°C ±50ppm/V
Base Diffused 100-200Ω/sq. ±20% 0.2% +1750ppm/°C -
Emitter Diffused 2-10Ω/sq. ±20% ±2% +600ppm/°C -
Base Pinched 2k-10kΩ/sq. ±50% ±10% +2500ppm/°C Poor
Epitaxial Pinched 2k-5kΩ/sq. ±50% ±7% +3000ppm/°C Poor
Source/Drain Diffused 10-100 Ω/sq. 35% 2% 1500ppm/°C -200ppm/V
Ion Implanted Resistor 0.5-2 kΩ/sq. 15% 2% 400ppm/°C -800ppm/V
Poly Resistor 30-200 Ω/sq. 30% 2% 1500ppm/°C -100ppm/V
n-well Resistor 1-10 kΩ/sq. 40% 5% 8000ppm/°C -10kppm/V

Thin Film 0.1k-2kΩ/sq. ±5-±20% ±0.2-±2% ±10 to ±200ppm/°C -
INDUCTORS
Inductors
What is the range of values for on-chip inductors?
,,,,,, 12
10
Inductor area is too large
Inductance (nH)
8
6 ωL = 50Ω
,,,,,,
4
Interconnect parasitics
2 are too large
0 0 10 20 30 40 50
Frequency (GHz) Fig. 6-5
Consider an inductor used to resonate with 5pF at 1000MHz.

1 1
L= 2 2 = = 5nH
4π fo C (2π·109)2·5x10-12
Note: Off-chip connections will result in inductance as well.
Candidates for inductors in CMOS technology are:

1.) Bond wires
2.) Spiral inductors
3.) Multi-level spiral
4.) Solenoid
Bond wire Inductors:
β β
d Fig.6-6
• Function of the pad distance d and the bond angle β

• Typical value is 1nH/mm which gives 2nH to 5nH in typical packages
• Series loss is 0.2 /mm for 1 mil diameter aluminum wire
• Q 60 at 2 GHz
Planar Spiral Inductors

Spiral Inductors on a Lossy Substrate:
L R
C1 C2
R1 R2
Fig. 16-7
• Design Parameters:
Inductance, L = Σ(Lself + Lmutual)
ωL
Quality factor, Q =
R
1
Self-resonant frequency: fself =
LC
• Trade-off exists between the Q and self-resonant frequency
• Typical values are L = 1-8nH and Q = 3-6 at 2GHz
Planar Spiral Inductors - Continued

Inductor Design
I
,,,,,
W
SiO2
I ID I
Silicon
S
I Fig. 6-9
Nturns = 2.5
Typically: 3<Nturns <5 and S = Smin for the given current
Select the OD, Nturns, and W so that ID allows sufficient magnetic flux to flow through the
center.
Loss Mechanisms:
• Skin effect
• Capacitive substrate losses
• Eddy currents in the silicon

Influence of a Lossy Substrate
L R
C1 C2
CLoad
R1 R2
Fig. 12.2-13
where:
L is the desired inductance
R is the series resistance
C1 and C2 are the capacitance from the inductor to the ground plane
R1 and R2 are the eddy current losses in the silicon
Guidelines for using spiral inductors on chip:
• Lossy substrate degrades Q at frequencies close to fself
• To achieve an inductor, one must select frequencies less than fself
• The Q of the capacitors associated with the inductor should be very high

Comments concerning implementation:
1.) Put a metal ground shield between the inductor and the silicon to reduce the capacitance.
• Should be patterned so flux goes through but electric field is grounded
• Metal strips should be orthogonal to the spiral to avoid induced loop current
• The resistance of the shield should be low to terminate the electric field
2.) Avoid contact resistance wherever possible to keep the series resistance low.
3.) Use the metal with the lowest resistance and furtherest away from the substrate.
4.) Parallel metal strips if other metal levels are available to reduce the resistance.
Example:
Fig. 6-10
Multi-Level Spiral Inductors

Use of more than one level of metal to make the inductor.
• Can get more inductance per area
• Can increase the interwire capacitance so the different levels are often offset to get
minimum overlap.
• Multi-level spiral inductors suffer from contact resistance (must have many parallel contacts
to reduce the contact resistance)
Solenoid Inductors
Example:
Upper Metal
nt
,,
e
o i l Curr
C
Contact
Vias Magnetic Flux
,,,,,,,,,,
Current
Coil Lower Metal
SiO2
Silicon
Fig. 6-11
Comments:
• Magnetic flux is small due to planar structure
• Capacitive coupling to substrate is still present
• Potentially best with a ferromagnetic core
OTHER CONSIDERATIONS OF CMOS TECHNOLOGY

Lateral Bipolar Junction Transistor
P-Well Process
NPN Lateral-
VDD Base Emitter Collector
n+ p+ n+ n+
p-well
n-substrate
Lateral Bipolar Junction Transistor - Continued

Field-aided Lateral-
ßF ≈ 50 to 100 depending on the process
Keep channel
from forming
VDD Base Emitter VGate Collector
n+ p+ n+ n+
p-well
n-substrate
• Good geometry matching

• Low 1/f noise (if channel doesn’t form)
• Acts like a phototransistor with good responsitivity
Geometry of the Lateral PNP BJT
Minimum Size layout of a single 40 emitter dot LPNP transistor (total device area
emitter dot lateral PNP BJT: is 0.006mm2 in a 1.2µm CMOS process):
p-substrate
p-diffusion diffusion
n-well contact
Base
n-well
contact Lateral
Collector
Emitter
31.2 71.4
µm µm
Base
Gate
V SS
V SS 84.0 µm
Lateral
Collector Gate
Emitter (poly)
33.0 µm
Performance of the Lateral PNP BJT

Schematic:
Emitter
Gate
Base Vertical
Collector
Lateral ( V SS )
Collector
ßL vs ICL for the 40 emitter dot LPNP Lateral efficiency versus IE for the 40
BJT: emitter dot LPNP BJT:
VCE =
150 − 4.0 V
1.0
VCE =
130 0.8 − 4.0 V
Lateral Efficiency
VCE =
Lateral ß
110 0.6 − 0. 4V
VCE =
90 − 0. 4V
0.4
70 0.2
50 0
1 nA 10 nA 100 nA 1 µA 10 µA 100 µA 1 mA 1 nA 10 nA 100 nA 1 µA 10 µA 100 µA 1 mA
Lateral Collector Current Emitter Current
Performance of the Lateral PNP BJT - Continued

Typical Performance for the 40 emitter dot LPNP BJT:
Transistor area 0.006 mm2

Lateral ß 90
Lateral efficiency 0.70
Base resistance 150
En @ 5 Hz 2.46 nV / Hz
En (midband) 1.92 nV / Hz
fc (En) 3.2 Hz
In @ 5 Hz 3.53 pA / Hz
In (midband) 0.61 pA / Hz
fc (In) 162 Hz
fT 85 MHz
Early voltage 16 V

High Voltage MOS Transistor
The well can be substituted for the drain giving a lower conductivity drain and therefore higher
breakdown voltage.
NMOS in n-well example:
Source Gate Drain Substrate
Oxide Polysilicon
n+
Source n+ p+
Channel
n-well
p-substrate
Fig. 2.6-7A
Drain-substrate/channel can be as large as 20V or more.
Latch-up in CMOS Technology

Latch-up Mechanisms
1. SCR regenerative switching action.
2. Secondary breakdown.
,,,, ,, ,, ,, ,,
3. Sustaining voltage breakdown.
,,,,,,,,,,
,, ,,
Parasitic lateral PNP and vertical NPN BJTs in a p-well CMOS technology:
,,,, ,, ,, ,, ,,
,,,,
|,, ,,
{
|,,,,
{

VDD D G S S G D VSS
B
A
p-well
n+ p+ p+ n+ n+ p+
RN- RP-
n- substrate
Fig. 2.6-8
Equivalent circuit of the SCR formed from the parasitic BJTs:
VDD
VDD +
RN- A
-
A
Vin ≈VSS Vout
B
B
RP-
VSS
VSS Fig. 2.6-9
Preventing Latch-Up in a P-Well Technology

1.) Keep the source/drain of the MOS device not in the well as far away from the well as possible. This
will lower the value of the BJT betas.
2.) Reduce the values of RN- and RP-. This requires more current before latch-up can occur.
3.) Make a p- diffusion around the p-well. This shorts the collector of Q1 to ground.
p-channel transistor n-channel transistor
n+ guard bars p+ guard bars
VDD VSS
FOX FOX FOX FOX FOX FOX FOX

p-well
n- substrate
Figure 2.6-10
For more information see R. Troutman, “CMOS Latchup”, Kluwer Academic Publishers.
Electrostatic Discharge Protection (ESD)

Objective: To prevent large external voltages from destroying the gate oxide.
Electrical equivalent circuit
VDD
p+ to n-well
diode
To internal gates Bonding
p+ resistor Pad
n+ to p-substrate
diode
VSS
Implementation in CMOS technology
Metal
FOX n+ FOX p+ FOX

n-well
p-substrate
Fig. 2.6-11
Temperature Characteristics of Transistors

Fractional Temperature Coefficient
1 ∂x
TCF = x· ∂T Typically in ppm/°C
MOS Transistor
V T = V(T0 ) + α(T-T 0 ) + ···, where α ≈ -2.3mV/°C (200°K to 400°K)
µ = KµT-1.5
BJT Transistor
Reverse Current, IS:
1 ∂I S 3 1 VG0
· = +
IS ∂T T T kT/q
Empirically, IS doubles approximately every 5°C increase
Forward Voltage, vD:
∂vD V G0 - v D 3kT/q
= - - T ≈ -2mV/°C at vD = 0.6V
∂Τ T
Noise in Transistors
Shot Noise
i2 = 2qID∆f (amperes2)
where
q = charge of an electron
ID = dc value of iD
∆f = bandwidth in Hz
i2
Noise current spectral density = 2
∆f (amperes /Hz)
Thermal Noise
Resistor:
v2 = 4kTR∆f (volts2)
MOSFET:
8kTgm∆f
iD2 = (ignoring bottom gate)
3
where
k = Boltzmann’s constant
R = resistor or equivalent resistor in which the thermal noise is occurring.
gm = transconductance of the MOSFET
Noise in Transistors - Continued

Flicker (1/f) Noise
 Ia 
iD2 = Kf b ∆f
f 
where
Kf = constant (10-28 Farad·amperes)
a = constant (0.5 to 2)
b = constant (≈1)
Noise power
spectral density
1/f
log(f) Fig. 2.6-12
Design Rules
Design rules are geometrical constraints which guarantee the proper operation of a circuit implemented by
a given CMOS process.
These rules are necessary to avoid problems such as device misalignment, metal fracturing, lack of
continuity, etc.
Design rules are expressed in terms of minimum dimensions such as minimum values of:
• Widths
• Separations
• Extensions
• Overlaps
• Design rules typically use a minimum feature dimension called “lambda”. Lambda is usually equal to
the minimum channel length.
• Minimum resolution of the design rules is typically half lambda.
• In most processes, lambda can be scaled or reduced as the process matures.
DIODES
BJT Diode
Different configurations
Diode
PC08A PC08B PC08C PC08D PC08E PC08F
Condition IC = 0 IE = 0 IE =0 V CB = 0 V EB = 0 VCE = 0
no emitter
Series rbb’ rbb’+rcc’ rbb’+rcc’ rbb’/β rbb’/β + rcc' rbb’
Resistance
VF @10mA 960mV 950mV 950mV 850mV 940mV 920mV
Breakdown BVEBO BVCBO BVCBO BVEBO BVCBO BVEBO
Voltage
Storage Time ≈70ns ≈130ns ≈80ns ≈6ns ≈90ns ≈150ns
MOS Diode
PC09
iD = β(vD-VT)2
Comparison of the BJT and MOS diodes

Assume the Is = 1fA, βo = 99 and VD = 0.65V for the BJT diodes and β = 300µA/V2 and VT = 0.5V for
the MOS diode. Find the dc current, the static resistance, and the dynamic resistance of the BJT diode in
the first and fourth columns and the MOS diode.
IC=0 diode:
IC 1fA 1fA 0.65V
ID = β = 99 exp(0.65/0.026) = 99 (7.2x10+10) = 0.727µA , Rstatic = 0.727µA = 893kΩ
ο
1 ∂iD Isexp(0.65/0.026) ID 1
= ∂v = = = r d = 35.7kΩ
rd D V tβ ο V t 35.7kΩ
VCB=0 diode:
IC 1+βo 0.65V
ID = IE = IC+IB = α = β Isexp(0.65/0.026) = 72.7µA , Rstatic = 72.7µA = 8.93kΩ
o
Vt
rd = I = 357Ω
D
MOS diode:
0.65V 1 1
ID = 300µA/V2(0.65-0.5)2 = 6.75µA, Rstatic = 6.75µA = 100kΩ , r d ≈ g = = 11.1kΩ
m 2·300·6.75
SUMMARY
• Showed passive components that were compatible with silicon IC technology
• Capacitors are inherently the most accurate passive components
• Inductors are possible at frequencies in excess of 100Mhz
• Modifications to the standard active device include:
- Lateral PNP transistor for a BJT technology
- Lateral BJT with the base the well in CMOS technology
- Substrate BJTs
- High voltage transistors
- Latch up
- ESD protection in CMOS technology
• Diodes include BJT and CMOS (BJT diodes are more ideal)

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IC Passive Components (1/13/00) Page 1 -1

INTEGRATED CIRCUIT PASSIVE COMPONENTS

INTEGRATED CIRCUIT CAPACITORS

p-type semiconductor n-type semiconductor

Cross section of an ideal pn junction: Impurity concentration (cm-3)

iD Depletion charge concentration (cm-3)

Electric Field (V/cm)

Summary of PN Junction Analysis

Summary of PN Junction Analysis - Continued

Summary of PN Junction Analysis - Continued

Heavily Lightly Intrinsic Lightly Heavily Metal

Model: Sidewall contribution:

G D,S VDG =VGS >V T

MOS Capacitors - Continued

MOS Capacitors - Continued

CG-D,S = CGS(oxide) + CGB(depletion)

• Still not a good capacitor for large voltage swings

MOS Capacitors - Continued

MOS Capacitors - Continued

Unit capacitance ≈ 1.2 fF/µm2

MOS Capacitors - Continued

Best possible capacitor for analog circuits

Top Plate Top Plate

Bottom Plate Bottom Plate

Implementation of Capacitors using Available Metal and Poly Interconnect Layers

Top View of a Lateral Flux Capacitor

Capacitor Errors - Oxide Gradients

Capacitor Errors - Edge Effects

Improved matching achieve by matching the surroundings of A and B.

Capacitor Errors - Area/Periphery Ratio

Capacitor Errors - Relative Accuracy

Unit Capacitance = 0.5pF

Capacitor Errors - Parasitics

Top plate parasitic is 0.01 to 0.001 of Cdesired

Other Considerations on Capacitor Accuracy

A structure that minimizes the ratio of perimeter to area (circle is best).

Capacitor Errors - Temperature and Voltage Dependence

Double-polysilicon capacitor Triple-level metal capacitor.

,,,, Metal 3 Metal 2 Metal 1 Metal 3

INTEGRATED CIRCUIT RESISTORS

Resistance of a conductive sheet is expressed in terms of

n+ buried layer Collector

IV Curves and Model:

vAB Collector PC05

Sheet resistance ≈ 1-10kΩ/

MOS Resistors - Source/Drain Resistor

Diffusion: Ion Implanted:

30-100 ohms/square (unshielded)

FOX FOX FOX

Example of Resistor Layouts

FOX FOX FOX FOX FOX

Example 2.6-1 Resistance Calculation

Integrated Circuit Passive Component Performance Summary

Component Type Range of Values Absolute Relative Temperature Voltage

Poly Resistor 30-200 Ω/sq. 30% 2% 1500ppm/°C -100ppm/V

n-well Resistor 1-10 kΩ/sq. 40% 5% 8000ppm/°C -10kppm/V

Consider an inductor used to resonate with 5pF at 1000MHz.

Note: Off-chip connections will result in inductance as well.

Candidates for inductors in CMOS technology are: