Wang Mingzhen

HIGH-SPEED LOW-POWER CMOS FLASH
ANALOG-TO-DIGITAL CONVERTER FOR WIDEBAND
COMMUNICATION SYSTEM-ON-A-CHIP
A dissertation submitted in partial fulfillment of the

requirements for the degree of
Doctor of Philosophy
By
MINGZHEN WANG
B.S.in Computer Engineering, Huazhong University of Science and Technology, 1990
M.S.Egr. in Computer Science, Wright State University, 2002
M.S.Egr. in Electrical Engineering, Wright State University, 2005
__________________________________________
2007
Wright State University
WRIGHT STATE UNIVERSITY
SCHOOL OF GRADUATE STUDIES
September 11, 2007
I HEREBY RECOMMEND THAT THE DISSERTATION PREPARED UNDER

MY SUPERVISION BY Mingzhen Wang ENTITLED High-Speed Low-Power
CMOS Flash Analog-to-Digital Converter for Wideband Communication
Systems-on-a-Chip BE ACCEPTED IN PARTIAL FULFILLMENT OF THE
REQUIREMENTS FOR THE DEGREE OF Doctor of Philosophy.
___________________________________
Chien-In Henry Chen, Ph.D.
Dissertation Director
____________________________________
Ramana V. Grandhi, Ph.D.
Director, Ph.D. in Electrical Engineering
____________________________________
Joseph F. Thomas, Jr., Ph.D.
Dean, School of Graduate Studies
Committee on
Final Examination
____________________________________
Chien-In Henry Chen, Ph.D.
____________________________________
Raymond Siferd, Ph.D.
____________________________________
Marian Kazimierczuk, Ph.D.
____________________________________
Jack S.N. Jean, Ph.D.
____________________________________
Wen-Ben Jone, Ph.D.
ABSTRACT
Wang, Mingzhen, Ph.D, Engineering Ph.D Program, Department of Electrical Engineering,

Wright State University, 2007. High-Speed Low-Voltage CMOS Flash Analog-to-Digital
Converter for Wideband Communication System-on-a-Chip
With higher-level integration driven by increasingly complex digital systems and
downscaling CMOS processes available, system-on-a-chip (SoC) is an emerging
technology of low power, high cost effectiveness and high reliability and is exceedingly
attractive for applications in high-speed data conversion wireless and wideband
communication systems.
This research presents a novel ADC comparator design methodology; the speed and
performance of which is not restricted by the supply voltage reduction and device linearity
deterioration in scaling-down CMOS processes. By developing a dynamic offset
suppression technique and a circuit optimization method, the comparator can achieve a 3
dB frequency of 2 GHz in 130 nanometer (nm) CMOS process.
Combining this new comparator design and a proposed pipelined thermometer-Gray-
binary encoder designed by the DCVSPG logic, a high-speed, low-voltage clocked-digital-
comparator (CDC) pipelined CMOS flash ADC architecture is proposed for wideband
communication SoC. This architecture has advantages of small silicon area, low power,
and low cost. Three CDC-based pipelined CMOS flash ADCs were implemented in 130
nm CMOS process and their experimental results are reported:
1. 4-b, 2.5-GSPS ADC: SFDR of 21.48-dB, SNDR of 15.99-dB, ENOB of 2.4-b, ERBW
of 1-GHz, power of 7.9-mW, and area of 0.022-mm2.
iii
2. 4-b, 4-GSPS ADC: SFDR of 25-dB, SNDR of 18.6-dB, ENOB of 2.8-b, ERBW of
2-GHz, power of 11-mW.
3. 6-b, 4-GSPS ADC: SFDR of 48-dB at a signal frequency of 11.72-MHz, SNDR of
34.43-dB, ENOB of 5.4-b, power of 28-mW.
An application of the proposed CDC-based pipelined CMOS flash ADC is 1-GHz
bandwidth, 2.5-GSPS digital receiver on a chip. To verify the performance of the receiver,
a mixed-signal block-level simulation and verification flow was built in Cadence AMS
integrated platform. The verification results of the digital receiver using a 4-b 2.5-GSPS
CDC-based pipelined CMOS ADC, a 256-point, 12-point kernel function FFT and a
frequency detection logic show that two tone signals up to 1125 MHz can be detected and
discriminated.
A notable contribution of this research is that the proposed ADC architecture and the
comparator design with dynamic offset suppression and optimization are extremely
suitable for future VDSM CMOS processes and make “all-digital” receiver SoC design
practical.
iv
Contents
Chapter 1 Introduction...................................................................................................1
1.1 Background ............................................................................................... 1

1.2 Initial Research Requirements .................................................................. 3
1.3 Dissertation Research Summary ............................................................... 4
1.4 Dissertation Layout................................................................................... 5
Chapter 2 ADC Fundamentals ......................................................................................7
2.1 Primary Characteristics............................................................................. 8

2.1.1 Sampling Frequency ........................................................................8
2.1.2 Resolution ........................................................................................9
2.2 Performance Characteristics ....................................................................11
2.2.1 Static Performance .........................................................................11
2.2.1.1 Offset and Gain Error.........................................................11
2.2.1.2 Integral Non-Linearity and Differential Non-Linearity .....11
2.2.2 Dynamic Performance ...................................................................12
2.2.2.1 Signal-to-Noise Ratio........................................................ 12
2.2.2.2 Signal-to-Noise-and-Distortion Ratio............................... 12
2.2.2.3 Effective Number of Bits .................................................. 13
2.2.2.4 Spurious-Free Dynamic Range ......................................... 13
2.2.2.5 Total Harmonic Distortion ................................................ 14
Chapter 3 ADC Literature Review..............................................................................15
3.1 Architecture Overview............................................................................ 15

3.2 High Speed ADC in Literature................................................................ 17
3.3 Flash ADCs Using Inverter Comparator for SoC ................................... 19
Chapter 4 High-Speed ADCs in Wideband Receivers ...............................................22
4.1 Spurs in Spectrum ................................................................................... 23

4.2 Signal Slew Rate Limitation ................................................................... 28
4.3 Sparkles and Meta-stability..................................................................... 29
Chapter 5 Clocked Digital Comparator......................................................................32
5.1 Introduction............................................................................................. 32
5.2 Inverter Amplifier ................................................................................... 34
5.3 Clocked Digital Comparator with Dynamic Offset Suppression............ 36
5.4 Optimization of Sizing Design................................................................ 41
5.4.1 Methodology ..................................................................................41
5.4.2 Optimum Ids ...................................................................................49
5.5 Summary ................................................................................................. 52
v
Chapter 6 CDC-Based Pipelined Flash ADC Architecture .......................................53
6.1 Architecture............................................................................................. 53
6.2 CDCs and Gain Boosters ........................................................................ 57
6.3 Pipelined DCVSPG Encoders................................................................. 58
6.3.1 Encoder Architecture .....................................................................58
6.3.2 DCVSPG Logic Circuit Blocks .....................................................62
6.4 Clock Tree............................................................................................... 65
Chapter 7 Implementation and Performance of CDC-based Pipelined CMOS Flash

ADC Architecture.......................................................................................67
7.1 4-b 1.25-GHz Bandwidth 2.5-GSPS ADC.............................................. 67

7.1.1 Implementation and Performance ..................................................68
7.1.2 Schematic vs. Post Layout Performance........................................80
7.2 4-b 2-GHz Bandwidth 4GSPS ADC ....................................................... 90
7.2.2 Comparison with 4-b Flash ADCs in Literature ............................97
7.3 6-b 4GSPS ADC ..................................................................................... 98
7.3.2 Comparison with State-of-the-art 6-b flash ADC ........................108
7.4 Comparison of BDB and TGB Encoders...............................................110
Chapter 8 Application of 4-b CDC-based Pipelined ADC in a Digital Wideband

Receiver-on-a-Chip ..................................................................................112
8.1 AMS Verification Flow..........................................................................112

8.2 DEMUX Design.....................................................................................113
8.3 Verification Results................................................................................116
Chapter 9 Conclusions................................................................................................118
Appendix.........................................................................................................................122
A. Estimation of Source and Drain Areas and Peripheries ........................ 122

B. Signal / Clock Generators in Verilog_AMS.......................................... 123
C. DEMUX in VHDL................................................................................ 125
Bibliography ...................................................................................................................142
vi
List of Figures
Figure 1-1 Digital Receiver SoC [5].............................................................................................. 3
Figure 2-1 N = 3 Quantization Steps ............................................................................................. 9

Figure 2-2 Uniform Distribution of Quantization Error .............................................................. 10
Figure 3-1 Resolution N vs. Sampling Frequency fsampling............................................................ 16

Figure 3-2 Flash ADC Architecture ............................................................................................. 17
Figure 4-1 Time and frequency domain data using an 8-point DFT............................................ 24
Figure 4-2 8-point DFT with Spurs ............................................................................................. 26
Figure 4-3 Correspondence among Thermometer, Gray and Binary Codes................................ 30
Figure 4-4 Pipelined Thermometer-to-Gray Encoder.................................................................. 30
Figure 4-5 Comparison of Gray and Direct Binary Encoding at Various Sparkles ..................... 31
Figure 5-1 Inverter Amplifier with Voltage-Transfer Characteristics.......................................... 34

Figure 5-2 Small-Signal Characteristics of Inverter Amplifier.................................................... 35
Figure 5-3 Clocked Digital Comparator ...................................................................................... 37
Figure 5-4 Static VTC.................................................................................................................. 38
Figure 5-5 Transient Behavior of CDC Quantization Inverters................................................... 39
Figure 5-6 Small-Signal Model of CDC Quantization Inverters ................................................. 43
Figure 5-7 Diagram for Matlab Analysis..................................................................................... 45
Figure 5-8 Ids, Co1, Cin, Slew-Rate Vs. NMOS width at Vm = 0.484v .......................................... 46
Figure 5-9 Comparison of Vo1 Rising Speeds with Vm=0.484v and Various Ids ........................... 47
Figure 5-10 Comparison of Vo1 Falling Speeds with Vm=0.484v and Various Ids ........................ 48
Figure 5-11 Comparison of ADC SFDR for Optimization of Ids ................................................. 51
Figure 6-1 Architecture of CDC-based Pipelined ADC with Direct-Binary Encoding ............... 54
Figure 6-2 Architecture of CDC-based Pipelined ADC with Gray Encoding ............................. 55
Figure 6-3 Timing Diagram of CDC-based Pipelined CMOS Flash ADC.................................. 56
Figure 6-4 4-b Direct-Binary Balanced Encoder ......................................................................... 59
Figure 6-5 Pipelined Encoding of Thermometer-to-Gray Code .................................................. 61
Figure 6-6 Pipelined Encoding of Gray-to-Binary Code............................................................. 62
Figure 6-7 Clocked DCVSPG AND/NAND Gate ....................................................................... 63
Figure 6-8 Clocked DCVSPG OR/NOR Gate............................................................................. 63
Figure 6-9 Clocked DCVSPG XOR/XNOR Gate ....................................................................... 64
Figure 6-10 Clocked DCVSPG Buffer ........................................................................................ 64
Figure 6-11 Performance of Clock Tree ...................................................................................... 66
Figure 7-1 Schematic of 4-b 1.25-GHz Bandwidth 2.5-GSPS ADC ........................................... 69

Figure 7-2 Schematic of TGB 4-b Encoder ................................................................................. 70
Figure 7-3 Schematic of Gray-to-Binary Encoding..................................................................... 70
Figure 7-4 Schematic of Clock Tree for a 4-b ADC .................................................................... 71
Figure 7-5 Schematic of 15 CDC Comparators........................................................................... 72
Figure 7-6 Outputs of 15 Quantization Inverters at DC .............................................................. 73
Figure 7-7 Outputs of CDC Comparators at 100MHz Sinusoidal Signal.................................... 74
Figure 7-8 Reconstructed Signal and Spectrum of 9.766MHz Signal......................................... 74
Figure 7-9 Spectrum of 250MHz Signal...................................................................................... 75
vii
Figure 7-10 Spectrum of 952 MHz signal ................................................................................... 76
Figure 7-11 Spectrum of 1.248GHz Signal ................................................................................. 76
Figure 7-12 SFDR and SNDR vs. Input Frequencies .................................................................. 77
Figure 7-13 ENOB vs. Input Frequencies ................................................................................... 77
Figure 7-14 SFDR Comparison of three ADCs ........................................................................... 78
Figure 7-15 SNDR Comparison of two ADCs ............................................................................ 79
Figure 7-16 Layout of the ADC................................................................................................... 81
Figure 7-17 Outputs of 15 Quantization Inverters at DC Post Layout Simulation...................... 82
Figure 7-18 Reconstructed Signal and Spectrum of 9.8MHz signal............................................ 83
Figure 7-19 Spectrum of 125MHz Signal.................................................................................... 84
Figure 7-22 SFDR and SNDF vs. Input Frequencies .................................................................. 86
Figure 7-23 SFDR and SNDR Comparison between Schematic and Layout.............................. 87
Figure 7-24 ENOB Comparison between Schematic and Layout ............................................... 88
Figure 7-25 Schematic of 4-b 2-GHz Bandwidth 4-GSPS ADC ................................................. 91
Figure 7-28 Spectrum of 1.6GHz Signal ..................................................................................... 93
Figure 7-31 SFDR and SNDR vs. Input Frequencies .................................................................. 95
Figure 7-32 ENOB vs. Input Frequencies ................................................................................... 96
Figure 7-33 Schematic of 6-b 2.5GSPS ADC.............................................................................. 99
Figure 7-34 Schematic of 6-b TGB Encoder ............................................................................. 100
Figure 7-35 Schematic of 6-b Gray-to-Binary Encoding .......................................................... 101
Figure 7-36 63 CDC Comparators............................................................................................. 102
Figure 7-37 Schematic of Clock Tree for 6-b ADC................................................................... 103
Figure 7-38 Outputs of 63 Quantization Inverters at DC .......................................................... 104
Figure 7-39 Outputs of 6 bits at DC .......................................................................................... 105
Figure 7-40 Spectrum of 12.2MHz Signal................................................................................. 106
Figure 7-41 Reconstructed Signal and Spectrum of 11.7MHz signal........................................ 107
Figure 7-42 Performance Comparison of the ADC with 2.5-GSPS .......................................... 110
Figure 7-43 Performance Comparison of the ADC with 4-GSPS ............................................. 111
Figure 8-1 AMS Verification Flow of Digital Receiver ............................................................ 113

Figure 8-2 Diagram of DEMUX................................................................................................ 114
Figure 8-3 Sixteen 6.4ns Pulse Signals...................................................................................... 115
Figure 8-4 State Diagram of Pulse Signals ................................................................................ 115
Figure 8-5 Bin and Peak Amplitude of 1125MHz Signal.......................................................... 116
Figure 8-6 1st and 2nd Peak Amplitude of 700MHz and 1GHz .................................................. 117
Figure 9-1 Spectrum of 400MHz Signal with -40°C................................................................. 120

Figure 9-2 Spectrum of 400MHz Signal with 25°C .................................................................. 120
Figure 9-3 Spectrum of 400MHz Signal with 75°C .................................................................. 121
Figure 9-4 Spectrum of 400MHz Signal with 140°C ................................................................ 121
Figure A-1 Estimation of Source and Drain Areas and Peripheries........................................... 122
viii
List of Tables
Table 1-1 Initial Requirements of ADC for Digital Receiver ........................................................ 4
Table 1-2 Achieved Performance of ADC for the Digital Receiver .............................................. 5
Table 3-1 Comparison to State-of-the-art GHz Flash ADCs ....................................................... 19

Table 3-2 Comparison to Flash ADCs with Inverter Comparator ............................................... 20
Table 5-1 Comparison of Switching Speeds of Vm = 0.484v and 6 different Ids .......................... 49
Table 5-2 Comparison of Switching Speeds for Various Vm ........................................................ 50
Table 6-1 Relation between Input Voltage Range and 3-dB Bandwidth of CDCs ...................... 57
Table 7-1 Dynamic Performance Improvement Rate of the ADC ............................................... 80

Table 7-2 Performance Comparison of Schematic and Layout ................................................... 86
Table 7-3 Dynamic Performance Degradation Rate of the Layout.............................................. 89
Table 7-4 Dynamic Performance Parameters of Various Frequency Signals .............................. 92
Table 7-5 Comparison with 4-b Flash ADCs in Literature .......................................................... 97
Table 7-6 Performance Comparison of 6-b Flash ADC............................................................. 108
Table 9-1 Temperature variation on SFDR analysis of 4-b 2.5-GSPS CDC-based ADCs with input
signal frequency of 400 MHz..................................................................................... 119
ix
Acknowledgements
I am grateful to many people who supported, encouraged and guided me during the
dissertation research work. My most sincere gratitude belongs to my dissertation advisor,
Prof. Chien-In Henry Chen, for his guidance and support throughout this endeavor. His
good insight on my dissertation research is invaluable, and he has been providing full
support on the research source. I also thank him for his constant encouragement and
patience throughout the entire research period. This doctoral research experience would
be a special journey in my professional life.
I would like to sincerely thank Prof. Raymond Siferd for taking me as an IC design
research assistant at the first place of my doctoral study and teaching me the analog
circuit design. I also thank Prof. Marian Kazimierczuk and Prof. Jack Jean for their
encouragement and guidance during my graduate study. I am truly grateful to Prof.
Wen-Ben Jone, Prof. Marian Kazimierczuk, Prof. Raymond Siferd and Prof. Jack Jean for
willing to serve on my dissertation committee.
I thank all the colleagues in the VLSI research lab for sharing and discussion. Mike
Myers deserves a special thank for helping me at the beginning of my research in the VLSI
lab, and also with design layout in the end. Without his help, my ADC layout would not be
completed successfully in that short time.
I extend my acknowledgements to Sheila Hollenbaugh and the Department of
x
Electrical Engineering for providing me all the necessary technical support required for the
successful completion of this dissertation. I would also like to thank the Engineering Ph. D.
Program for the financial support.
I am most grateful to my family, my husband and daughter, my mom, my brothers and
sisters for their love and support during my doctoral study. The most special gratitude goes
to my husband, Li, for teaching me technical writing and organizing the research, and also
taking care of our daughter, Jiechen, when I was not there. Without him, I would never get
to this point.
xi
Dedicated to
My husband and our daughter, Li and Jiechen.
xii
Chapter 1 INTRODUCTION
1.1 Background
Analog-to-digital converters (ADCs) are electronic circuits that convert continuous
electric signals into discrete digital numbers for signal analysis or signal transmission.
ADCs are characterized primarily by conversion speed, resolution, power and area
consumption, which vary with a variety of applications. In addition, selection of an ADC
for an individual application is essential for cost effectiveness.
With higher-level integration driven by increasingly complex digital systems and
downscaling processes available, system-on-a-chip (SoC) is an emerging technology for
low power-consumption, high cost effectiveness, and high reliability. SoC is in great
demand for wireless and wideband communication systems which require high-speed data
conversion, especially consumer electronic devices. SoC integrates all components of
electronic systems into a single integrated circuit containing digital, analog, and
mixed-signal functions on one chip. A high-speed A/D converter becomes an integral part
of SoC products.
Generally three types of solid state technologies are available for A/D converter
implementation. They are Gallium Arsenide (GaAs), Silicon Germanium (SiGe) and
1
Silicon (Si), and of the three GaAs is the most and Si is the least expense process. As to
the Si process the CMOS Si, unlike the BiCMOS Si using high power consumption bipolar
devices, uses low-power NFET and PFET devices which makes CMOS mixed-signal/SoC
become an emerging technology in the semiconductor industry.
However, shrinking the feature size of the semiconductor technology makes
high-speed high-performance ADC design quite challenge in a standard CMOS technology,
due to the reduced effective voltage headroom and the deteriorated linearity of transistor
device in the small feature size technology. The semiconductor technology is now
approaching the 45 nanometer feature size, pushing development of SoC applications to a
new milestone.
Giga-sample-per-second (GSPS) flash-based ADCs in CMOS technology were
reported [1]-[3]. Although they had improved the conversion speed by using
time-interleaving, the conversion precision by averaging offset, or the effective resolution
bandwidth (ERBW) by interpolating and folding, etc., the sample rate is still limited by 2
GHz. Besides, these ADCs are not suitable for SoC due to noise effect on the analog
components, and high power consumption. We need a robust ADC architecture to
minimize substrate noise in a SoC core and has as few analog nodes and components as
possible [4].
2
1.2 Initial Research Requirements
The initial objective of this research is to investigate and design a high-speed,
low-power, and low-voltage CMOS A/D converter for use in a 2.5 GSPS, 1 GHz wideband
digital receiver on a chip, as shown in Figure 1-1. The receiver is to produce a low cost
(fewer devices and less PCB area), small and lightweight (130 nanometers CMOS) and
low power (less than 2 W) SoC for correctly processing two simultaneous signals (in a
frequency range between 125 and 1125 MHz) by detecting their frequency, pulse width
(PW), and time of arrival (TOA). The design of digital receiver is divided into two areas: 1)
signal sampler and formatting and 2) super resolution and frequency measurement [5].
Figure 1-1 Digital Receiver SoC [5]
Then the requirements of ADC for the digital receiver are shown in Table 1-1. To
process two simultaneous signals with maximum instantaneous dynamic range (IDR), the
digital receiver requires the embedded ADC with high spur-free-dynamic-range (SFDR).
3
Table 1-1 Initial Requirements of ADC for Digital Receiver
1.3 Dissertation Research Summary
The research goal is to investigate and design a high-speed, low-power, low-voltage
flash CMOS ADC for 1 GHz bandwidth digital receiver on a chip with a high two-signal
instantaneous dynamic range (IDR). The research is accomplished by proposed
CDC-based pipelined CMOS flash ADC architecture, dynamic offset suppression
technique, and circuit optimization. The performance of a 4-b CDC-based pipelined ADC
is summarized in Table 1-2.
4
Table 1-2 Achieved Performance of ADC for the Digital Receiver
Using a 2.5 GHz sampling rate, the ADC achieves a high spurious-free dynamic range
(SFDR) of 26 dB at a Nyquist frequency signal of 1.248 GHz. After the sampling rate
increases to 4 GHz, the ADC achieves a SFDR of 24 dB at a Nyquist frequency signal of
1.997 GHz. The proposed ADC is suitable for applications in wideband communication
SoC.
1.4 Dissertation Layout
After an overview of ADC fundamentals in chapter 2, where examples and the
state-of-the-art implementations are cited, chapter 3 reviews ADCs in the literature and
chapter 4 discusses high speed ADCs in wideband receivers. In chapter 5 a new digital
clocked comparator (CDC) is proposed and coupled with dynamic offset suppression
technique and circuit optimization to improve dynamic performance of ADC. A
5
CDC-based pipelined flash ADC architecture is then proposed in chapter 6. Chapter 7
presents implementations and experimental results of three CDC-based pipelined flash
ADCs with different design requirements in 130 nanometer (nm) digital CMOS process.
The CDC-based pipelined ADCs are compared with the ADCs in literature. Chapter 8
presents an application of a 4-b CDC-based pipelined flash ADC in a wideband digital
receiver with 2.5 GSPS and 1 GHz bandwidth. A block-level post-design verification flow
for the receiver has been established in Cadence analog/mixed-signal (AMS) platform.
Interface hardware and down-conversion between ADC and DSP is presented.
Conclusions and the future work are discussed in chapter 9.
6
Chapter 2 ADC FUNDAMENTALS
When an ADC converts analog signals into digital signals, it converts the continuous
values into the discrete values both in time and amplitude. The process converting signals
from continuous time to discrete time is called sampling with a sampling frequency fsampling.
fsampling is one of the primary characteristics of ADC and represents the conversion speed of
ADC. The other process converting signal amplitude from continuous voltages into
discrete voltages is called quantization with a resolution N. N is another primary
characteristic and represents the conversion precision of ADC. The sampling usually
precedes the quantization in the conversion process of the conventional low-speed ADC
designs, while in some high speed ADC designs two actions can be mixed or are
commutative [7].
The performance characteristics of ADCs are classified into the static performance
and the dynamic performance. The static performance includes offset, gain mismatch,
integral non-linearity (INL) and differential non-linearity (DNL) errors, etc. The dynamic
performance includes signal to noise ratio (SNR), signal to noise and distortion ratio
(SINAD), effective number of bits (ENOB), spurious-free dynamic range (SFDR) and total
harmonic distortion (THD), etc. Definitions and principles of primary characteristics and
calculation of performance parameters are discussed in the following sections.
7
2.1 Primary Characteristics
2.1.1 Sampling Frequency
An analog signal is sampled at regularly-spaced time intervals T. The discrete
samples of xa(t) are denoted by x(n) = xa (nT ) with − ∞ < n < ∞ where x(n) is the
discrete-time sample of the continuous-time analog signal xa(t) every T seconds. The
sampling frequency fsamping is defined as the reciprocal of the time interval T, as
f sampling = 1 and is so called the sampling rate as well with dimensions of samples per
T
second. If a continuous-time sinusoidal signal is xa (t ) = A cos(2πft + θ ) with
− ∞ < t < +∞ and − ∞ < f < +∞ , where A is the amplitude of the sinusoid, f is the signal
frequency in hertz, and θ is the phase in radian, its discrete-time sinusoidal signal can be
expressed as x(n) = A cos(2πfnT + θ ) = A cos(ωn + θ ) with ω = 2π f in radian

f sampling
per sample.
How to select the sampling frequency fsamping? According to the characteristic of
discrete-time sinusoids whose frequencies are separated by an integer multiple of 2π are
identical, e.g., cos[(ω0 + 2π )n + θ ] = cos(ω0 n + θ ) . The sequences of any two
discrete-time sinusoids with frequencies only in the range − π ≤ ω ≤ π are distinct. Thus
the analog signals have to be equal or smaller than half of the sampling frequency as
− 12 f sampling ≤ f ≤ 1
2 f sampling (2-1)
To reconstruct signals back unambiguously without aliasing, the sampling frequency
has to be equal or greater than twice of the frequency bandwidth of analog signals. This is
Nyquist-Shannon sampling Theorem [8].
8
2.1.2 Resolution
Quantization converts signal amplitude from continuous voltages into discrete
values by dividing a full-scale signal voltage into 2N-1 sub-range where N is the resolution
of ADC. The resolution N represents the expected conversion precision of ADC. The
effective conversion precision is decreased due to various noises. A primary noise source in
data conversion is quantization error.
Figure 2-1 N = 3 Quantization Steps
Quantization inherently adds noise into digitized signals. Figure 2-1 presents
quantization steps for a resolution of N = 3. The full-scale amplitude of analog signal is
divided into 7 sub-ranges. Any voltage in a sub-range between every two steps is rounded
to the closed step. Thus, quantization unavoidably results in a loss of information and is
presented as the quantization noise.
Quantization error Q is one step size VLSB and generally considered as a random
9
variable with a uniform distribution. The error density function fQ(x) is 1
V LSB
in the range
[- VLSB
2
, V LSB
2
] as shown in Figure 2-2.
1
V LSB
V LSB V LSB
−
2 2
Figure 2-2 Uniform Distribution of Quantization Error
To approximate the quantization noise, the signal-to-noise ratio (SNR) is calculated
by comparing the signal power over the quantization noise power. The root-mean-square
V LSB
(rms) value of the quantization noise is VQ rms = [ ∫
1
V
2
x 2 V LSB
1
dx ] 2 =
V LSB
12
where
− LSB
2
V FS
VL SB = 2N
.
cos(Ωt + θ ) with a full-scale voltage, the rms value

V FS
For a sinusoidal signal 2
1
2π
is Vin rms = ⎡ 21π ⋅ ∫ ( ⋅ cos(Ωt + θ ) 2 dΩt ⎤ =
2
V FS V FS
. The signal-to-noise ratio (SNR) of ADC
⎢⎣ 0 2 ⎥⎦ 2 2
is the ratio of the rms value of signal to the rms value of the quantization noise.
Vin rms
SNR = 20 log10 ( ) = 6.02 N + 1.76(dB) (2-2)
VQ rms
Thus the ideal SNR of an N-b ADC is 6.02N + 1.76 dB as shown in Equ. (2-2). For
example, a 4-b ADC has an ideal SNR of 25.84 dB.
10
2.2 Performance Characteristics
Performance characteristics of ADCs [9, 10] presented in this section aims at giving
an evaluation metric of ADCs.
2.2.1 Static Performance
2.2.1.1 Offset and Gain Error
Offset is a constant difference between the actual finite resolution characteristic and the
ideal finite resolution characteristic measured at any vertical jump. Gain Error is the
difference between the actual finite resolution and an infinite resolution characteristic
measured at the rightmost vertical jump. It is proportional to the magnitude of ADC input
voltage. In conventional comparison of ADC performance, the sampling speed is assumed
for all input voltage due to the linearity of circuits, however, a high input voltage results in
a faster response than does a low input voltage which eventually results in an ADC gain
error.
2.2.1.2 Integral Non-Linearity and Differential Non-Linearity
Integral nonlinearity (INL) is the maximum difference between the actual finite
resolution characteristic and the ideal finite resolution characteristic measured vertically. It
can be expressed as a percentage of the full scale range or in terms of the least significant
bit (LSB).
Differential Nonlinearity (DNL) is a measure of the separation between adjacent levels
measured at each vertical jump. It measures bit-to-bit deviations from ideal output steps
11
and can be expressed in terms of the LSB as shown in Equ. (2-3).
'
Vk' +1 − Vk
DNL(k ) = − 1LSB (2-3)
VLSB
Equ. (2-3) is used to calculate the DNL for each quantization level and VLSB is one
voltage step size and equal to VFS (2 N − 2) in flash ADCs. V’k+1 and V’k are adjacent
actual voltage levels. The maximum DNL characterizes the differential nonlinearity of the
ADCs.
2.2.2 Dynamic Performance
2.2.2.1 Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio of the signal power to the total noise power
at the output usually measured for a sinusoidal input. It is expressed in decibel (dB) as the
following equation [11]:
⎛A ⎞
SNR = 20 log10 ⎜⎜ rms , signal ⎟
⎟ (2-4)
⎝ Arms , noise ⎠
where Arms,signal and Arms, noise are the root mean square of the amplitude for the signal and
noise, respectively. The SNR can also be calculated as the signal fundamental spectrum in
dB minus the sum of all the noise spectra excluding the significant harmonics.
2.2.2.2 Signal-to-Noise-and-Distortion Ratio
The signal-to-noise-and-distortion ratio (SNDR) is the ratio of the signal power to the
12
total noise power and harmonics power at the output when inputting a sinusoid.
Mathematically the SNDR is formalized as the following [12]
⎛ Arms , signal ⎞
SNDR = 20 log10 ⎜⎜ ⎟
⎟ (2-5)
⎝ Arms , noise + harmonics ⎠
where Arms, signal and Arms, noise+harmonics are the rms of the signal amplitude and the
rms of all the noise amplitudes and all the harmonic amplitudes. According to the SNR in
Equ. (2-2), the performance parameters SNR and SNDR are both up-bounded at
6.02N+1.78 dB.
2.2.2.3 Effective Number of Bits
The effective number of bits (ENOB) is defined by the following equation [15]:
SNDR − 1.78dB
ENOB = (2-6)
6.02
In the Nyquist ADC, the ENOB is smaller than the resolution N of ADC, while with
noise-shaping technique, the over-sampling ADC may achieve an ENOB higher than the
resolution N. The ADC architectures are reviewed and discussed in the next chapter.
2.2.2.4 Spurious-Free Dynamic Range
The spurious-free dynamic range (SFDR) is the ratio of the signal power to the largest
harmonic power, or the power of the highest spur if the power of the highest spur is greater
than the largest harmonic power. It can be expressed as
13
⎛ Arms , signal ⎞
SFDR = 20 log10 ⎜ ⎟ (2-7)
⎜ A nd ⎟
⎝ rms , 2 harmonic / highestSpur ⎠
The SFDR performance shows the dynamic range of an ADC. In [13] and [14], an
empirical equation for the SFDR was derived as
SFDR ≈ 9 N − c (2-8)
where N is the resolution of the ADC, c is the offset ranges from 0 for low resolution and 6
for high resolution [24].
2.2.2.5 Total Harmonic Distortion
The total harmonic distortion (THD) is the ratio of the total significant harmonic power
over the signal power. The THD can be expressed as
⎛A ⎞
THD = 20 log10 ⎜ rms , harmonics ⎟ (2-9)
⎜ A ⎟
⎝ rms , signal ⎠
14
Chapter 3 ADC LITERATURE REVIEW
The literature review is intended to provide information to understand the context of
this research. Following a brief overview of ADC architectures, high speed flash ADCs are
surveyed and the performances of state-of-the-art flash ADCs are discussed. At the end of
this chapter, flash ADCs using inverter comparator configuration for SoC applications are
discussed.
3.1 Architecture Overview
As the primary characteristics, the precision and speed in data conversion determine
the selection of ADC architectures for a specific application. ADC precision and speed, in
terms of resolution and sampling frequency, is shown in Figure 3-1 [16]. Sigma-Delta
ADCs have the highest resolution but the lowest sampling frequency; flash ADCs have he
highest sampling frequency but the lowest resolution. The resolution and the sampling
frequency for successive approximation register (SAR) ADCs and pipelined ADCs are in
the between.
15
Figure 3-1 Resolution N vs. Sampling Frequency fsampling
The primary characteristics of the ADC architectures determine their applications. The
Sigma-Delta ADCs adopt over-sampling and noise shaping techniques to increase the SNR
by pushing low-frequency noise to higher frequencies which is out of the interest
bandwidth. The Sigma-Delta ADCs have features of low-bandwidth, high-resolution and
are particularly suitable for applications of precision measurement. The SAR ADCs use
one comparator over many cycles to conduct its conversion. They are often used at lower
speed, high resolution applications like industrial control and battery-powered applications.
The pipelined ADCs divide the conversion task into several consecutive stages to achieve
high resolution than the flash ADCs. The pipelined ADCs are often applied to high speed,
low resolution applications such as Video, HDTV, and Medical & CCD Imaging. The
flash ADCs convert the signal in one cycle by parallelizing all comparators to achieve fast
16
conversion speed. They are often used in high speed applications like high-density disk
drives, wireless communications, wideband satellite receivers, etc. In general, power
consumption and silicon area of the flash ADCs increases with the increase of signal
bandwidth.
3.2 High Speed ADC in Literature
Vin
Vref1 Comp .
N-b outputs
Vref2 Comp . Encoder
Comp .
Vrefn
Figure 3-2 Flash ADC Architecture
A general architecture of flash ADC is presented in Figure 3-2. In an N-bit flash ADC,
2N-1 reference voltages and comparators are used to convert the analog input signal into a
thermometer digital output signal. Commonly, the reference voltages are provided by a
2N-1-resistor ladder and the thermometer-code output is converted into a binary code by a
thermometer-to-binary encoder.
A full flash architecture, in principle, does not need an explicit front-end
sample-and-hold circuit and its performance is determined primarily by its constituent
17
comparators [9]. Since comparators do not require linear amplification and typically
achieve a higher speed than sample-and-hold amplifiers (SHA), flash ADCs can operate
faster than those that demand front-end SHA [9]. Since the number of comparators
grows exponentially with the resolution, these ADCs have excessively large input
capacitance, power and area consumption, and different comparator offset voltages. In
addition, lack of a front-end sample-and-hold amplifier makes the converter vulnerable to
sparkles and slew-dependent sampling points.
Full flash ADCs employ parallelism and “distributed” sampling to achieve a high
conversion speed with a simple architecture, but the resolution is limited when its sampling
frequency reaches several giga-hertz [35]. A few of circuit techniques have been
proposed to improve the resolution while maintaining a one-step conversion without using
sample-and-hold circuits. Folding and interpolation techniques were proposed to increase
the effective input bandwidth by reducing the number of comparators but the architecture
becomes complicated [17-23] [36]. Averaging technique was proposed to improve the
performance of the resolution and the DNL error by suppressing the output offsets of
comparators by scarifying the input signal dynamic range due to dummy comparators [1]
[3] [24-26] [29-31]. Time-interleaved technique was proposed to increase the sampling
frequency by parallelizing ADCs but the high nonlinearity mismatch noise requires an
elaborate digital calibration system [32-34].
18
Table 3-1 Comparison to State-of-the-art GHz Flash ADCs
The performances of state-of-the-art GHz flash ADCs are compared in Table 3-1. The
effective resolution bandwidth (ERBW) is limited by 1000 MHz (1GHz), although the
sampling rate reaches 4 GHz. The input capacitance, power and area consumption increase
as the ERBW increases.
3.3 Flash ADCs Using Inverter Comparator for SoC
In recent years, with technology processes continuously scaling-down and SoC
technique becoming feasible, high-performance low-voltage ADCs are in demand. The
19
low-voltage ADCs with comparators in a simple inverter configuration particularly
suitable for SoC are reported.
Segura et al. in 1998 [35] suggested that an inverter could be used as an analog
comparator. Tangel in 1999 [36] first proposed using threshold inverter quantization (TIQ)
technique for comparator design in CMOS flash ADCs. An 1-GSPS CMOS flash ADCs
for SoC application was reported in 2001 [16][37]. Thereafter, a number of inverter-based
ADCs with emphasis on optimization of comparators were reported [38]-[43]. Some of
their performances are shown in Table 3-2.
Table 3-2 Comparison to Flash ADCs with Inverter Comparator
In [37] and [39], the ADCs were reported with emphasis on static performance of INL
and DNL. Using random size variation (RSV) and systematic size variation (SSV)
techniques to optimize the comparators improves the static performance of ADCs. The
ADC in [40] was designed with random sizing method and achieved a SFDR of 9 dB with
20
an input signal frequency of 1 GHz. The ADC in [41] was designed by consideration of
dynamic offset suppression and achieved a SFDR of 19.81 dB with an input signal
frequency of 1.25 GHz. Their ADC performances are summarized in Table 3-2.
Flash ADCs with inverter comparator in Table 3-2, compared with flash ADCs in
Table 3-1, have comparatively higher sampling rate, low power and area consumption, and
using smaller feature size technologies.
21
Chapter 4 HIGH-SPEED ADCS IN WIDEBAND RECEIVERS
In wideband communication systems, an ADC in receivers digitizes several channels
of strong and weak signals simultaneously. A digital signal processor (DSP) subsequently
detects each channel. First, the input dynamic range is an important performance
parameter for communication receivers. The ADC is desired to have high-speed data
conversion and high input dynamic range [45]. Usually, the SFDR of ADCs limit
wideband receiver sensitivity, not the SNR [44][46]. Therefore a design objective of
ADC for wideband communications is to increase the SFDR by lowering the spur and
noise floor therefore the weak legitimate signals can be detected. Secondly, the wide
bandwidth requires a high conversion rate in the ADC design by Nyquist theorem. The
flash ADC architecture is commonly used without external sample-and-hold (S/H) and has
distributed sampling on high-speed comparators for giga-hertz input signals. The sparkles
in thermometer code, meta-stability, and signal slew rate limitation will generate spurious
code and odd harmonics in the digital output [9][51]. Engineers have to consider all
these issues for a good ADC design in wideband communication systems.
22
4.1 Spurs in Spectrum
The spurious-free dynamic range (SFDR) must be sufficiently high so that weak
signals are not covered in the spurious-floor. The SFDR of the ADC is defined as the
difference in decibels (dB) between the full-scale fundamental and the maximum spurious
tone including harmonics in the output spectrum. The signal-to-noise ratio (SNR) is
relatively less important here [46].
To understand the spurs in the output spectrum, we look at the discrete Fourier
transform (DFT) as the following:
N −1
X (k ) = ∑ x(n)e − j 2πnk / N (4.1)
n =0
where x(n) is the sampled output of ADC, N is the total number of samples, and X(k) is the
output spectrum power in real-imaginary domain with k ranging from 1 to N. Ideally, X(k)
is zero at the non-signal points and non-zero at the signal point. This is illustrated by an
example of 1-GSPS ADC at an input signal frequency of 125 MHz signal using an 8-point
DFT. Both time and frequency domain data are depicted in Figure 4-1.
23
Figure 4-1 Time and frequency domain data using an 8-point DFT
For a periodic signal, ideal samples are [0, a, b, a, 0, -a, -b, -a] as shown Figure 4-1
(a). We take those samples into Equ.(4.1) and get Equ.(4.2) with W nk = e − j 2πnk / N for
simple expression.
⎡ X (0) ⎤ ⎡1 1 1 1 1 1 1 1 ⎤ ⎡ x(0) = 0 ⎤
⎢ X (1) ⎥ ⎢1 W1 W2 W3 W4 W5 W 6
W 7 ⎥⎥ ⎢⎢ x(1) = a ⎥⎥
⎢ ⎥ ⎢
⎢ X (2)⎥ ⎢1 W2 W4 W6 W8 W 10 W 12 W 14 ⎥ ⎢ x(2) = b ⎥
⎢ ⎥ ⎢ ⎥⎢ ⎥
⎢ X (3) ⎥ = ⎢1 W3 W6 W9 W 12 W 15 W 18 W 21 ⎥ ⎢ x(3) = a ⎥
⎢ X (4)⎥ ⎢1 W4 W8 W 12 W 16 W 20 W 24 W 28 ⎥ ⎢ x(4) = 0 ⎥ (4.2)
⎢ ⎥ ⎢ ⎥⎢ ⎥
⎢ X (5) ⎥ ⎢1 W 5 W 10 W 15 W 20 W 25 W 30 W 35 ⎥ ⎢ x(5) = − a ⎥
⎢ X (6) ⎥ ⎢1 W 6 W 12 W 18 W 24 W 30 W 36 W 42 ⎥ ⎢ x(6) = −b ⎥
⎢ ⎥ ⎢ ⎥⎢ ⎥
⎢⎣ X (7)⎥⎦ ⎢⎣1 W 7 W 14 W 21 W 28 W 35 W 42 W 49 ⎥⎦ ⎢⎣ x(7) = − a ⎥⎦
24
Because of symmetry and periodicity property of DFT, which are W Nnk = −W Nnk + N / 2
and W Nnk = W Nnk + N , Equ.(4.2) is simplified to Equ.(4.3).
⎡ X (0) ⎤ ⎡1 1 1 1 1 1 1 1 ⎤⎡ 0 ⎤
⎢ X (1) ⎥ ⎢1 W 1 W2 W3 −1 −W 1 −W 2 − W 3 ⎥⎥ ⎢⎢ a ⎥⎥
⎢ ⎥ ⎢
⎢ X (2)⎥ ⎢1 W 2 −1 −W 2 1 W2 −1 −W 2 ⎥⎢ b ⎥
⎢ ⎥ ⎢ ⎥⎢ ⎥
⎢ X (3) ⎥ = ⎢1 W
3
−W 2 W1 −1 −W 3 W2 −W 1 ⎥⎢ a ⎥
⎢ X (4)⎥ ⎢1 − 1 1 −1 1 −1 1 −1 ⎥⎢ 0 ⎥ (4.3)
⎢ ⎥ ⎢ ⎥⎢ ⎥
⎢ X (5) ⎥ ⎢1 − W −W 3 −1 W 1 −W 2 W 3 ⎥ ⎢− a ⎥
1
W2
⎢ X (6) ⎥ ⎢1 − W 2 −1 W2 1 −W 2 −1 W 2 ⎥ ⎢− b⎥
⎢ ⎥ ⎢ ⎥⎢ ⎥
⎣⎢ X (7)⎦⎥ ⎣⎢1 − W −W 2 −W 1 −1 W 3 W 1 ⎦⎥ ⎣⎢− a ⎦⎥
3
W2
The values of X(k) are calculated in Equ.(4.4). X(1) and X(7) are signal-point and
symmetry, while the rest are non-signal points and equal to zero, shown in Equ.(4.4) and
in Figure 4-1 (b).
⎡ X (0) ⎤ ⎡ 0 ⎤
⎢ X (1) ⎥ ⎢ 2a (W 1 + W 3 ) + 2bW 2 ⎥
⎢ ⎥ ⎢ ⎥
⎢ X ( 2)⎥ ⎢ 0 ⎥
⎢ ⎥ ⎢ ⎥
⎢ X (3) ⎥ = ⎢ 0 ⎥
⎢ X ( 4)⎥ ⎢ 0 ⎥ (4.4)
⎢ ⎥ ⎢ ⎥
⎢ X (5) ⎥ ⎢ 0 ⎥
⎢ X (6) ⎥ ⎢ 0 ⎥
⎢ ⎥ ⎢ ⎥
⎣⎢ X (7)⎦⎥ ⎣⎢− 2a (W + W ) − 2bW ⎦⎥
1 3 2
For non-ideal case of sampling as shown in Figure 4-2 (a), the samples can be [∆0,
a+∆1, b+∆2, a+∆3, ∆4, -a+∆5, -b+∆6, -a+∆7], where ∆i is an offset from its ideal value
resulting from error sources, sparkles or meta-stability, for instances.
25
Figure 4-2 8-point DFT with Spurs
Putting the offset samples into Eqn.(4.3) as shown in Equ.(4.5), we can see that X(k)
at non-signal points are not zero and completely determined by the offsets, while X(k) at
signal points are modified by the offset in the samples, shown in Equ.(4.6).
⎡ X (0) ⎤ ⎡1 1 1 1 1 1 1 1 ⎤⎡ ∆ 0 ⎤
⎢ X (1) ⎥ ⎢1 W 1
⎢ ⎥ ⎢ W2 W3 −1 −W 1 −W 2 − W 3 ⎥⎥ ⎢⎢ a + ∆ 1 ⎥⎥
⎢ X (2)⎥ ⎢1 W 2 −1 −W 2 1 W2 −1 − W 2 ⎥⎢ b + ∆ 2 ⎥
⎢ ⎥ ⎢ ⎥⎢ ⎥
⎢ X (3) ⎥ = ⎢1 W
3
−W 2 W1 −1 −W 3 W2 − W 1 ⎥⎢ a + ∆3 ⎥
(4.5)
⎢ X (4)⎥ ⎢1 − 1 1 −1 1 −1 1 −1 ⎥⎢ ∆ 4 ⎥
⎢ ⎥ ⎢ ⎥⎢ ⎥
⎢ X (5) ⎥ ⎢1 − W
1
W2 −W 3 −1 W1 −W 2 W 3 ⎥ ⎢− a + ∆ 5 ⎥
⎢ X (6) ⎥ ⎢1 − W 2 −1 W2 1 −W 2 −1 W 2 ⎥ ⎢− b + ∆ 6 ⎥
⎢ ⎥ ⎢ ⎥⎢ ⎥
⎢⎣ X (7)⎥⎦ ⎢⎣1 − W
3
−W 2 −W 1 −1 W 3 W2 W 1 ⎥⎦ ⎢⎣− a + ∆ 7 ⎥⎦
26
⎡X(0)⎤ ⎡ ∆0 + ∆1 + ∆2 + ∆3 + ∆4 + ∆5 + ∆6 + ∆7 ⎤
⎢ X(1) ⎥ ⎢ 2a(W1 +W3 ) + 2bW2 + (∆ − ∆ ) + (∆ − ∆ )W1 + (∆ − ∆ )W 2 + (∆ − ∆ )W3 ⎥
⎢ ⎥ ⎢ 0 4 1 5 2 6 3 7 ⎥
⎢X(2)⎥ ⎢ (∆0 − ∆2 + ∆4 − ∆6 ) + (∆1 − ∆3 + ∆5 − ∆7 )W 2
⎥
⎢ ⎥ ⎢ ⎥
⎢ X(3)⎥ = ⎢ (∆0 − ∆4 ) + (∆3 − ∆7 )W + (∆6 − ∆2 )W + (∆1 − ∆5 )W
1 2 3
⎥ (4.6)
⎢X(4)⎥ ⎢ ∆0 − ∆1 + ∆2 − ∆3 + ∆4 − ∆5 + ∆6 − ∆7 ⎥
⎢ ⎥ ⎢ ⎥
⎢X(5)⎥ ⎢ (∆0 − ∆4 ) + (∆5 − ∆1 )W1 + (∆2 − ∆6 )W 2 + (∆7 − ∆3 )W3 ⎥
⎢X(6)⎥ ⎢ (∆0 − ∆2 + ∆4 − ∆6 ) −(∆1 − ∆3 + ∆5 − ∆7 )W 2 ⎥
⎢ ⎥ ⎢ ⎥
⎣⎢X(7)⎦⎥ ⎣⎢− 2a(W +W ) − 2bW + (∆0 − ∆4 ) + (∆7 − ∆3 )W + (∆6 − ∆2 )W + (∆5 − ∆1 )W ⎦⎥
1 3 2 1 2 3
Those non-zeros X(k) at non-signal points appear as the spurs in spectrum domain as
shown in Figure 4-2 (b).
To lower the spurious-floor in ADC design, the offsets (∆i) need to be suppressed.
The offsets ∆i can be static offsets, dynamic offsets or the sum of them. They may be
characterized as random or mutual correlated. The random offset of ∆i is difficult to
control and only can be suppressed, while the correlated offset of ∆i may even be
eliminated in certain cases.
In high-speed data conversion, a major source of errors is dynamic offsets caused by
mismatches in sampling switches and sampling capacitance values [52]. The dynamic
offsets can be suppressed or even eliminated in ADC design.
27
4.2 Signal Slew Rate Limitation
In the flash conversion without an external S/H circuit, the signal slew rate limits the
ADC speed and resolution in a given technology. When the maximum slew rate of the
analog input is close to the clock transition rate, the logic output can be different from the
expected value because the input signal still influences the output of comparators during
the time between the clock latch turned on and the input signal locked off. This
phenomenon introduces odd harmonics because it occurs for both negative and positive
slopes [54].
This error can be lowered when the clock transition rates are sufficiently higher than
the maximum slew rate of the analog input. On a large chip, this requires careful clocking
distribution with particular attention to their loading [9].
Another concept related to signal slew rate is the clock jitter, or called aperture jitter.
The maximum tolerable jitter determines the ADC’s resolution and speed [47]-[50]. For a
full-scale analog input Vin = V fs 2 sin 2πft , whose maximum rate of change is πּ f ּVfs.
The maximum tolerable jitter for 1-LSB is
1
dt MAX = (4.7)
π ⋅ f ⋅ 2N
where dtMAX represents the maximum clock jitter and N is the converter’s resolution.
28
4.3 Sparkles and Meta-stability
Sparkles and meta-stability are general phenomena in high-speed ADCs, which result,
in grossly incorrect digital output codes. The sparkle phenomenon is a ONE above ZERO
caused by timing mismatch among comparators. An important effect resulting from the
lack of a S/H in flash ADC is the sparkles (or bubbles) in the thermometer code [51][53].
Meta-stability is a phenomenon associated with binary digital logic system. A meta-stable
state occurs when an indeterminate state between logic ‘1’ and logic ‘0’ is latched at the
clock edge. It can happen by a comparator with slow regenerative time or using flip-flops
for synchronization of signals [51].
There are digital encoding schemes developed to suppress the sparkles and
meta-stability errors. But in high speed flash converters Gray encoding is used as an
intermediate step between thermometer and binary codes to suppress two potential errors
[9]. The error of meta-stable state can be suppressed because one meta-stable state of a
comparator is fed into no more than one input in Gray coding. The error of sparkles is
reduced because the accuracy of the Gray code degrades gradually as more sparkles appear
in the thermometer code.
A 3-bit Gray code example is used to illustrate the above points as shown in Figure 4-3
[9]. From the correspondence, the output G3G2G1 can be expressed in terms of the
thermometer code as follows:
___ ___
G1 = T1 T3 + T5 T7 (4.8)
___
G2 = T2 T6 (4.9)
29
G3 = T4 (4.10)
The thermometer code Ti appears in only one expression and hence no signal is split
and the effect of meta-stable states can be reduced as shown in Figure 4-4. With pipelining,
the time for regeneration is increased to reduce logic meta-stabilities.
Figure 4-3 Correspondence among Thermometer, Gray and Binary Codes
Figure 4-4 Pipelined Thermometer-to-Gray Encoder
30
Figure 4-5 illustrates the Gray encoding suppressing the effect of various sparkles,
compared with direct binary encoding. The Gray output remains a reasonable
approximation of the sampled value with the number of sparkles increasing.
Figure 4-5 Comparison of Gray and Direct Binary Encoding at Various Sparkles
Although the Gray encoding can be used to suppress the errors by meta-stability and
sparkles, the performance of flash conversion is determined primarily by the speed and
accuracy of the comparators.
31
Chapter 5 CLOCKED DIGITAL COMPARATOR
5.1 Introduction
Comparator is the constituent part of ADCs with full-flash architecture. The overall
performance of flash ADCs is limited by the performance of their comparators for the
multi-bit flash ADCs are comparators parallelized, which are one-bit converters. However,
CMOS flash ADCs suffer greatly from offsets in the comparators because of device
mismatches and clock timing mismatches.
Generally, high-speed flash ADCs use the differential amplifier structure in
pre-amplifier and comparator design. There are two types of offsets in a differential
comparator. One is a static and random offset from device mismatches, which is amplified
into a larger offset in the output. The other is a dynamic offset at the output of comparator
arising from clock switching in the regenerative latch. The dynamic performance of ADC
is degraded greatly by the offsets of differential comparators.
In the state-of-the-art flash ADCs with the speed less than 2-GHz sampling frequency
reported in Table 3-1, averaging technique is used to smooth out the random mismatch
across the differential comparator and improve the SNR in flash ADCs [1][3][19][34]. For
32
strongest averaging [44], one third dummy amplifiers are added and extra reference
voltage increases the difficulty of the high-speed differential comparator design due to the
stringent effective input voltage range in scaling-down CMOS processes. Besides,
averaging method reduces amplifier bandwidth and consumes extra power due to dummy
amplifiers [44].
In design of monolithic flash ADCs using feature size less than 130-nm CMOS
processes with the sampling speed over 2-GHz and the effective signal bandwidth over
1000-MHz, the differential comparator design is challenged. More importantly, the
dynamic offsets from clock timing mismatches between parallelizing comparators become
more significant and apparently effect to the ADC performance at over 1-GHz frequency
signal.
As reviewed in Chapter 3, the comparator with inverter configuration was suggested
for scaling-down CMOS processes. However, the relative researches reported were
focusing on the static performance, did not consider the dynamic performance of the ADCs
for high frequency signals.
In this research, we propose a high-speed clocked digital comparator (CDC) with
inverter configuration, coupled with a dynamic offset suppression and an optimum
implementation method for high-speed wideband CMOS flash ADCs. With a simple
inverter configuration, the CDC has less device mismatch issues and lower device linearity
requirements. The dynamic offset arising from clock timing mismatches is more apparent
in the CDC design, than the random static offset from device mismatches, which is dealt
with in this research by dynamic offset suppression technique and optimization design for
wideband communications without additional hardware.
33
A brief review of inverter amplifier is presented in Section 5.2. CDC and dynamic
offset suppression is presented in Section 5.3. Section 5.4 presents procedures to
implement the optimal CDC design, and discuss optimization theory and experimental
results. The performance of CDC is summarized in Section 5.5.
5.2 Inverter Amplifier
Figure 5-1(a) illustrates an inverter amplifier where M1 and M2 are PMOS and NMOS
transistors. The operating regions of the inverter amplifier for different input voltages are
shown on the voltage transfer function characteristics of Figure 5-1(b). Both the
transistors are in saturation region between points A and B on the output curve with a bias
voltage Vbias. Since both transistors are being driven by vin and in saturation, the inverter
amplifier has the highest gain.
Vdd Vout
Vdd C
B d
M1 ate
tur
sa tive
Vbias OS a c
Vin Vout NM OS
∆Vout
NM
e
tiv
ac ted
OS tura
PM S s a A
O
M2 PM
D Vin
Vss ∆Vin
(a) Inverter Amplifier (b) Voltage-Transfer Characteristics
Figure 5-1 Inverter Amplifier with Voltage-Transfer Characteristics
34
The PMOS M1 is in the saturation region when v DS1 ≥ v SG1 − VTp , then we have
vOUT ≤ v IN + VTp (5.1)
The NMOS M2 is in the saturation region when v DS 2 ≥ v SG 2 − VTn , then we have
vOUT ≥ v IN − VTn (5.2)
For both transistors in saturation, the output range ∆Vout can be derivate by subtracting
Equ.(5.2) from Equ.(5.1) as
∆Vout = VTp + VTn (5.3)
Figure 5-2 illustrates the small-signal characteristics of inverter amplifier. The parasitic
capacitances are presented in Figure 5-2(a) and Figure 5-2(b) presents the small-signal
model of (a).
(gm1+gm2)Vin
1/(gds1+gds2)
Cdb1+Cdb2
Figure 5-2 Small-Signal Characteristics of Inverter Amplifier
35
The largest small-signal voltage gain occurs when both transistors are saturated which
can be expressed by
2 2
+
− ( g m1 + g m 2 ) Vbias − VTn Vdd − Vbias − VTp
A0 = = (5.4)
g ds1 + g ds 2 (λ n + λp )
From Equ.(5.4), the value of A0 is process-dependent and varies in a certain range with
Vbais. For IBM 130 nm CMOS process, A0 is around 16 and slight changes with Vbais from
0.4v to 0.75v.
The input range for both transistors in saturation is ∆vin for Vbias which can be
expressed by
∆vin =
(λ n (
+ λ p ) VTp + VTn ) (5.5)
⎛ 2 2 ⎞
⎜ + ⎟
⎜ Vbias − VTn V − V − V ⎟
⎝ dd bias Tp ⎠
For IBM 130 nm CMOS process, if VTp + VTn approximate to 0.4V, ∆vin is around 25 mV.
The -3dB frequency response can be expressed as
g ds1 + g ds 2
= (λ n + λ p ) ds
I
ω0 = (5.6)
C out C out
with C out = C gds1 + C gds 2 + C bd 1 + C bd 2 + C L , illustrated in Figure 5-2(b).
5.3 Clocked Digital Comparator with Dynamic Offset Suppression
Figure 5-3 shows the structure of clocked digital comparators (CDCs) designed in
the n-bit flash ADC, in which the 2n-1 comparators have the same structure, but are sized
36
differently. A comparator consists of two cascaded CMOS inverters and a digital CMOS
switch. The first inverter is a quantization component. The second inverter is a component
which sharpens and balances the quantized output. The digital switch is a digitization
component which makes the comparator perform a sampling operation.
Figure 5-3 Clocked Digital Comparator
The analog quantization level of clocked digital comparator is the switching
threshold voltage of the quantization inverter. It is a reference voltage and is
self-determined by the size ratio of NMOS and PMOS. As shown in Figure 2(a), this
internal reference voltage, Vm, is defined as the input voltage Vin of the quantization
inverter when the output voltage Vo1 equals to Vin, where both PMOS and NMOS
transistors are in saturation. Figure 2(a) is the static voltage transfer characteristic (VTC) of
the inverter. The voltage Vdd is the supply voltage of the process. The value of Vm is
expressed as
37
µ pW p
µ nW n (Vdd − VTp ) + V Tn
Vm = (5.7)
µ pW p
1+ µ nW n
where VTp and VTn are threshold voltages of PMOS and NMOS devices; Wp and Wn are
widths of PMOS and NMOS; µp and µn are hole mobility and electron mobility,
respectively.
Figure 5-4 Static VTC
Figure 5-4(b) shows the static VTC for the 2n-1 comparators. The 2n-1 analog
quantization levels Vm(i), i = 1,….2n-1, are equally-spaced. However, due to the hysteresis
of the inverter switching, there will be a time delay (a time offset) ∆toffset for Vo1 rise to or
fall to Vm after Vin = Vm. If the ∆toffset of 2n-1 comparators are all different, the outputs Vo1 of
all comparators won’t equally-spaced. Then the analog quantization levels will have
irregular offsets when compared with their corresponding values in static VTC. The offsets
38
of the comparators and the offset differences among the comparators introduce dynamic
noises and degrade ADC dynamic performance.
V vo1(t)
Vdd
∆V f
Vm
∆Vr
vin(t)
t
+ +
t1 t1 t2 t2
(a) switching time
Vo1 Vo1
Vdd Vdd
Vin Vin
Vm Vm +
Vm- Vm
(b) falling volt. offset (c) rising volt. offset
Figure 5-5 Transient Behavior of CDC Quantization Inverters
To model the dynamic offsets, we analyze the transient behavior of a clocked digital
comparator for an input sinusoidal signal, vin(t)=Acos(ωt) where A is signal amplitude and
ω is signal frequency. Figure 5-5 shows the transient behaviors of the quantization inverter
39
in the digital comparator. The switching time offset is defined as the offset time ∆toffset for
the inverter output Vo1 to rise to or fall to Vm after Vin = Vm. Both fall offset time ∆tf-offset =
(t1+ - t1) and rise offset time ∆tr-offset = (t2+ - t2) are shown in Figure 5-5(a). When Vin is
approaching to Vm, , assuming the load capacitance is small and both NMOS and PMOS are
in saturation, ∆tf-offset ≈ ∆tr-offset (=∆toffset) and is expressed as
I ds = 12 K n ( WL ) n (Vin − VTn ) 2 (1 + λnVo1 ) (5.8)
I ds = 12 K p ( WL ) p (Vdd − Vin − | VTp |) 2 [1 + λ p (Vdd − Vo1 )] (5.9)
∆idsn
= λn I ds (5.10)
∆vo1
∆idsp
= −λ p I ds (5.11)
∆vo1
∆ids = ∆idsn − ∆idsp = (λn + λ p ) I ds ∗ ∆vo1 (5.12)
∆vo1 Co1 (5.13)

∆t offset = Co1 ≈
∆ids (λn + λ p ) I ds
where Co1 is the capacitive load at the output Vo1; Ids is the drain-source current of NMOS
and PMOS; λn and λp are active-region slope parameters for NMOS and PMOS,
respectively.
On the other hand, during time ∆toffset, vin(t) will either rise or fall to Vm+ or Vm-
depending on if it is in the rising or falling cycle. The difference between Vm and Vm+ or Vm-
is the dynamic voltage offset. Both falling voltage offset ∆Vf-offset = (Vm+ - Vm) and rising
voltage offset ∆Vr-offset = (Vm - Vm-) are shown in Figures 5-5(b) and (c). Since rising offset
and falling offset happen when both transistors are in saturation, ∆Vf-offset ≈ ∆Vr-offset and
output offset ∆Voffset is expressed by
40
∆Voffset = A0 ∗ ( Aω ) sin ωt ∗ ∆t offset (5.14)
It is clear that ∆Voffset is frequency-dependent, so called dynamic offset. Substituting
Equ. (5.13) to Equ. (5.14), we obtain
C o1
∆V offset = A0 ∗ ( Aω ) sin ωt (5.15)
(λ n + λ p )I ds
where λn and λp are process-dependent, and A and ω are signal-dependent.
To suppress the dynamic offset ∆Voffset of comparators and to eliminate the offset
differences among comparators, as shown in Equ. (5.15) the Co1 is designed as small as
possible and has the same value for 15 comparators, and similarly the Ids is designed as
large as possible and has the same value for 15 comparators.
5.4 Optimization of Sizing Design
5.4.1 Methodology
Suppressing the CDC dynamic offset demands a large value of Ids as well as a small
value of Co1. However, with a fixed gate-source voltage, increasing Ids is only by increasing
sizes of the transistors, which results in large parasitic capacitance of Co1 in the CDC
comparator. Thus optimization of Ids is required for dynamic offset suppression in CDC
design.
A circuit-level optimal process of CDC design is developed for the optimization of Ids
and the optimization of the dynamic offset suppression. In the optimal process, the CDC
41
feature values, including Co1, Ids, and the ratio of them, are firstly analyzed by calculated in
Matlab with a simple model to gain an insight into the relationship between CDC dynamic
offsets and Ids. The simple model used here is the level-1 transistor model, a model that
generally is used by most of analog circuit design analysis. Then the Ids of the CDC is
determined optimally by simulating 6 different sizing CDCs in Cadence Spectre with a
more complex transistor model. The model used in the simulation is the level-49 transistor
model, a model that is used for IBM 130 nm process. This two-step optimal process results
in an optimization of dynamic offset suppression in the CDC design.
Before optimizing the CDC design for dynamic offset suppression, we analyze the
relationship between CDC dynamic offsets and the switching speed of its quantization
inverter. Switching speed of an amplifier is generally expressed by its output slew rate
[55]. The slew rate of CDC is then expressed by
∆vout I (5.16)
SlewRate = max( ) = sat
∆t CL
The slew rate of the quantization inverter represents the switching speed as in Equ.
(5.17):
∆vo1 I (5.17)
SlewRate = max( ) = ds
∆t Co1
In Equ. (5.13) and (5.15) both the time and voltage offsets are proportional to the ratio
of Co1 and Ids and inversely proportional to the slew rate of the CDC’s quantization
inverter as shown in Equ.(5.18) and (5.19).
Co1 1 (5.18)
∆toffset ∝ =
I ds SlewRate
42
Co1 1 (5.19)
∆Voffset ∝ =
I ds SlewRate
Therefore, Higher slew rate will generate smaller dynamic offset in CDCs. In our
dynamic offset suppression slew rates of 15 CDC’s quantization inverters are analyzed to
determine the optimum value of Ids.
To determine the slew rate of the quantization inverter, two parameters Co1 and Ids are
calculated and analyzed. In the CDC comparator, the Co1 is the sum of gate-to-drain
capacitance, bulk-to-drain capacitance of the quantization inverter and capacitive load
from the CDC second inverter. Figure 5-6 shows the small-signal model of a CDC
quantization inverter for calculating the capacitance load Co1 in Equ.(5.20), where Cgd1 and
Cgd2 are the gate-to-drain capacitances of NMOS and PMOS, respectively. Cbd1 and Cbd1
are the bulk-to-drain capacitances of NMOS and PMOS, respectively. CL is the capacitive
load from the CDC second inverter.

(gm1+gm2)Vin
1/(gds1+gds2)
Cdb1+Cdb2
Figure 5-6 Small-Signal Model of CDC Quantization Inverters
43
Co1 = Cgd1 + Cgd 2 + Cbd 1 + Cbd 2 + CL (5.20)
For predicting the input capacitance of CDC-based ADCs, the input capacitance of
CDC is approximated in Equ. (5.21), referring to Figure 5-2(a), which is under Miller
effect, where gm1 and gm2 are the trans-conductance of M1 and M2, respectively. gds1 and
gds2 are the conductance of M1 and M2, respectively.
⎛ g + g m2 ⎞
Cin = ⎜⎜1 + m1 ⎟⎟(C gd 1 + C gd 2 ) + (C gs1 + C gs 2 ) (5.21)
⎝ g ds1 + g ds 2 ⎠
Equ. (5.22), (5.23) and (5.24) are used for calculating the gate-to-drain, gate-to-source and
bulk-to-drain parasitic capacitances, Cgd, Cgs and Cbd. Cox is the oxide capacitance. LD is
the lateral diffusion. Weff is the effective channel width. AD is the area of the drain. PD is
the perimeter of the drain. CJ is the zero-bias junction capacitance, CJSW is the zero-bias,
bulk-drain sidewall capacitance. PB is the bulk junction potential. MJ is the bulk junction
grading coefficient. MJSW is the bulk-drain sidewall grading coefficient. The calculation
of AD and PD is shown in Appendix A.
C gd = C ox (LD )(Weff ) (5.22)
C gs = C ox (LD + 0.67 Leff )(Weff ) (5.23)
⎡ V ⎤ ⎡ V ⎤
Cbd = (CJ )( AD )⎢1 + (MJ ) bd ⎥ + (CJSW )(PD )⎢1 + (MJSW ) bd ⎥ (5.24)
⎣ PB ⎦ ⎣ PB ⎦
W
I ds = K ' (VGS − VT )2 (1 + λVDS ) (5.25)
2L
The drain-source current in saturation is calculated in Equ.(5.25), where W and L are the
width and length of transistor. VGS and VDS are the gate-source and drain-source voltages.
44
VT is the transistor threshold voltage. K’ is the trans-conductance parameter in saturation
and λ is the channel length modulation parameter. As analyzed in the previous section,
the offsets happen when both transistors are in saturation. The critical segment in the
switching time of CDC quantization inverter is the time segment that both transistors are
in saturation, which is used to approximate the slew-rate of the quantization inverter.
Parameter values in Equ. (5.22) to (5.24) are taken from IBM 130 nm CMOS process
A diagram of Matlab analysis in Figure 5-7 is designed to illustrate the calculation of Ids,
Cin, Co1, and the slew rate (SR) for optimization of Ids, CDC transistor sizing, and
dynamic offset suppression.
Figure 5-7 Diagram for Matlab Analysis
45
Figure 5-8 shows the results of the diagram of Matlab analysis using IBM 130 nm
CMOS process parameters where the desirable threshold voltage Vm equal to 0.484 V.
Figures 5-8 (a), (b) and (c) show that Co1 (fF), Ids (µA) and Cin (fF) all monotonously
increase as the NMOS width increases. It is shown from Figures 5-8(a) and (c) the
bulk-to-drain capacitance is much larger than its gate-to-drain capacitance, especially in
scaling-down CMOS processes. Figure 5-8 (d) illustrates that the slew-rate is saturated
when the Ids increases to 150 µA.
Figure 5-8 Ids, Co1, Cin, Slew-Rate Vs. NMOS width at Vm = 0.484v
46
A large slew-rate is desired for efficient dynamic offset suppression and high speed
conversion. If the slew-rate is saturated, then there is no need to increase the Ids by
increasing the size of transistors which in turn will increase the input capacitance Cin of
CDC, as shown in Figure 5-8 (c). The total input capacitance of CDCs determines the
input signal frequency bandwidth of flash ADC. Therefore, a threshold current Ids-threshold of
CDC is defined as the value of Ids when the slew-rate become saturated.
When the slew rate becomes saturated, it does not decrease as Ids is increasing.
However, in Cadence simulation, the slew rate decreases when the values of Ids are either
too small or too large which are shown in Figures 5-9 and 5-10.
Figure 5-9 Comparison of Vo1 Rising Speeds with Vm=0.484v and Various Ids
47
Figure 5-10 Comparison of Vo1 Falling Speeds with Vm=0.484v and Various Ids
Following the diagram for Matlab analysis in Figure 5-7, we enumerate 6 different
values of Ids and design 6 different CDC comparators for a same threshold voltage Vm of
0.484 V. Figures 5- 9 and 5-10 show switching speed comparison of the 6 quantization
inverters with 6 different Ids (20 µA, 50 µA, 75 µA, 100 µA, 150 µA, and 200. The
input sinusoidal signal frequency is 1 GHz. Figures 5-9 and 5-10 compare the rising and
the falling speed at the output Vo1 of the 6 quantization inverters. It is observed that
50µA is close to the saturated current Ids-threshold and the comparator with Ids = 50µA is
only 3ps slower than the fastest one. As shown in Table 5-1, the comparator with Ids =
100µA has the fastest rising speed and the comparator with Ids = 75µA has the fastest
falling speed. The optimum value of Ids to achieve the fastest switching speed is in the
range of [75µA, 100µA]. This enumeration method can be repeated with Ids in the small
range of [75µA, 100µA] for optimum value of Ids.
48
Table 5-1 Comparison of Switching Speeds of Vm = 0.484v and 6 different Ids
The Ids-threshold obtained from Cadence simulation is slightly smaller than the value
calculated from the diagram of Matlab analysis. The above optimization process is for
one CDC comparator and the threshold voltage Vm equals to 0.484v. The same
optimization process can be repeated for all CDC comparators with different threshold
voltages Vm. Ideally, a same value of Ids for all CDC quantization inverters is desired to
suppress dynamic offsets. In reality, the Ids-threshold values of all CDCs are likely different
because their threshold voltages Vm are different. Therefore, we need to find an optimal
value of Ids for each CDC.
5.4.2 Optimum Ids
The design optimization developed for dynamic offset suppression is applied and
validated on a 4-b 2.5-GSPS CMOS flash ADC. Table 5-2 shows switching speed
comparison of three CDCs with Vm in the range of [0.45v, 0.668v]. Vm(i) with i = 1…15
represents the threshold voltages of 15 CDCs in the 4-b flash ADC. Vm(1) is the threshold
voltage of the first CDC; Vm(15) is the threshold voltage of the last CDC. The transistor
49
widths of NMOS and PMOS, Ids, and the switching speed order (rising and falling) for each
CDC are indicated in Table 5-2. The optimum Ids of Vm(1) and Vm(15) is determined in the
range [75µA, 100µA].
Table 5-2 Comparison of Switching Speeds for Various Vm
Assume Ids-threshold(i) with i =1…15 represents the threshold currents of 15 CDC
quantization inverters. We’ll have
I ds −threshold (1) < I ds −threshold ( 2)....... < I ds −threshold (8) (5.26)
I ds −threshold (8) > .......I ds −threshold (14) > I ds −threshold (15) (5.27)
Thus, the CDCs with Vm(1) and Vm(15) become critical designs in the CDC design since
their switching speeds determine the speed of the ADC.
From Table 5-2 it is shown that both Ids- threshold(1) and Ids- threshold(15) are smaller than
150µA because the switching speed decreases when Ids is 150µA. Ids- threshold(8) is larger
than 200µA because the switching speed increases when Ids is 200µA. Then the optimum
50
Ids for this 4-b flash ADC with the threshold voltage range [0.45v, 0.688v] is determined in
the range of [75µA, 100µA]. In this 4-b flash ADC, Ids = 80µA as its optimum value is
being used for the CDC design. Optimization of Ids also optimizes the dynamic offset
suppression in the CDC design.
Three 4-bit flash ADCs with Ids of 50µA, 80µA and 150µA and input dynamic range of
[0.45v, 0.688v] was designed. Comparison of SFDR of these three ADCs is presented in
Figure 5-11.
Figure 5-11 Comparison of ADC SFDR for Optimization of Ids
The results testify the optimization of dynamic offset suppression in CDC design. As
discussed above the Ids of 80µA is an optimum value for designing the quantization
inverter for efficient dynamic offset suppression. Its ADC achieves the highest SFDR.
The quantization inverters with Ids of 50µA and 150µA have smaller slew rates and
51
results in 3 to 5 dB down of SFDR compared with the quantization inverter with Ids of
80µA as shown in Figure 5-10.
5.5 Summary
The CDC implemented by inverter configuration, with dynamic offset suppression and
optimization, is characterized in the following:
• No external resistor or capacitance array needed for generating reference voltages,
which results in small area and avoids resistive thermal noise which usually
generates a reference voltage offset.
• Fewer analog components, which is robust for DSP interference in SoC
applications and no requirement of device linearity in scaling-down CMOS
technologies.
• Small static power consumption, which makes it suitable for SoC and
battery-powered applications.
• No additional hardware needed for dynamic offset suppression
• Less possibility for the metastable output due to high switching speed of CDCs.
52
Chapter 6 CDC-BASED PIPELINED FLASH ADC ARCHITECTURE
The speed of monolithic flash ADCs is limited by the comparator switching speed and
the propagation delay of the logic in the encoder [51]. This CDC-based pipelined flash
ADC architecture adopts high-speed comparators and pipelined clocked DCVSPG
encoders to achieve a maximum sampling frequency. Using the dynamic offset
suppression technique and circuit optimization method presented in Chapter 5, the
CDC-based pipelined flash ADC can achieve 2-GHz signal bandwidth. The architecture
is well suited for integrated SoC applications due to its full compatibility with digital
CMOS technology, low power and small area.
6.1 Architecture
Two block diagrams of the CDC-based pipelined CMOS flash ADC architecture are
shown in Figures 6-1 and 6-2. Both block diagrams have the same architecture except
different encoding schemes. The direct-binary encoder takes an 1-of-n code after the 1/0
boundary detector and outputs a binary code (Figure 6-1). The Gray encoder takes the
thermometer code, decodes it into Gray code, and then outputs a binary code (Figure 6-2).
53
Direct Binary Clocked_Encoder
Figure 6-1 Architecture of CDC-based Pipelined ADC with Direct-Binary Encoding
Figure 6-1 presents an ADC architecture with direct-binary encoding which includes an
array of CDC comparators, an array of gain booster, an array of 1/0 boundary detectors, a
direct-binary clocked encoder, and a clocked tree. For a 4-b, 1-GHz signal bandwidth
ADC in 130-nm CMOS process, the maximum tolerant aperture error is about 20 ps. The
clock signal from the clock tree has transient time about 15 ps. Therefore the ADC output
should have less possibility of sparkles.
54
CLK Clock-Tree
CLK
CLK CLK CLK
Vin
MSB
LSB
Comparator Gain Booster Encoder
Figure 6-2 Architecture of CDC-based Pipelined ADC with Gray Encoding
The ADCs with Gray encoding in Figure 6-2 have better dynamic performances than
the ADCs with direct-binary encoding because of better sparkles and meta-stability
suppression. The timing diagram of CDC-based pipelined CMOS flash ADC is shown in
Figure 6-3. The clock signals CLK and CLKB are the inputs to the CDCs and the pipelined
encoder, no matter either direct-binary encoding or Gray encoding is employed.
55
The associated timing diagram of CDC-based pipelined CMOS flash ADC is shown in
Figure 6-3. The clock signals CLK and CLKB are the inputs for the CDCs with
complementary digital CMOS clock and the pipelined encoder regardless of direct-binary
encoding or Gray encoding.
Figure 6-3 Timing Diagram of CDC-based Pipelined CMOS Flash ADC
The sampling rate in the proposed CDC-based pipelined CMOS flash ADC is
determined by the propagation delay in the pipelined encoder plus the clock transition time,
not the switching speed of the CDCs. The pipelined encoder is implemented in DCVSPG
clocked logic. One clocked DCVSPG logic has about 57 ps transition time (propagation
delay) in IBM 130 nm digital CMOS process. The total transition time including the clock
transition time is about 87 ps. The gain booster is two cascaded inverters and the
propagation delay is much less than 87 ps. The regenerative speed of the CDCs with
inverter configuration, optimized with high slew rate, should be in the speed range of an
inverter, which is about 10 to 20 ps. The signal transition time in the ADC would be less
than 100 ps. Thus the maximum sampling frequency of the CDC-based pipelined CMOS
flash ADC could be up to 5-GSPS.
56
6.2 CDCs and Gain Boosters
The CDC design is presented in the previous chapter. The first quantization inverter of
CDC is optimized with dynamic offset suppression. The second inverter of CDC is
designed to sharpen the quantized output and also a small load to the quantization inverter
in order to have a small dynamic offset.
The signal bandwidth of a CDC-based pipelined CMOS flash ADC varies when the
input voltage range changes. Experiments of observing the 3-dB bandwidth and the input
voltage ranges of CDCs in 130 nm CMOS process are conducted and the results are shown
in Table 6-1.
Table 6-1 Relation between Input Voltage Range and 3-dB Bandwidth of CDCs
in IBM 130-nm Digital CMOS Process
57
6.3 Pipelined DCVSPG Encoders
To achieve high sampling frequency in flash ADCs, pipelined encoder divides the total
propagation time into small time segments. In this research, two pipelined encoding
schemes, both implemented in clocked logic gates using differential cascade voltage
switch with pass-gate (DCVSPG) logic [56], are presented. This section first introduces
the pipelined encoder architecture and then presents the DCVSPG logic implementation.
6.3.1 Encoder Architecture
Two pipelined DCVSPG encoders are proposed. The first encoder is direct-binary
balanced encoder which takes an 1-of-n code after 1/0 boundary detector. The 1/0
boundary detector is a two-input XOR gate converting a thermometer code to a 1-of-n code.
A 4-bit direct-binary balanced encoder is shown in Figure 6-4.
58
Figure 6-4 4-b Direct-Binary Balanced Encoder
59
The binary output code b3b2b1b0 can be expressed in a balanced distribution in terms of
1-of-n code as follows:
These balanced logic functions are suitable for pipeline implementation.
The second encoder is thermometer-Gray-binary (TGB) encoder which include
two-step encoding processes: 1) thermometer-to-Gray code, and 2) Gray-to-binary code. A
4-bit pipelined thermometer-Gray-binary encoder to illustrate the two-step encoding
processes is shown in Figures 6-5 and 6-6. The Gray code outputs G3G2G1G0 of the
thermometer-to-Gray code in Figure 6-5 can be expressed by thermometer codes as
follows.
G3 = T8 (6.1)
___
G2 = T4 T12 (6.2)
___ ___
G1 = T2 T6 + T10 T14 (6.3)
___ ___ ___ ___
G0 = T1 T3 + T5 T7 + T9 T11 + T13 T15 (6.4)
60
T1
T3 AND
CLK
OR
T5
CLK
T7 AND
CLK
OR G0
T9
CLK
T11 AND
CLK
OR
T13
CLK
T15 AND
CLK
T2
T6 AND
CLK
OR
T10 CLK buffer G1
CLK
T14 AND
CLK
T4
T12 AND
CLK CLK buffer
CLK buffer G2
T8
CLK buffer
CLK buffer G3
CLK buffer
Figure 6-5 Pipelined Encoding of Thermometer-to-Gray Code
The binary code outputs b3b2b1b0 of the pipelined encoding in Figure 6-6 are expressed
in terms of Gray code as follows
b3 = G3 (6.5)
b2 = [G3 ⊕ G2 ] (6.6)
b1 = [G3 ⊕ G2 ] ⊕ G1 (6.7)
b0 = [G3 ⊕ G2 ] ⊕ [G1 ⊕ G0 ] (6.8)
61
Figure 6-6 Pipelined Encoding of Gray-to-Binary Code
As discussed in chapter 4, the encoding scheme with Gray code has advantage of
suppressing the sparkles and meta-stability, especially for high slew rate signals in
wideband applications. In the next chapter, the majorities of implementation of the
proposed CDC-based pipelined CMOS flash ADC are realized with Gray encoding scheme,
while one 4-b implementation has both encoders and its performances are compared.
6.3.2 DCVSPG Logic Circuit Blocks
In the above two pipelined encoders, logic functions involved include AND, OR,
XOR, and Buffer and all are implemented by the DCVSPG logic shown in Figures 6-7, 6-8,
6-9 and 6-10.
There are several advantages of the DCVSPG logic. Due to the cross-coupled pMOS
device load, the DCVSPG logic is designed to have a built-in latch structure. The output is
latched at the previous output value when the clock is “0.” Both Q and QN are produced
nearly at the same instance, which avoids an extra inverter delay to generate the QN from
62
the Q. The DCVSPG encoder is a ratioless logic, and the output obtained has no glitches. It
has superior performance with power and area, especially suitable for pipelined by
eliminating extra latches.
QN Q
CLK
AN A AN A
Vdd BN GND B
Figure 6-7 Clocked DCVSPG AND/NAND Gate
QN Q
CLK
AN A AN A
BN GND B Vdd
Figure 6-8 Clocked DCVSPG OR/NOR Gate

63
Figure 6-9 Clocked DCVSPG XOR/XNOR Gate
Figure 6-10 Clocked DCVSPG Buffer
64
6.4 Clock Tree
Since flash ADCs provide an intrinsic sampling function for dynamic input signals, the
clock timing uncertainty needs to be considered. The timing uncertainty ∆tMAX for a 6-b,
1-GHz bandwidth ADC is less than 5-ps and for a 4-b, 2-GHz bandwidth ADC is less than
10-ps from Equ.(4.7).
An inverter clock tree is designed. Simulations reveal rise/fall times of the clock
signal are about 20 ps (slew rate 50G v/s) shown in Figure 6-11. The output load for each
clock leaf is two DCVSPG gates. The average slew rate before the output load is 55G v/s.
With the load, the average slew rate is 50G v/s. The maximum threshold voltage variation
of the switch must be less than 300 mV according to Equ.(6.9).
∆t max
∆VT ≤ (Vdd − Vss ) (6.9)
t rise / fall
65
Figure 6-11 Performance of Clock Tree
66
Chapter 7 IMPLEMENTATION AND PERFORMANCE OF CDC-BASED
PIPELINED CMOS FLASH ADC ARCHITECTURE
This chapter presents three implementations of CDC-based pipelined CMOS flash
ADCs is 130 nm CMOS process. First, a 4-b, 1-GHz bandwidth 2.5-GSPS ADC is the
initial research objective used in a digital receiver-on-a-chip. Both schematic and
post-layout performances are compared. Secondly, a 4-b, 2-GHz bandwidth 4-GSPS
ADC is implemented and compared with the state-of-the-art 4-b ADCs in literature. Lastly,
a 6-b CDC-based pipelined ADC is implemented and its performance is evaluated. This
15mv-input-range CDC-based pipelined ADC also shows the performance difference of
using balanced direct binary (BDB) encoder and thermometer-Gray-binary (TGB)
encoder.
7.1 4-b 1.25-GHz Bandwidth 2.5-GSPS ADC
This 4-b 1-GHz bandwidth 2.5-GSPS flash ADC is proposed and implemented in three
versions. In the first version, the ADC is pipelined to achieve a 2.5 GHz sampling rate and
the inverter comparators are sized manually [40]. Using the dynamic offset suppression
technique in the design of inverter comparators, the second version ADC improves a SFDR
of 10 dB in the Nyquist bandwidth [41]. By optimization of dynamic offset suppression
67
and using a thermometer-Gray- binary encoding scheme, the third version ADC achieves
an ENOB of 3 bits and a SFDR of 25 dB.
7.1.1 Implementation and Performance
This ADC is designed and simulated in 130 nm CMOS process using Cadence Spectre
and VSDE 4.1 (Aptivia). Figure 7-1 is the schematic diagram of 4-b CDC-based pipelined
ADC, which includes 15 CDC comparators, a TGB encoder and a clock tree. Figure 7-2 is
the schematic of the TGB encoder, which include a Gray-to-binary encoding diagram
(Figure 7-3). Figure 7-4 is the schematic of the clock tree. Figure 7-5 is the schematic of
15 CDC comparators, with an input voltage range of Vm from 0.45v to 0.688v and an
optimum Ids of 80µA.
68
Figure 7-1 Schematic of 4-b 1.25-GHz Bandwidth 2.5-GSPS ADC
69
Figure 7-2 Schematic of TGB 4-b Encoder
Figure 7-3 Schematic of Gray-to-Binary Encoding
70
Figure 7-4 Schematic of Clock Tree for a 4-b ADC
71
Figure 7-5 Schematic of 15 CDC Comparators
72
Figure 7-6 shows the simulated voltage transfer characteristics of 15 quantization
inverters in 15 CDCs. The 15 quantization levels are equally-spaced. Figures 7-7 (a) and (b)
show the simulated outputs Vo1 and Vo2 of the 15 CDCs (Figure 5-3) at an input signal
frequency of 100 MHz. The outputs Vo1 and Vo2 of 15 comparators are nearly
equally-spaced after the dynamic offsets suppressed, which warrant a small differential
nonlinearity (DNL) error.
Figure 7-6 Outputs of 15 Quantization Inverters at DC
(a) output Vo1
73
( b) output Vo2
Figure 7-7 Outputs of CDC Comparators at 100MHz Sinusoidal Signal
Figure 7-8 Reconstructed Signal and Spectrum of 9.766MHz Signal
74
Figure 7-8 is the reconstructed signal and the spectrum of 9.77MHz signal. The
reconstructed signal figure shows the 15 comparators function correctly. The 4-b ADC
achieves an ENOB of 3.8 bits and a SFDR of 33.34dB as shown in the spectrum figure.
Figures 7-9, 7-10 and 7-11 show the reconstructed spectra for three input signal
frequencies of 250 MHz, 952 MHz and 1.248 GHz. The 4-b ADC achieves (SFDR,
ENOB) of (29.57 dB, 3.4 bits), (24.09 dB, 2.9 bits) and (22.25 dB, 2.8 bits), respectively.
Figure 7-9 Spectrum of 250MHz Signal
75
Figure 7-10 Spectrum of 952 MHz signal
Figure 7-11 Spectrum of 1.248GHz Signal
76
Figure 7-12 SFDR and SNDR vs. Input Frequencies
Figure 7-13 ENOB vs. Input Frequencies
77
Both SFDR and SNDR for input signal frequency up to 1.25 GHz at a 2.5GHz
conversion rate are plotted in Figure 7-12. ENOB vs. input signal frequency is plotted in
Figure 7-13. The SFDR of the 4-b ADC is above 22 dB and the ENOB is above 2.8 bits for
the Nyquist bandwidth.
Figure 7-14 SFDR Comparison of three ADCs
Figures 7-14 and 7-15 compare SFDR and SNDR of the 4-b 1.25 GHz bandwidth 2.5
GSPS CDC-based pipelined ADC with its previous versions [40, 41]. Compared with the
previous version ADC of dynamic offset suppression and BDB encoder [41], the SFDR is
improved by 2 to 3 dB at input frequencies above 800 MHz as shown in Figure 7-14. The
SNDR is also improved by 5 dB at input frequencies below 800 MHz, and 12 dB at input
78
frequencies above 800 MHz, as shown in Figure 7-15. The ENOB is improved almost by
1 bit at input frequencies below 800 MHz and 2 bits at frequencies above 800 MHz.
Compared with the other version ADC with comparators sized manually [40], the SFDR is
improved by 8 dB at low input frequencies and 13 dB at high input frequencies, as shown
in Figure 7-14. The performance improvements are summarized in Table 7-2.
Figure 7-15 SNDR Comparison of two ADCs
79
Table 7-1 Dynamic Performance Improvement Rate of the ADC
with Dynamic Offset Suppression and Design Optimization
7.1.2 Schematic vs. Post Layout Performance
The layout of the 4-b 1.25 GHz bandwidth 2.5 GSPS CDC-based pipelined ADC in
Figure 7-16 includes a clock tree on the top, 15 comparators in the middle, and a TGB
encoder on the bottom. The transistor sizes of the ADC in this layout are same as their sizes
in the schematic design. The area of layout is 220 µm x106 µm and the power is 7.9 mW for
a 2.5 GHz clock.
The dynamic performance of the layout is reported in the following figures and
compared with its schematic counterpart in the end of the section.
80
Figure 7-16 Layout of the ADC
81
Figure 7-17 Outputs of 15 Quantization Inverters at DC Post Layout Simulation
The 15 quantization levels of the layout are shown in Figure 7-17 from the post layout
DC simulation. The quantization levels of the first 14 comparators are almost equally
spaced. The quantization level of the15th comparator is slightly close to the one of the 14th
comparator.
82
Figure 7-18 Reconstructed Signal and Spectrum of 9.8MHz signal
The 15 quantization levels of the layout are also presented in Figure 7-18 from the post
layout transient simulation with a 9.8 MHz input signal. The 15 comparators function
correctly and the ADC achieves a SFDR of 34.03 dB, a SNDR of 24.58 dB, and an ENOB
of 3.8 bits. Comparing the layout performance (SFDR / SNDR / ENOB = 34.03 dB /
24.58 dB / 3.8 bits) (Figure 7-18) with the schematic performance (SFDR / SNDR / ENOB
= 33.34 dB / 24.79 dB / 3.825 bits) (Figure 7-8), it is shown the dynamic performances of
ADC of schematic and layout are close at an input signal of 9.8 MHz.
83
84
Figures 7-19, 7-20 and 7-21 show the reconstructed spectra for input signal frequencies
of 150 MHz, 952 MHz and 1.248 GHz. The ADC achieves (SFDR, ENOB) of (26.57 dB,
3.215 bits), (21.48 dB, 2.358 bits) and (19.34 dB, 1.7 bits), respectively.
Comparing the performance of SFDR and ENOB of the layout at input signal
frequencies 952 MHz and 1.248 GHz shown in Figures 7-20 and 7-21 with the ones of the
schematic shown in Figures 7-10 and 7-11, it is shown that the SFDR is decreased by 3.5
dB and 2.9 dB and the ENOB is decreased by 0.5 bit and 1 bit at input signal of 952 MHz
and 1.248 GHz respectively. The results are summarized in Table 7-2.
85
Table 7- 2 Performance Comparison of Schematic and Layout
at 952 MHz and 1.248 GHz
Schematic Layout Degradation

Signal Freq.
(MHz)
SFDR ENOB SFDR ENOB SFDR ENOB
(dB) (bits) (dB) (bits) (dB) (bits)
3.5 0.55
952 24.09 2.907 21.48 2.358
(14%) (17%)
2.9 1.13
1248 22.25 2.828 19.34 1.7
(13%) (35%)
Figure 7-22 SFDR and SNDF vs. Input Frequencies
86
Both SFDR and SNDR of the layout for input signal frequency up to 1.25 GHz at 2.5
GHz conversion rate are plotted in Figure 7-22. The plot shows that SFDR is above 18 dB
and SNDR above 12 dB up to the Nyquist frequency.
Figure 7-23 SFDR and SNDR Comparison between Schematic and Layout
87
Figure 7-24 ENOB Comparison between Schematic and Layout
Figures 7-23 and 7-24 compare the layout performance of the 4-b 1.25 GHz bandwidth
2.5 GSPS CDC-based pipelined ADC with its schematic counterpart. The SFDR and
SNDR of the layout both degrade about an average 5 dB compared to the schematic. That
means the ENOB degrades about 0.8 bit. That’s about 22% SFDR degradation and 28%
SNDR and ENOB degradation. From Figures 7-23 and 7-24, the degradation increases
with the input frequency exceeds 1 GHz. The maximum degradation of SNDR and ENOB
is 35% at 1.248 GHz, calculated in Table 7-1. The performance degradation is summarized
in Table 7-3.
88
Table 7-3 Dynamic Performance Degradation Rate of the Layout
Compared to the Schematic of the ADC
89
7.2 4-b 2-GHz Bandwidth 4GSPS ADC
The maximum 3-dB frequency of the comparators in 130nm IBM digital process is
approximated to 2-GHz in Chapter 5 during the optimal analysis. In Chapter 6, the
maximum speed of the digital circuit is 5-GHz. By the Nyquist theory, a 4-GSPS is
required for the bandwidth as 2-GHz. Thus this ADC is a special case of 4-b ADCs using
IBM 130nm digital process due to its bandwidth at the highest limitation. The
implementation and performance of the ADC are presented in this section, which is
followed by performance comparison of the ADC with 4-b ADCs in literature.
This ADC is designed and simulated using Cadence Spectre and VSDE 4.1 (Aptivia).
Figure 7-25 is the schematic diagram of 4-b 2-GHz 4-GSPS CDC-based pipelined ADC,
which includes a set of CDC comparators, a TGB encoder and a clock tree. The schematic
of the TGB 4-b encoder is the same as the previous ADC shown in Figure 7-2. The
schematic of the clock tree in the ADC is the same as the one shown in Figure 7-4. The
schematic of 15 CDC comparators is the same as the one in Figure 7-5, with a different
input voltage range of Vm from 0.501v to 0.62v and an optimum Ids 150µA.
90
Figure 7-25 Schematic of 4-b 2-GHz Bandwidth 4-GSPS ADC
91
Figure 7-26 to Figure 7-30 show the reconstructed spectra for various frequency input
signals and the ADC achieves SFDR, SNDR and ENOB at those frequencies presented in
Table 7-4.
Table 7-4 Dynamic Performance Parameters of Various Frequency Signals
Sig. freq.
200.2 1374 1600 1807 1997
(MHz)
SFDR
33.01 28.42 26.9 29.28 24.99
(dB)
SNDR
23.8 21.08 20.05 19 18.6
(dB)
ENOB
3.66 3.209 3.03 2.864 2.798
(dB)
92
93
94
Figure 7-31 SFDR and SNDR vs. Input Frequencies
95
Figure 7-32 ENOB vs. Input Frequencies
Both SFDR and SNDR for input signal frequency up to 2 GHz at 4 GHz conversion
rate are plotted in Figure 7-31. ENOB for input signal frequency is plotted in Figure 7-32.
The plots show that, with 4 GHz sampling frequency, SFDR of the ADC is stable at 28 dB
and ENOB above 3.2 bits with frequency up to 1.4 GHz. The ENOB is above 3.0 bits with
frequency up to 1.6 GHz, and above 2.8 bits for the Nyquist bandwidth.
96
7.2.2 Comparison with 4-b Flash ADCs in Literature
Table 7-5 Comparison with 4-b Flash ADCs in Literature
The proposed 4-b ADC implemented in the process with smaller feature size, compared
with three referenced ADCs in Table 7-5, with wider bandwidth, lower power and area
consumption in a monolithic architecture with no need of digital calibration. The overall
performance is superior over the other 4-b ADCs in the table.
97
7.3 6-b 4GSPS ADC
After the validity of the comparator dynamic offset suppression and design
optimization is proved in the section 7.1 with a 4-b 2.5-GSPS ADC, a 4-b 4-GSPS ADC
with a higher speed is implemented and presented in the section 7.2. In this section, a 6-b
2.5-GSPS ADC with a higher resolution is implemented in 130nm IBM digital process.
Theoretically, this 6-b ADC can be sampled in a clock signal up to 4-GHz.
This ADC is designed and simulated using Cadence Spectre and VSDE 4.1 (Aptivia).
Figure 7-33 is the schematic diagram of 6-b 2.5-GSPS CDC-based pipelined ADC, which
includes a set of CDC comparators, a TGB encoder and a clock tree. The schematic of the
TGB 6-b encoder is shown in Figure 7-34, which includes a 6-b Gray-to-binary encoding
as in Figure 7-35. The schematic of the clock tree in the ADC is shown in Figure 7-37,
which is much larger than the clock tree for 4-b ADCs. The schematic of 63 CDC
comparators is the same as the one in Figure 7-36, with an input voltage range of Vm from
0.445v to 0.693v with a quantization step size (LSB) equal to 4mv. The CDCs are sized
with Ids as 80µA.
98
Figure 7-33 Schematic of 6-b 2.5GSPS ADC
99
Figure 7-34 Schematic of 6-b TGB Encoder
100
Figure 7-35 Schematic of 6-b Gray-to-Binary Encoding
101
Figure 7-36 63 CDC Comparators
102
Figure 7-37 Schematic of Clock Tree for 6-b ADC
103
Figure 7-38 Outputs of 63 Quantization Inverters at DC
Figure 7-38 presents the voltage transfer characteristics of 63 quantization inverters in
the 6-b ADC. The threshold voltages are regularly spaced.
104
Figure 7-39 Outputs of 6 bits at DC
Figure 7-39 presents 6-bit outputs of the 6-b ADC at DC simulation. It proves that the
6-b ADC functions correctly.
105
Figure 7-40 Spectrum of 12.2MHz Signal
Figure 7-40 presents a reconstructed spectrum of 12.2MHz input signal with 2.5-GSPS
of the 6-b ADC. The ADC achieves 48.03-dB SFDR, 33.46-dB SNDR and 5.3-bits ENOB.
The noise floor is at about -60-dB lower than the signal power.
106
Figure 7-41 Reconstructed Signal and Spectrum of 11.7MHz signal
Figure 7-41 presents a reconstructed signal and spectrum of 11.7MHz input signal with
4-GSPS of the 6-b ADC. The ADC achieves 47.02-dB SFDR, 34.43-dB SNDR and
5.4-bits ENOB. The noise floor is at about -60-dB lower than the signal power.
107
7.3.2 Comparison with State-of-the-art 6-b Flash ADC
There is one 6-b flash ADC designed in 0.13µm digital CMOS process at 1.2-GS/s
reported in IEEE Journal of Solid-State Circuit in 2005 by Sandner and his colleagues from
the Microelectronics Development Center of Siemens AG, now Infineon Technologies, in
Villach, Austria [23]. The flash ADC employs differential comparators and capacitive
interpolation architecture for low power and wide bandwidth. This 6-b flash ADC is used
as a reference to evaluate the proposed 6-b CDC-based pipelined ADC as depicted in Table
7-6.
Table 7-6 Performance Comparison of 6-b Flash ADC

in 130nm Digital CMOS Process
108
The figure of merit (FoM) in the table of the performance comparison is calculated as
Power
FoM = [ pJ / convstep] (7.1)
2 ⋅ 2 ⋅ ERBW
ENOB , DC
The proposed CDC-based pipelined flash ADC achieves a FoM of 0.23pJ/conv. at
2.5-GSPS and 0.17pJ/conv. at 4-GSPS, with smaller area size and similar ENOB
performance at 1.2v supply voltage. The overall performance of our 6-b flash ADC is
better than the ADC in [23]. The achieved performance, large ERBW, high sampling rate,
low power and area consumption, of the 6-b ADC implementation once again prove that
the proposed CDC-based pipelined CMOS flash ADC architecture has superior features
for wideband communication systems-on-a-chip.
109
7.4 Comparison of BDB and TGB Encoders
In this section, comparison of dynamic performance of a 15mv-input-range 4-b
CDC-based pipelined CMOS flash ADC using the BDB encoder and using the TGB
encoder is depicted in Figure 7-42 with 2.5 GSPS and in Figure 7-43 with 4 GSPS.
Sampled at 4 GSPS, the SNDR of ADC using the TGB encoder is constantly 4 to 5 dB
above the SNDR of ADC using the BDB encoder, which accounts for an increased ENOB
by about 0.7 bit.
Figure 7-42 Performance Comparison of the ADC with 2.5-GSPS
110
Figure 7-43 Performance Comparison of the ADC with 4-GSPS
111
Chapter 8 APPLICATION OF 4-B CDC-BASED PIPELINED ADC IN A
DIGITAL WIDEBAND RECEIVER-ON-A-CHIP
This chapter presents a mixed-signal block-level simulation and verification flow in
Cadence AMS integration platform for an 1 GHz bandwidth digital receiver which include
the proposed 4-b 2.5 GSPS CDC-based pipelined CMOS flash ADC. This flow is
different from Simulink-based system-level simulation, by considering the effects
originating from analog and mixed signal subsystem. It involves low-level models of the
devices in critical analog blocks. After the individual blocks have been designed, an AMS
verification flow was built to integrate all the blocks in different level descriptions into one
simulation platform for design verification. With Verilog-AMS, one can create and use
modules that describe the high-level behavior and structure of analog, digital, and
mixed-signal components and systems.
8.1 AMS Verification Flow
The AMS verification flow of the digital receiver is presented in Figure 8-1. It is
composed of signal generation, data collection, and digital signal processing. An analog
input signal and a clock signal need to be generated as the inputs to the receiver. In this
verification, mono-tone or multi-tone sinusoidal input signals and a 2.5 GHz clock signal
are created in Verilog-AMS code with real-time function. The data collection includes a 2.5
112
-GSPS ADC schematic design and a DEMUX in VHDL. The digital signal processor (DSP)
includes a 256-point, 12-point kernel function FFT in VHDL, and a frequency detector in
VHDL. The verification process stimulates the Spectre simulator, Verilog_AMS compiler,
and VHDL compiler for analog and digital mixed signals in the flow. Both the analog
signal and clock signal generator in Verilog_AMS are in Appendix B.
Figure 8-1 AMS Verification Flow of Digital Receiver
8.2 DEMUX Design
Figure 8-2 presents the diagram of DEMUX design. The DEMUX collects 256 sets of
4-b output data of ADC clocked at 2.5 GHz and feed them to the 256-point FFT clocked at
9.76 MHz. Four 16-b shift registers clocked at 2.5 GHz collect the data from the outputs
of 4-b ADC, and transfer the data into sixteen 16x4 pipelined registers at every 6.4 ns. The
sixteen 16x4 pipelined registers transfer the data to a 256x4 pipelined registers at every
102.4 ns. A total of 256x4 bits of data is then sent to the 256-point FFT.
113
Figure 8-2 Diagram of DEMUX
The clock divider in the DEMUX functions as a timing controller. Four 16-b shift
registers are clocked at 2.5GHz, and 256x4 pipelined registers are clocked at 9.76MHz.
Sixteen 16x4 pipelined registers are clocked by sixteen 6.4 ns pulse signals C[0:15] as
shown in Figure 8-3. The 16 states Si of C[0:15] are presented in the state diagram shown in
Figure 8-4. The DEMUX is programmed in VHDL. The code is attached in Appendix C.
114
Figure 8-3 Sixteen 6.4ns Pulse Signals
Figure 8-4 State Diagram of Pulse Signals
115
8.3 Verification Results
Figure 8-5 presents verification results of an input signal frequency of 1125 MHz. The
signal is detected at the frequency bin of 115 of the FFT outputs. The frequency bin of
1125MHz is calculated as
1
× 1125MHz = 115 d = 73 h .
2.5GHz
256
The address y[6:0] of the signal with maximum amplitude is 73h, and the output
x_out[115] has an amplitude of 2Fh which is the highest peak amplitude as shown in Figure
8-5.
Figure 8-5 Bin and Peak Amplitude of 1125MHz Signal

116
Figure 8-6 presents verification results of two simultaneous signals of 700 MHz and 1
GHz. The two frequencies are detected by the receiver. The 700 MHz signal has the highest
peak amplitude of 09h at the frequency bin of 72d and 1GHz signal has 2nd highest peak
amplitude of 05h at the frequency bin of 102d.
Figure 8-6 1st and 2nd Peak Amplitude of 700MHz and 1GHz
117
Chapter 9 CONCLUSIONS
Generally, high-speed flash ADCs use the differential amplifier structure in
pre-amplifier and comparator design. There are two types of offsets in differential
comparators. They are: 1) static and random offsets due to device mismatches, which in
turn would be amplified to larger offsets in output, and 2) dynamic offsets at output of
comparators, which occur due to clock switching in the regenerative latch.
In this dissertation a high-speed clocked digital comparator (CDC) with inverter
configuration for high-speed high-performance CMOS flash ADCs was first proposed.
Both the dynamic offset and the random static offset were reduced by a proposed dynamic
offset suppression technique and a circuit optimization method. Employing a multi-stage
pipelined architecture, a CDC-based pipelined CMOS flash ADC architecture was
presented for high-speed conversion in low-voltage CMOS processes. Three CDC-based
pipelined CMOS flash ADCs were implemented in 130 nm CMOS process. The
experimental results reported the ADCs achieve high sampling rate, high SFDR, low
power, a wide bandwidth up to the Nyquist frequency. These features make “all-digital”
wideband communication SoC become practical.
118
The CDC comparator is a single-ended circuit design. Experiments of temperature
variation on SFDR analysis of 4-b CDC-based ADCs were conducted. FFT Spectra of
400 MHz input signal with -40°C, 25°C, 75°C, 140°C were shown in Figures 9-1, 9-2, 9-3
and 9-4, respectively. Table 9-1 tables the SFDR results. It is shown that the SFDR is
increased with the increase of temperature. Future work of CDC-based pipelined CMOS
flash ADCs includes that, first, since the CDC comparator is the single-ended circuit
design, the impact of the process, voltage and temperature variation on the performance of
CDC-based ADCs will be investigated in detail. Secondly, the CDC comparator design
automation is desired for two reasons; one for easily migrating the design into the different
CMOS processes, and two for enhancing the optimization for the best dynamic
performance.
Table 9-1 Temperature variation on SFDR analysis of 4-b 2.5-GSPS CDC-based ADCs with
input signal frequency of 400 MHz
Temperature -40°C 25°C 75°C 140°C
SFDR(dB) 24.22 29.8 32.32 31.32
119
Figure 9-1 Spectrum of 400MHz Signal with -40°C
Figure 9-2 Spectrum of 400MHz Signal with 25°C
120
121
APPENDIX
A. Estimation of Source and Drain Areas and Peripheries
A simple rectangular MOSFET layout in an inverter is shown in Figure A-1 [10].
L3 L2 L1 L1 L2 L3
Poly W
Diffusion Diffusion
Figure A-1 Estimation of Source and Drain Areas and Peripheries
The minimum possible source or drain area would be that indicated by the sum of the
lengths, L1, L2, and L3 times W. The lengths L1, L2 and L3 are related to the design rules
for a given process and are as follows:
L1 = Minimum allowable distance between the contact in S/D and the poly
L2 = Width of a minimum size contact to diffusion
L3 = Minimum allowable distance from the contact in S/D to the edge of the S/D
122
The minimum area of the drain and source is (L1+L2+L3) × W and the corresponding
periphery is 2(L1+L2+L3) + 2W.
B. Signal / Clock Generators in Verilog_AMS
1. Two-signal Generator
//Verilog-AMS HDL for "usrlib", "analogGen" "verilogams"

`include "constants.vams"
`include "disciplines.vams"
`timescale 1ns/100ps
module analogGen (analsig, Vdd, Vss );
output analsig, Vdd, Vss;

electrical analsig, Vdd, Vss;
parameter real vdd = 1.2, vss = 0;
parameter real frequency1 = 1e9, ampl1 = 0.1;
parameter real frequency2 = 9e8, ampl2 = 0.14;
real tempvar;
analog begin
V(Vdd) <+ transition( vdd );
V(Vss) <+ transition( vss );
V(analsig) <+ (ampl1 * sin(2.0*`M_PI * frequency1 * $abstime)) + (ampl2 *
sin(2.0*`M_PI * frequency2 * $abstime)) + 0.6;
$bound_step(0.02 / frequency1);
end
endmodule
2. Clock Generator
//Verilog-AMS HDL for "adc_ideal", "clk_digital" "verilogams"
`timescale 1ns/100ps
123
module clk_digital ( clk );
output clk;
logic clk;
reg clock;
parameter period = 0.4;
assign clk = clock;

initial
begin
clock = 1'b0;
forever #(period/2) clock = ~clock;
end
endmodule
3. Converting Electrical Signal to Logic Signal
//Verilog-AMS HDL for "usrlib", "electrical_2_logic" "verilogams"
module electrical_2_logic (bit3,bit2,bit1,bit0,clk_in, out3,out2,out1,out0,clk_out);
input bit3, bit2, bit1, bit0, clk_in;

output out3, out2, out1, out0;
output clk_out;
logic out3, out2, out1, out0;
logic clk_out;
electrical bit3, bit2, bit1, bit0, clk_in;
integer temp3,temp2,temp1,temp0;
integer tmp_clk;
assign out3 = temp3;

assign clk_out = tmp_clk;
124
always @ ( above( V(bit3) - 0.6))
temp3 = 1'b1;
always @ ( above( 0.6 - V(bit3)))
temp3 = 1'b0;

temp2 = 1'b1;
temp2 = 1'b0;

temp1 = 1'b1;
temp1 = 1'b0;

temp0 = 1'b1;
temp0 = 1'b0;
always @ ( above( V(clk_in) - 0.6))

tmp_clk = 1'b1;
always @ ( above( 0.6 - V(clk_in)))
tmp_clk = 1'b0;
endmodule
C. DEMUX in VHDL
library ieee,work;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use STD.TEXTIO.ALL;
use WORK.CONV.ALL;
package demux_type is
type state_type is (s0, s1, s2, s3, s4, s5, s6, s7,
s8, s9, s10, s11, s12, s13, s14, s15, s_initial);
type TYPE_DEMUX_ARRAY_16x4 is array(0 to 15) of std_logic_vector(3 downto
0);
type TYPE_DEMUX_ARRAY_256x4 is array(0 to 255) of std_logic_vector(3
downto 0);
type TYPE_DEMUX_ARRAY_16x64 is array(0 to 15) of
TYPE_DEMUX_ARRAY_16x4;
125
end demux_type;
library ieee,work;
use STD.TEXTIO.ALL;
use work.demux_type.all;
use WORK.CONV.ALL;
entity clock_generator is
Port (
clk : IN std_logic;
reset : IN std_logic;
output : OUT std_logic_vector(15 downto 0);
clk_fft : OUT std_logic;
out_clk : OUT std_logic;
out_clk1 : OUT std_logic;
temp_clk : OUT std_logic
);
end clock_generator;
architecture behavior of clock_generator is
----- signal declaration -----

signal current_state, next_state : state_type;
signal clk_16 : std_logic;
----- start -----
begin
clk16: process(reset, clk)
variable count : integer := 0;
begin
if (clk'event and clk='1') then
if (reset = '1') then
current_state <= s_initial;
126
else
count := count + 1;
if (count = 16 and reset /= '1') then
count := 0;
current_state <= next_state;
end if;
end if;
end if;
end process clk16;
-- sync: process( clk_16 )

-- begin
-- if (clk_16'event and clk_16='1') then
-- current_state <= next_state;
-- end if;
-- end if;
-- end process sync;
FSM: process(current_state) -- mod => input is inserted

begin
-- next_state <= s0; -- default assignment;
case current_state is
when s_initial =>
next_state <= s0;
output <= "0000000000000000";
when s0 =>
next_state <= s1;
output <= "0000000000000001";
when s1 =>
next_state <= s2;
output <= "0000000000000010";
when s2 =>
next_state <= s3;
output <= "0000000000000100";
when s3 =>
next_state <= s4;
output <= "0000000000001000";
when s4 =>
next_state <= s5;
output <= "0000000000010000";
when s5 =>
next_state <= s6;
output <= "0000000000100000";
127
when s6 =>
next_state <= s7;
output <= "0000000001000000";
when s7 =>
next_state <= s8;
output <= "0000000010000000";
when s8 =>
next_state <= s9;
output <= "0000000100000000";
when s9 =>
next_state <= s10;
output <= "0000001000000000";
when s10 =>
next_state <= s11;
output <= "0000010000000000";
when s11 =>
next_state <= s12;
output <= "0000100000000000";
when s12 =>
next_state <= s13;
output <= "0001000000000000";
when s13 =>
next_state <= s14;
output <= "0010000000000000";
when s14 =>
next_state <= s15;
output <= "0100000000000000";
when s15 =>
next_state <= s0;
output <= "1000000000000000";
end case;
end process FSM;
gen_out_clk: process(current_state)
begin
if ( current_state = S0 or current_state = S1 or current_state = S2 or current_state =

S3 or current_state = S4 or current_state = S5 or current_state = S6 or current_state = S7)
then
clk_fft <= '1';
else
clk_fft <= '0';
end if;
--- This clk will synchronize all the pipelines flip-flops ---
128
if (current_state = S0 or current_state = S1) then
out_clk <= '1'; -- high from 0 to 12.8ns
else
out_clk <= '0';
end if;
--- This clk will go to initial_sort subsystem ---

--- and latch the sel_high_low into their flip-flops ---
out_clk1 <= '1'; -- high from 19.2 to 32ns
else
out_clk1 <= '0';
end if;

out_clk2 <= '1'; -- high from 44.8 to 57.6ns
else
out_clk2 <= '0';
end if;

out_clk3 <= '1'; -- high from 51.2 to 64ns
else
out_clk3 <= '0';
end if;

else
out_clk4 <= '0';
end if;

else
out_clk5 <= '0';
end if;

temp_clk <= '1'; -- high from 83.2 to 96ns
else
temp_clk <= '0';
end if;
end process gen_out_clk;
129
end behavior;
-------------------------------------------------------
-------------------------------------------------------
library ieee,work;
use STD.TEXTIO.ALL;
use WORK.CONV.ALL;
entity latch_v1 is
port ( clk : IN std_logic;
input : IN std_logic;
output : OUT std_logic
);
end latch_v1;
architecture behavior of latch_v1 is
begin
test : process(clk)
begin
if ( clk'event and clk='1') then
output <= input;
end if;
end process test;
end behavior;
-------------------------------------------------------
-------------------------------------------------------
library ieee,work;
use STD.TEXTIO.ALL;
use WORK.CONV.ALL;
entity latch_v1_4_p is
input : IN std_logic_vector(3 downto 0);
output : OUT std_logic_vector(3 downto 0)
);
end latch_v1_4_p;
130
architecture structure of latch_v1_4_p is
component latch_v1
input : IN std_logic;
output : OUT std_logic
);
end component;
begin
latch0: latch_v1 port map (clk,input(0),output(0));

end structure;
-------------------------------------------------------
-------------------------------------------------------
library ieee,work;
use STD.TEXTIO.ALL;
use WORK.CONV.ALL;
entity latch_v1_4_p_16 is
output : OUT TYPE_DEMUX_ARRAY_16x4
);
end latch_v1_4_p_16;
architecture structure of latch_v1_4_p_16 is
component latch_v1_4_p
);
end component;
signal temp_output : TYPE_DEMUX_ARRAY_16x4;
131
begin
latch0: latch_v1_4_p port map (clk,input,temp_output(15));

latch1: latch_v1_4_p port map (clk,temp_output(15),temp_output(14));
output <= temp_output;
end structure;
-------------------------------------------------------
-------------------------------------------------------
library ieee,work;
use STD.TEXTIO.ALL;
use WORK.CONV.ALL;
entity latch_v1_4_p_16_p is
input : IN TYPE_DEMUX_ARRAY_16x4;
);
end latch_v1_4_p_16_p;
architecture structure of latch_v1_4_p_16_p is
component latch_v1_4_p
);
end component;
132
begin
block_16_latch0: latch_v1_4_p port map (clk, input(15), output(15));

end structure;
-------------------------------------------------------
-------------------------------------------------------
library ieee,work;
use STD.TEXTIO.ALL;
use WORK.CONV.ALL;
entity latch_v1_4_p_16_p_16 is
port ( clk : IN std_logic_vector(15 downto 0);
output : OUT TYPE_INPUT_FFT
);
end latch_v1_4_p_16_p_16;
architecture structure of latch_v1_4_p_16_p_16 is
component latch_v1_4_p_16_p
);
end component;
signal tmp_output : TYPE_DEMUX_ARRAY_16x64;
133
begin
block_64_latch0: latch_v1_4_p_16_p port map (clk(0),input,tmp_output(0 ));

output(0) <= tmp_output(0)(0);
block_64_latch1: latch_v1_4_p_16_p port map (clk(1),input,tmp_output(1));


134


135



136


137



138


139

end structure;
library ieee,work;
use STD.TEXTIO.ALL;
use WORK.CONV.ALL;
entity demux is
port ( clk,reset : IN std_logic;
output: OUT TYPE_INPUT_FFT
);
end demux;
architecture structure of demux is
component latch_v1_4_p_16
);
end component;
140
component latch_V1_4_p_16_p_16
port ( clk : IN std_logic_vector(15 downto 0);
output : OUT TYPE_INPUT_FFT
);
end component;
component clock_generator
reset : IN std_logic;
output : OUT std_logic_vector(15 downto 0);
out_clk : OUT std_logic;
temp_clk : OUT std_logic
);
end component;
signal bus_64 : TYPE_DEMUX_ARRAY_16x4;

signal clk_state : std_logic_vector(15 downto 0);
--signal clk_fft : std_logic;
signal out_clk, out_clk1, out_clk2 : std_logic;
signal out_clk3, out_clk4, out_clk5, temp_clk : std_logic;
begin
u0: clock_generator port map

(clk,reset,clk_state,clk_fft,out_clk,out_clk1,out_clk2,out_clk3,out_clk4,out_clk5,temp_cl
k);
-- clk_fft <= clk_fft;
u1: latch_v1_4_p_16 port map (clk,input,bus_64);
u2: latch_v1_4_p_16_p_16 port map (clk_state, bus_64, output);
end structure;
141
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HIGH-SPEED LOW-POWER CMOS FLASH

ANALOG-TO-DIGITAL CONVERTER FOR WIDEBAND

A dissertation submitted in partial fulfillment of the

September 11, 2007

I HEREBY RECOMMEND THAT THE DISSERTATION PREPARED UNDER

Wang, Mingzhen, Ph.D, Engineering Ph.D Program, Department of Electrical Engineering,

With higher-level integration driven by increasingly complex digital systems and

downscaling CMOS processes available, system-on-a-chip (SoC) is an emerging

attractive for applications in high-speed data conversion wireless and wideband

deterioration in scaling-down CMOS processes. By developing a dynamic offset

dB frequency of 2 GHz in 130 nanometer (nm) CMOS process.

Combining this new comparator design and a proposed pipelined thermometer-Gray-

binary encoder designed by the DCVSPG logic, a high-speed, low-voltage clocked-digital-

nm CMOS process and their experimental results are reported:

of 1-GHz, power of 7.9-mW, and area of 0.022-mm2.

2-GHz, power of 11-mW.

3. 6-b, 4-GSPS ADC: SFDR of 48-dB at a signal frequency of 11.72-MHz, SNDR of

34.43-dB, ENOB of 5.4-b, power of 28-mW.

An application of the proposed CDC-based pipelined CMOS flash ADC is 1-GHz

1.1 Background ............................................................................................... 1

Chapter 2 ADC Fundamentals ......................................................................................7

2.1 Primary Characteristics............................................................................. 8

Chapter 3 ADC Literature Review..............................................................................15

3.1 Architecture Overview............................................................................ 15

Chapter 4 High-Speed ADCs in Wideband Receivers ...............................................22

4.1 Spurs in Spectrum ................................................................................... 23

Chapter 5 Clocked Digital Comparator......................................................................32

Chapter 7 Implementation and Performance of CDC-based Pipelined CMOS Flash

7.1 4-b 1.25-GHz Bandwidth 2.5-GSPS ADC.............................................. 67

Chapter 8 Application of 4-b CDC-based Pipelined ADC in a Digital Wideband

8.1 AMS Verification Flow..........................................................................112

A. Estimation of Source and Drain Areas and Peripheries ........................ 122

Figure 2-1 N = 3 Quantization Steps ............................................................................................. 9

Figure 3-1 Resolution N vs. Sampling Frequency fsampling............................................................ 16

Figure 5-1 Inverter Amplifier with Voltage-Transfer Characteristics.......................................... 34

Figure 7-1 Schematic of 4-b 1.25-GHz Bandwidth 2.5-GSPS ADC ........................................... 69

Figure 8-1 AMS Verification Flow of Digital Receiver ............................................................ 113

Figure 9-1 Spectrum of 400MHz Signal with -40°C................................................................. 120

Table 3-1 Comparison to State-of-the-art GHz Flash ADCs ....................................................... 19

Table 7-1 Dynamic Performance Improvement Rate of the ADC ............................................... 80

dissertation research work. My most sincere gratitude belongs to my dissertation advisor,

be a special journey in my professional life.

encouragement and guidance during my graduate study. I am truly grateful to Prof.

willing to serve on my dissertation committee.

completed successfully in that short time.

I extend my acknowledgements to Sheila Hollenbaugh and the Department of

Program for the financial support.

I am most grateful to my family, my husband and daughter, my mom, my brothers and

My husband and our daughter, Li and Jiechen.

Analog-to-digital converters (ADCs) are electronic circuits that convert continuous

consumption, which vary with a variety of applications. In addition, selection of an ADC

for an individual application is essential for cost effectiveness.

With higher-level integration driven by increasingly complex digital systems and

downscaling processes available, system-on-a-chip (SoC) is an emerging technology for

conversion, especially consumer electronic devices. SoC integrates all components of

become an emerging technology in the semiconductor industry.

However, shrinking the feature size of the semiconductor technology makes

high-speed high-performance ADC design quite challenge in a standard CMOS technology,

approaching the 45 nanometer feature size, pushing development of SoC applications to a

Giga-sample-per-second (GSPS) flash-based ADCs in CMOS technology were