Interconnect Tutorial:

A Complex, Important Integration Evolution to sub-

14nm Technology Nodes
Kevin Boyd
Deputy Director, BEOL Integration , Advanced Technology Development
SPCC
2018 Agenda

• Defining Interconnects
• Interconnect Fundamentals
– Yield, Reliability, Structural Integrity, Performance
– Metallization evolution
• Al, Ti, W, Ta, Cu, Co, Ru
– Dielectric evolution
• TEOS, FTEOS, Low K, ULK, airgaps
– Integration evolution
• Single-Damascene, TFVL, VFTL, TFHM, SADP
• EUV

• Interconnect Scaling
– Power, Performance, Area, Cost
– Tradeoffs in the 7nm and 5nm Nodes: Design, Dielectrics, Metals

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SPCC
2018 Agenda

• Defining Interconnects
• Interconnect Fundamentals
– Yield, Reliability, Structural Integrity, Performance
– Metallization evolution
• Al, Ti, W, Ta, Cu, Co, Ru
– Dielectric evolution
• TEOS, FTEOS, Low K, ULK, airgaps
– Integration evolution
• Subtractive RIE, Single-Damascene, TFVL, VFTL, TFHM, LELE, SADP
• EUV

• Interconnect Scaling
– Power, Performance, Area, Cost
– Tradeoffs in the 7nm and 5nm Nodes: Design, Dielectrics, Metals

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SPCC
2018 Defining Interconnects

• Definitions

BEOL = Back End of Line M1

Wiring (Global Interconnect)
V0

MOL = Middle of Line

Local Interconnect CA

TS

FEOL = Front End Of Line Gate

Transistors/Devices
Perpendicular to gate
Parallel to gate

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SPCC
2018 Agenda

• Defining Interconnects
• Interconnect Fundamentals
– Yield, Reliability, Structural Integrity, Performance
– Metallization evolution
• Al, Ti, W, Ta, Cu, Co, Ru
– Dielectric evolution
• TEOS, FTEOS, Low K, ULK, airgaps
– Integration evolution
• Subtractive RIE, Single-Damascene, TFVL, VFTL, TFHM, LELE, SADP
• EUV

• Interconnect Scaling
– Power, Performance, Area, Cost
– Tradeoffs in the 7nm and 5nm Nodes: Design, Dielectrics, Metals

5
SPCC
2018
Interconnect Fundamentals

• Interconnect Used in Integrated Circuits

– MOL
• Local Interconnect
– Short-length, impacts device performance, connects devices to wiring

– BEOL
• Short-range Digital Signals (e.g. between devices within logic blocks)
– Minimum-pitch, high frequency, low C desired, low EM risk

• Clock Tree
– Some minimum-pitch, high frequency, low RC desired, mild EM risk

• Long-distance Data Transfer (e.g. memory to CPU)

– High-speed, low attenuation/distortion, low RC desired, moderate EM risk

• Power Grid
– Wide lines, low R desired, high EM risk

Interconnects must meet a variety of (often opposing) circuit wiring needs6

SPCC
2018 Interconnect Fundamentals

• Interconnect Impact on Product Performance

“People talk about reaching the end of Moore’s Law, but really, it’s irrelevant. Transistors
are not a rate-limiting factor in today’s computers. We could improve transistors by a
factor of 1,000 and it would have no impact on the modern computer. The rate-limiting
parts are how you store and move information.”
S. Williams (HP), 2013

“Processor chips since around 2000 are power - not area - limited. All of the power is
spent moving data around. It is important to optimize the entire interconnect
system – the wire, the circuit, and the NoC together – not just each of the three in
isolation.”
B. Dally (NVIDIA), 2012 (also quoting C. Moore (AMD), 2011)

“The interconnect challenges looking into the future are even more daunting than
the compute challenges.”
S. Borkar (Intel), 2012

Interconnect is now a rate-limiting factor to overall product performance

Compiled by J. Candelaria, SRC, 2014 7
SPCC
2018 Interconnect Fundamentals

• Interconnect Impact on Product Performance

– RC Performance

ITRS, 1997

Interconnect RC delay is a dominant factor to overall product performance

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SPCC Defining Interconnects
2018

BEOL
17 metal
level stack

MOL
FEOL 9
SPCC
2018 Interconnect Fundamentals

• Interconnect Impact on Product Performance

– Yield
– Reliability
– Structural Integrity (Chip Package Integration = CPI)
– Performance (RC)
Random Regional Semi-regional
Fail Fail Fail

Yield Reliability CPI Performance (RC)

Interconnect directly impacts a broad range of product performance metrics

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SPCC
2018 Interconnect Fundamentals

• Interconnect Impact on Product Performance

– Yield
• AutoRegressive Integrated Moving Average = ARIMA
• Time To Market = TTM

Interconnect is a key contributor to logic and memory yield, ARIMA (TTM)11

SPCC
2018 Interconnect Fundamentals

• Interconnect Impact on Product Performance

– Reliability Failure Modes

• Intrinsic (wear-out)
• Extrinsic (defects, process integrity issues)

Degraeve et al.,
TED, 1998

Intrinsic fail
Extrinsic fail

Interconnect must withstand intrinsic and extrinsic fail modes, including EM

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SPCC
2018 Interconnect Fundamentals

• Interconnect Impact on Product Performance

– Intrinsic Reliability (Electromigration = EM)

• Elevated temperature and applied voltage direct Cu ions toward vacancies
• Activation energy (eV) describes the likelihood for diffusion
• Diffusion depends on temperature, current density, diffusion path and mechanical
stress conditions
– There are generally two modes of EM failure:

Interconnect must be optimized to alleviate surface and interface-driven EM

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SPCC
2018 Interconnect Fundamentals

• Interconnect Impact on Product Performance

– Intrinsic Reliability (Stress Migration = SM)
• Similar fail mode as EM (i.e. void formation), but driving force is physical stress
• Void typically forms under via (highest mechanical stress gradient)

E. Ogawa, IRPS (2002)

Interconnect must be optimized for SM, especially for vias over wide lines
SPCC
2018
Interconnect Fundamentals

• Interconnect Impact on Product Performance

– Intrinsic Reliability (Time Dependent Dielectric Breakdown = TDDB)
• The loss of insulation between
neighboring interconnects  Leakage
current and short failures

− Failure rate depends upon electric

field Interfacial
Failure
− For a given potential difference,
Dielectric
minimum spacing determines Cap
maximum electric field strength Barrier
Failure
Cu Line
− Hot charge carriers cause defects in
the dielectric, which accumulate over
time
− Electric field can cause Cu+
migration along interfaces or through K. Yiang et al., IRPS, 2005
faulty barriers

Dielectric and metal interfaces must be optimized to withstand intrinsic TDDB

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SPCC Interconnect Fundamentals
2018

• Interconnect Impact on Product Performance

– Structural Integrity (Chip Package Integration = CPI)
• Different thermal expansions
between Si-Die and Package and
Lid (CTE mismatch)
• Mechanical stress on
Interconnect stack, Bumps,
Underfill
• Cracks, Delamination

BEOL Stack must withstand CTE mismatch, mechanical stress in package 16

SPCC
2018
Interconnect Fundamentals

• Interconnect Impact on Product Performance

– RC Performance (Cu resistivity as a function of linewidth)

Rossnagel, IBM, Semicon 2004

Electron mean free path (Cu)

(39nm)

G. Schindler et al., AMC., 2002.

Sidewall/grain boundary scattering, barrier thickness affect Cu line resistivity

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SPCC
2018 Interconnect Fundamentals

• Interconnect Impact on Product Performance

– RC Performance (narrow Cu linewidths)

• Sidewall Scattering
– As Cu linewidth approaches mean free path (~39nm),
sidewall scattering effects become more pronounced

• Grain Boundary Scattering

– More important in narrow lines with small grains
– Less important for wide lines, bamboo structure

• Barrier Thickness Scaling

– Barrier (high resistivity) thickness must scale with cross-
sectional area to avoid R increase

Sidewall/grain boundary scattering, barrier thickness affect

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Cu line resistivity
SPCC
2018 Interconnect Fundamentals

• Metallization Evolution
– BEOL: Al  Cu

(1996)

http://web.stanford.edu/class/ee311/NOTES/Interconnect_Al.pdf, K. Saraswat

Cu replaces Al/W to mitigate interconnect RC delay in ≤180nm nodes

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SPCC
2018
Interconnect Fundamentals

• Metallization Evolution
– BEOL: Cu  Enhanced Cu (Mn)
99
Cu-Mn 0.25%
Cu-Mn 0.5% CuMn
95 Cu-Mn 0.75%
90 Cu-Mn 1.0%
POR
80
70
Percent

60
50
Cu
40
30
20
10
5

1
1 10 (hrs)
TTF 100
CuMn seed improves Lifetime [a.u.]
EM performance, but with increase in line resistance
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SPCC
2018
Interconnect Fundamentals

• Metallization Evolution
– BEOL: Cu  Enhanced Cu (Co)
• CVD Co liner greatly enhances seed
wetting and nucleation, improving
sidewall coverage and void-free fill
• Selective Co cap enhances resistance
to electromigration

Co liner improves Cu seed wetting and nucleation, Co cap improves EM

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SPCC
2018
Interconnect Fundamentals

Capacitance (aF/µm)
• Dielectric Evolution
– TEOS  FTEOS  Low K  ULK

7
Si3N4 Dielectric
6
capping layer
SiCN
Sheet Resistance (ohm/sq)
5
Intrinsic k values

SiO2 Dielectric material Low K SiCN / Adv. ESL

4
SiOF (FTEOS)
F doping

3 SiCOH3.0
SiCOH2.7
Porous

Ultra Low k (ULK) 2.45

2

Air Gap
1

Technology Node

Low dielectric constant (ĸ) materials (e.g. low density, porous) reduce Ctotal
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SPCC
2018 Interconnect Fundamentals

• Dielectric Evolution
– TEOS  FTEOS  Low K  ULK

• To reduce ĸ from ~4.2 to ~2.7

– F doping (~3.9 - ~3.6)
– C doping (~3.2 - ~2.7)
– Reduction in film density
• To reduce ĸ below 2.7
– New dielectric materials
– Introduce/increase porosity for
SiO2-based system
• Lowering ĸ value degrades
thermomechanical materials
properties
– Modulus, hardness, stress, and
thermal conductivity

Lowering dielectric constant (ĸ value) degrades thermomechanical strength

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SPCC
2018 Interconnect Fundamentals

• Dielectric Evolution
– Low K  Ultra Low K (ULK)  Airgaps

1.4
Normalized Sheet Resistance

1.3 ULK

1.2 Low-k
D. Edelstein et al, AMC 2005
1.1 Nitta et al., IITC 2008

12%
1.0

0.9

0.8

0.7
0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 http://www.electroiq.com/articles/sst/print/vol
ume-53/issue-6/features/interconnects_low-
Normalized Capacitance /air-gaps_for_interconnects.html

Porous ULK reduces C over Low ĸ, airgaps reduce further (but CPI risk)
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SPCC
2018 Interconnect Fundamentals

• Process Integration Evolution

– Single-Damascene (Cu)  Dual-Damascene TFVL/VFTL
• Trench First Via Last = TFVL
• Via First Trench Last = VFTL

Dual-damascene integrations more cost-effective than single-damascene

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SPCC
2018
Interconnect Fundamentals

• Process Integration Evolution

– VFTL  TFMH SADP (next page)
VFTL (Via First Trench Last)
ILD Dep + Trench Trench Etch Barrier/Seed
Via Litho Via Etch Litho + Wet clean + Cu Plating CMP
Resist
ARC
Under layer
Oxide Cap

ILD
Etch stop

TFMH (Trench First

ILD Dep + Metal Hardmask) ILD Etch
HM Dep + Barrier/Seed
HM Open Via Litho (Via + Trench) CMP
Resist Trench Litho + Cu Plating
+ Wet Clean
ARC
Under layer
Metal HM
Oxide Cap
ILD

Etch stop

Advanced technology nodes require more complex integration

26
Matthias Lehr
SPCC
2018
Interconnect Fundamentals

• SADP Integration
Mandrel Litho/Etch Spacer Deposition/Etch CUT Litho/HMO Trench/Via Etch

M1 Cu M1 Cu
M1 Cu
Levels Below M1…
M1 Cu
Levels Below M1…
Levels Below M1…
Levels Below M1…

Metallization/CMP

M1 Cu
M1 Cu M1 Cu
M1 Cu

Levels Below M1…

Levels Below M1…
Levels Below M1… Levels Below M1…

Top Down View Loops

Top Down View Top Down View Top Down View
formed by
spacer

Advanced technology nodes require more complex integration

27 Matthias Lehr
SPCC
2018 Interconnect Fundamentals

• Process Integration Evolution

– Extreme UltraViolet Lithography = EUV

Reference: ASML tech symposium and http://www.nature.com/articles/srep09235

EUV needed at 7nm/5nm nodes to reduce complexity of optical integrations

EUV challenges: droplet generator, collector lifetime, tool uptime, pellicle/mask, resist
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SPCC
2018
Agenda

• Defining Interconnects
• Interconnect Fundamentals
– Yield, Reliability, Structural Integrity, Performance
– Metallization evolution
• Al, Ti, W, Ta, Cu, Co, Ru
– Dielectric evolution
• TEOS, FTEOS, Low K, ULK, airgaps
– Integration evolution
• Subtractive RIE, Single-Damascene, TFVL, VFTL, TFHM, LELE, SADP
• EUV

• Interconnect Scaling
– Power, Performance, Area, Cost
– Tradeoffs in the 7nm and 5nm Nodes: Design, Dielectrics, Metals

29
SPCC
2018
Interconnect Scaling

• Power, Performance, Area, Cost

14nm, Area =1 10nm, Area =0.56 7nm, Area =0.33 5nm, Area =0.17

• 0.7X pitch scaling equates to ~50% area scaling

• Minimum-pitch lines and wide power rails exist within same metal layer
• Sub-14nm node patterning requires additional design restrictions
(e.g. bidirectional to unidirectional)

Interconnect scaling into the sub-14nm nodes requires architectural change

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SPCC
2018 Interconnect Scaling

• Tradeoffs in the 7nm and 5nm Nodes: Design

Unrestricted Partially-restricted More-restricted

• Partial layout restrictions can greatly reduce metal complexity while
maximizing line end extensions
• Completely unidirectional routing allows fewest design-sensitive systematics,
enables LELE or SADP

Layout restrictions are increasingly important in lower metal layers due to

tradeoffs in area, track utilization, and pin count 31
SPCC
2018 Interconnect Scaling

• Tradeoffs in the 7nm and 5nm Nodes: Design

Before After
Optimization Optimization

• Even with significant design and process optimization, process windows

can span only several nanometers

Product-level logic yields more restricted by systematic design weakpoints

 SPCC
2018 Interconnect Scaling

• Tradeoffs in the 7nm and 5nm Nodes: BEOL (Dielectrics)

Reduced Sensitivity Minimized

To Process Damage Hard Mask
Undercut

E.T. Ryan et al., IITC, 2015

Improvements in dielectric mechanical strength and resistance to process

damage allow for more robust process integration, improved reliability (TDDB)
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 SPCC
2018 Interconnect Scaling

• Tradeoffs in the 7nm and 5nm Nodes: BEOL (Dielectrics)

New dielectric hard mask and capping (and/or etch stop layers) materials can
reduce integrated aspect ratios, greatly enhance metallization process window

34
SPCC
2018
Interconnect Scaling

• Tradeoffs in the 7nm and 5nm Nodes: BEOL (Metals)

64nm Pitch 45nm Pitch 34nm Pitch
Cu >80% of Area ~70% Cu <60% Cu

Plated Cu

Cu Seed
Liner
Barrier

• Structural (e.g. increased aspect ratio) and Materials (e.g. CVD seed
enhancement/liners/alloys/metals) changes are needed to enable pitches
below 45nm; more radical changes may be necessary for pitches <34nm
Structural or materials changes are needed to continue Cu interconnect scaling
35
SPCC
2018 Key Messages

• Interconnect (MOL/BEOL) is both increasingly complex

and increasingly important in sub-14nm Technology
Nodes

• Lower resistivity metals will continue to move from the

BEOL into MOL with further dimensional scaling (BEOL
will consume MOL)

• Even with EUV, CD and overlay control will continue to

become increasingly challenging

• New materials, methods, and integrations will be

needed to continue performance improvement and
differentiation at product/system-level
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SPCC
2018 Acknowledgements

• Robert Fox
• Rod Augur
• Seungman Choi
• E. Todd Ryan
• Keith Tabakman
• Bill Taylor
• André Labonté
• Patrick Justison
• Matthias Lehr
• Oliver Aubel
• Luke England
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SPCC
2018 References

• “The Struggle to Keep Scaling BEOL, and What We Can Do Next”, R. Augur, IEDM, 2016.
• “Moving Boundaries: Material Innovations for Future BEOL Interconnects”, E. Todd Ryan, N.
LiCausi, L. Liebman, B. Briggs, X. Zhang, X. Lin, J. Kelly, S. Nguyen, MRS, February 2017.
• “Process Window Challenges in Advanced Manufacturing: New Materials and Integration
Solutions”, R. Fox, R. Augur, C. Child, M. Zaleski, AMC, September 2015.
• “A Survey Addressing on High Performance On-Chip VLSI Interconnect”, C. Mohamed Yousuff,
V. Mohamed Yousuf Hasan, and M. R. Khan Galib, International Journal of Electronics and
Telecommunications, 2013, Vol. 59, No. 3, pp. 307–312.
• “Electromigration - A Brief Survey and Some Recent Results”, James R. Black, IEEE Trans. Elec.
Dev. 16 (4): 338–347, April 1969.
• “Strategies to Ensure Electromigration Reliability of Cu/Low-k Interconnects at 10 nm”, Anthony S.
Oates, ECS J. Solid State Sci. Technol.2015 volume 4, issue 1.
• “Addressing Cu/Low-k Dielectric TDDB-Reliability Challenges for Advanced CMOS Technologies”,
F. Chen, M. Shinosky, IEEE Transactions on Electron Devices, volume 56, issue 1, Jan. 2009.
• “Progress in the development and understanding of advanced low k and ultralow k dielectrics for
very large-scale integrated interconnects—State of the art”, A. Grill, S. M. Gates, E. T. Ryan, S. V.
Nguyen and D. Priyadarshini, Appl. Phys. Rev. 1, 011306 (2014).
• “Process technology scaling in an increasingly interconnect dominated world”, J. S. Clarke, C.
George, C. Jezewski, A. Maestre Caro, D. Michalak, J. Torres, VLSI Technology, Digest of
Technical Papers, 2014.
• “Optimizing ULK Film Properties to Enable BEOL Integration with TDDB Reliability”, E.T. Ryan,
IITC 2015.
• “Electrical Reliability Challenges of Advanced Low-k Dielectrics”, C. Wu, Y.Li, M.R. Baklanov, K.
Croes, ECS J. Solid State Sci. Technol. 2015 volume 4, issue 1.
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SPCC
2018 References
• “Characterization of ‘Ultrathin-Cu”’Ru(Ta)/TaN Liner Stack for Copper Interconnects”, C.-C. Yang,
S. Cohen, T. Shaw, P.-C. Wang, T. Nogami, D. Edelstein, IEEE ELECTRON DEVICE LETTERS,
VOL. 31, NO. 7, JULY 2010.
• “Comprehensive study of the resistivity of copper wires with lateral dimensions of 100 nm and
smaller”, W. Steinhögl, G. Schindler, G. Steinlesberger, M. Traving, M. Engelhardt, J. Appl. Phys. 97,
023706 (2005).
• “Electron scattering at surfaces and grain boundaries in Cu thin films and wires”, J. S. Chawla,
F. Gstrein, K. P. O’Brien, J. S. Clarke, and D. Gall, Phys. Rev. B 84, 235423.
• “Effects of microstructure on interconnect and via reliability: Multimodal failure statistics”,
C. V. Thompson, H. Kahn, J. of Electronic Materials, June 1993, Vol. 22, Issue 6, pp 581–587.
• “Improved Reliability of Copper Interconnects Using Alloying”, J.P. Gambino, Proc.17th IEEE IPFA,
pp 1-7 (2010).
• “Electromigration-resistance enhancement with CoWP or CuMn for Advanced Cu Interconnects”,
C. Christiansen, B. Li, Matthew Angyal, T. Kane, V. McGahay, Y. Y. Wang, S. Yao, IRPS 2011.
• “Co Capping Layers for Cu/Low-k Interconnects”, C.-C.Yang, P. Flaitz, B. Li, F. Chen,
C. Christiansen, D. Edelstein, S.-Y. Lee, P. Ma, AMC 2010.
• “Effects of cap layer and grain structure on electromigration reliability of Cu/low-k interconnects for
45 nm technology node”, L. Zhang, J. P. Zhou, J. Im, P. S. Ho, O. Aubel, C. Hennesthal, E. Zschech,
IRPS 2010.
• “Plasma Etch Challenges for Porous Low k Materials for 32nm and Beyond”, Cathy Labelle, C.
Sandow, S. Schmidt, S. Richter, W. Yu, B. Zhang, Q. T. Zhao and S. Mantle, CSTIC, 2011.
• “Photonic Integration for Interconnect”, W. Bogaerts, P. Absil, Photonics Integration Forum,
Eindhoven, 22 June 2011.
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