CMOS DEVICE ARCHITECTURE EVOLUTION AND METROLOGY

CHALLENGES
NAOTO HORIGUCHI, IMEC

CONFIDENTIAL
OUTLINE

 CMOS scaling trend and imec device roadmap

 Device scaling and metrology challenges
 FinFET
 Horizontal nanowire FET
 Vertical nanowire FET
 TFET
 2D material devices
 Summary

2 CONFIDENTIAL
CMOS SCALING TREND
TRANSISTOR ARCHITECTURE UNDER PRESSURE
7(?)-5nm: Finfet with
channel stress and/or
Nanowire introduction

log2(#transistors/$)
2.5nm & beyond
14nm: Si FinFET device STCO 3D (Vertical) Logic
– improved Hybrid stacking
electrostatics, current Beyond CMOS
density, and mismatch 1.75nm
DTCO 2.5nm New compute paradigms
20nm: Planar device runs 3.5nm
out of steam - electrostatics 5nm
7nm 2.5nm: Fin/Nanowire
10nm
devices run out of steam
14nm
20nm Less happy scaling era
28nm Still doubles but device
Happy scaling era 40nm scaling provides diminishing
# transistors per area returns
65nm
doubles every two year

NOW
for same cost 90nm

2005 2007 2009 2011 2013 2015 2017 2019 2021 2023 2025
Focus of process technology innovation is
Scale device and wire Scale basic logic cells Scale (sub-)system functions CONFIDENTIAL
IMEC HIGH PERFORMANCE MOBILE LOGIC ROADMAP
Early fdry 2014 2016-2017 2018-2019 2020-2021 2022-2023 2023-...
production N14 (industry ref.) iN10 iN7 iN5 iN3

Finfet
Finfet Finfet
HGAA
Ch-Ge Ch-IIIV
Horizontal nanowire
stacked devices (CFET)

Vdd (V) 0.8 0.8-0.7 0.7-0.6 0.7-0.5 0.6-0.5

Device FinFET FinFET FinFET or HGAA FinFET or HGAA HGAA Vertically integrated
device circuits
Channel nfet/pfet Si / Si Si / Si {SiGe} Si / SiGe Si/ SiGe (Higher mobility)
Gate Pitch (nm) 70-90, 193i 64, 193i 42, 193i 32, EUV TBD
Gate length (nm) 30 24 20 18-14 14-10
Contact metal W W W or Co Alternative metal Alternative metal
Metal Pitch (nm) 52-64, 193i 42, 193i 32, 193i, EUV cut/Via 24, EUV 18, EUV
New functional scaling on top
Low k dielectric 2.55 2.55 2.55-2.4 2.7-2.4 2.7-2.1 of base CMOS:
Mn/Ru + Cu and/or Spintronics, 2D devices,
Metallization TaN/Ta + Cu TaN/Co + Cu TaN/Ru + Cu Alternative metals (Steep-Slope switches)
Co via prefill

iNxx = imec node xx; *h/v GAA = horizontal/vertical Gate-All-Around; CONFIDENTIAL

ENHANCE PITCH-BASED SCALING WITH DTCO
CONTACTED GATE PITCH SCALING
16/14nm 10nm 7nm 5nm
1st gen scaling boosters: 2nd gen scaling boosters:
Pitch scaling o M1/CGP gear o Self aligned gate contact
Fins x0.61 o Single diffusion break o Fully self aligned via
Contacted Gate Pitch (CGP) Scaling  Gate length scaling
o Self aligned block o Super Via
x0.83 DTCO o In line merged via o Buried power rail
Fin # Fins
scaling  Fin height increase or high mobility channel
o Open M1architecture …
x0.51
Pitch scaling
Fins
Gates x0.67
x0.80 DTCO
Fins
x0.54
Pitch scaling
Gates Fins
x0.61
Fins x0.84 DTCO
Gates
Gates x0.51
Fins

9-tracks 7.5-tracks 6-tracks 6-tracks Fins

CGP = 78 SP CGP = 64 SADP/LELE CGP = 52 SADP CGP = 40 SADP
MP = 64 LELE MP = 48 SADP/LELE MP = 40 SADP MP = 32 EUV SP
FP = 48 SADP FP = 36 SAQP FP = 30 SAQP FP = 24 SAQP
4-fin 3-fin 2-fin 2-fin or stacked-NW
CONFIDENTIAL
DEVICE ARCHITECTURE IMPACTS ELECTROSTATICS

Subthreshold Swing (mV/dec)

Ultra-Thin Fin Straight Fin Tapered Fin
120
FinW=5nm FinW=7-8nm FinW=7-10nm
110
Lmin~ 18nm Lmin~ 22-24nm Lmin~ 28nm
100
90 28-32nm
Bulk Planar
80 (Vdd ~ 0.9-1.0V)
70 FinFETs
60
N5 N7 N10 N14 N22 (Vdd ~ 0.7-0.8V)
10 15 20 25 30
Lg (nm)
 FinFETs offered a Low-Voltage transistor option wrt bulk planar.
 To maintain electrostatics, fin width scaling is necessary.
6 CONFIDENTIAL
FIN SCALING

10 nm 45 nm 5 nm
30 nm 25 nm

50 nm
• Continuous fin pitch & cd scaling from SADP to SAQP
• Fin height increase for accelerate scaling and performance
 High aspect ratio in fin and subsequent modules
5 CONFIDENTIAL
 SCALED FINFET METROLOGY CHALLENGES Stress measurement in fin
CD & overlay measurements in high AR 3D structures

• Gate cd (@ fin sidewall) Dopant diffusion & activation

• Gate height in fin & SD
• Gate profile

Composition in thin
Fin film & interface
Fin
Defects
Fin
• Fin cd
Si:P
• Fin height SiGe
• Fin profile

8 CONFIDENTIAL
IMEC HIGH PERFORMANCE MOBILE LOGIC ROADMAP
Early fdry 2014 2016-2017 2018-2019 2020-2021 2022-2023 2023-...
production N14 (industry ref.) iN10 iN7 iN5 iN3

Finfet
Finfet Finfet
HGAA
Ch-Ge Ch-IIIV
Horizontal nanowire
stacked devices (CFET)

Vdd (V) 0.8 0.8-0.7 0.7-0.6 0.7-0.5 0.6-0.5

Device FinFET FinFET FinFET or HGAA FinFET or HGAA HGAA Vertically integrated
device circuits
Channel nfet/pfet Si / Si Si / Si {SiGe} Si / SiGe Si/ SiGe (Higher mobility)
Gate Pitch (nm) 70-90, 193i 64, 193i 42, 193i 32, EUV TBD
Gate length (nm) 30 24 20 18-14 14-10
Contact metal W W W or Co Alternative metal Alternative metal
Metal Pitch (nm) 52-64, 193i 42, 193i 32, 193i, EUV cut/Via 24, EUV 18, EUV
New functional scaling on top
Low k dielectric 2.55 2.55 2.55-2.4 2.7-2.4 2.7-2.1 of base CMOS:
Mn/Ru + Cu and/or Spintronics, 2D devices,
Metallization TaN/Ta + Cu TaN/Co + Cu TaN/Ru + Cu Alternative metals (Steep-Slope switches)
Co via prefill

iNxx = imec node xx; *h/v GAA = horizontal/vertical Gate-All-Around; CONFIDENTIAL

DEVICE ARCHITECTURE IMPACTS ELECTROSTATICS

Subthreshold Swing (mV/dec)

Ultra-Thin Fin Straight Fin Tapered Fin
120
FinW=5nm FinW=7-8nm FinW=7-10nm
110
Lmin~ 18nm Lmin~ 22-24nm Lmin~ 28nm
100
Gate-All-Around Nanowire 28-32nm
90
Nanowire =7nm Bulk Planar
80 (Vdd ~ 0.9-1.0V)
Lmin~ 15nm
70 FinFETs
60
N5 N7 N10 N14 N22 (Vdd ~ 0.7-0.8V)
10 15 20 25 30
Lg (nm)
 FinFETs offered a Low-Voltage transistor option wrt bulk planar.
 To maintain electrostatics, simple FinFETs will hit limits
10 CONFIDENTIAL
 CMOS LATERAL NANOWIRE DEMONSTRATION
Pfet Nfet

TiN TaN TiAl

LG = 30 nm

HfO2 HfO2

Pfet Nfet

2 stacked Si lateral nanowires CMOS demonstration with RMG CONFIDENTIAL

 STACKED NANOWIRE FET FLOW
Modifications to the Si FinFET flow
(EV-FF):
• Starting material: Si wafer
• Well implantations
• SiGe/Si epitaxy SiGe/Si SL epi and STI formation
• SADP fin patterning
• STI fill
• Dummy gate patterning
• Extension implantations
• Spacer
• Embedded S/D epitaxy
• ILD0 (incl. poly removal)
• Dummy oxide removal
Stacked nanowire fabrication
• Sacrificial layer etch
by SiGe etch in narrow gate trenches
• HK + WF metal
deposition
• Metal gate fill and CMP
• LI1 + LI2 + V0 + BEOL
Stacked nanowire FET process flow is similar as FinFET.
 Critical metrologies: FF + nanowire specific metrologies 12
40
CONFIDENTIAL
NANOWIRE SPECIFIC METROLOGIES
Si/SiGe multi layer defects and Ge diffusion Stacked nanowire diameter and shape &
HK/WFM conformality

CONFIDENTIAL
SCALED HIGH MOBILITY CHANNEL (III-V) GATE-AROUND (GAA)
DEVICES ON SILICON Record InGaAs channel
performances for Vdd=0.5V
Lg ~ 36nm-46nm (NEW)
Wfin ~ 16nm (NEW)
Gmsat > 2000 mS/mm
SS ~ 90-100mV/dec

• Improving III-V GAA Passivation improves performance and scalability

• 300mm-compatible process developed & record performance for InGaAs achieved
CONFIDENTIAL
 DEFECT ENGINEERING FOR III-V ON SILICON

C. Merckling & IIIV Epi Team

• Unique defect trapping Innovation allows for InGaAs to be

integrated in tight geometry in proximity to Si & other materials
 Defect characterization is key for high mobility channel integration in FF and NW.
CONFIDENTIAL
IMEC HIGH PERFORMANCE MOBILE LOGIC ROADMAP
Early fdry 2014 2016-2017 2018-2019 2020-2021 2022-2023 2023-...
production N14 (industry ref.) iN10 iN7 iN5 iN3

Finfet
Finfet Finfet
HGAA
Ch-Ge Ch-IIIV
Horizontal nanowire
stacked devices (CFET)

Vdd (V) 0.8 0.8-0.7 0.7-0.6 0.7-0.5 0.6-0.5

Device FinFET FinFET FinFET or HGAA FinFET or HGAA HGAA Vertically integrated
device circuits
Channel nfet/pfet Si / Si Si / Si {SiGe} Si / SiGe Si/ SiGe (Higher mobility)
Gate Pitch (nm) 70-90, 193i 64, 193i 42, 193i 32, EUV TBD
Gate length (nm) 30 24 20 18-14 14-10
Contact metal W W W or Co Alternative metal Alternative metal
Metal Pitch (nm) 52-64, 193i 42, 193i 32, 193i, EUV cut/Via 24, EUV 18, EUV
New functional scaling on top
Low k dielectric 2.55 2.55 2.55-2.4 2.7-2.4 2.7-2.1 of base CMOS:
Mn/Ru + Cu and/or Spintronics, 2D devices,
Metallization TaN/Ta + Cu TaN/Co + Cu TaN/Ru + Cu Alternative metals (Steep-Slope switches)
Co via prefill

iNxx = imec node xx; *h/v GAA = horizontal/vertical Gate-All-Around; CONFIDENTIAL

 LIMITS TO DENSITY/LGATE SCALING

Physical Dimension (nm)

No Room for
90 Lateral
Contacted Pitch
 Vertical

60

40

10 GAA
FinFET

3 5 7 10 20
CMOS Technology Node (nm)
• Continual gate pitch (density) scaling will be limited by space for Contact & Gate
 Solution necessary for Lgate scaling and contact area scaling
• Eventually disruptive architectures like Vertical NWs can extend density scaling
CONFIDENTIAL
VERTICAL FET PROCESS FLOW

• Nanowire diameter, shape, & profile control

and their metrologies are important in vertical
nanowire FET, which is similar as horizontal
nanowire.
• Vertical nanowire FET specific process control &
metrology: vertical alignment between gate-SD
18 CONFIDENTIAL
IMEC HIGH PERFORMANCE MOBILE LOGIC ROADMAP
Early fdry 2014 2016-2017 2018-2019 2020-2021 2022-2023 2023-...
production N14 (industry ref.) iN10 iN7 iN5 iN3

Finfet
Finfet Finfet
HGAA
Ch-Ge Ch-IIIV
Horizontal nanowire
stacked devices (CFET)

Vdd (V) 0.8 0.8-0.7 0.7-0.6 0.7-0.5 0.6-0.5

Device FinFET FinFET FinFET or HGAA FinFET or HGAA HGAA Vertically integrated
device circuits
Channel nfet/pfet Si / Si Si / Si {SiGe} Si / SiGe Si/ SiGe (Higher mobility)
Gate Pitch (nm) 70-90, 193i 64, 193i 42, 193i 32, EUV TBD
Gate length (nm) 30 24 20 18-14 14-10
Contact metal W W W or Co Alternative metal Alternative metal
Metal Pitch (nm) 52-64, 193i 42, 193i 32, 193i, EUV cut/Via 24, EUV 18, EUV
New functional scaling on top
Low k dielectric 2.55 2.55 2.55-2.4 2.7-2.4 2.7-2.1 of base CMOS:
Mn/Ru + Cu and/or Spintronics, 2D devices,
Metallization TaN/Ta + Cu TaN/Co + Cu TaN/Ru + Cu Alternative metals (Steep-Slope switches)
Co via prefill

iNxx = imec node xx; *h/v GAA = horizontal/vertical Gate-All-Around; CONFIDENTIAL

MOVING TO TUNNEL FET
LOW VOLTAGE APPLICATIONS

20 CONFIDENTIAL
 TFET INTEGRATION
Vertical heterojunction
Planar InGaAs TFET Vertical InGaAs TFET
TFET

SS down to 54mV/dec
by EOT scaling

SS down to 75mV/dec
80 Vd=
0.05V
70
SS (mV/dec)

0.5V
60

50 • Vertical TFET has same challenges as vertical

40 (c) EOT=0.8 nm nanowire FET (NW diameter, shape, profile)
30
-6 -5 -4 -3 -2 • Heterostructure defect control/metrology
10 10 10 10 10
Id (uA/um) 21 is TFET specific challenge. CONFIDENTIAL
 TFET SWING & LEAKAGE DETRACTORS
Lateral (Point) Vs.Vertical (Line) Dit: Interference & Fermi pinning
Tunneling & resultant DOS due to interface defect states
 Eg3 / 2  gate
J BTBT  exp   C 
 F 
 
source p i n drain
 Eg 
  2  ET 
J trap  C2 exp  
 kT  SRH: Thermal Gen. &
  gate
Recomb.
TAT: Trap-Assisted-Tunneling
 Eg 
Phonon-Assisted Tunneling  
J SRH  C1 exp   2 
 kT 
 

Ambipolar
Leakage: Low Eg
TFET performance
limites Vgd dominated by heterostructure and defects.
 Metrology of bulk/interface defects in heterostructure is important. CONFIDENTIAL
ELECTRICAL EVALUATION OF DEFECTS
DLTS Noise

Defect impact evaluated electrically by DTLS and Noise measurement.

23 CONFIDENTIAL
 2-D TRANSITION METAL DICHALCOGENIDES(TMD) CRYSTALS (MX2)

Natural Nanosheets VdW heterostructures (No

lattice mismatch issues?)
Low or free of dangling bonds H. Wang et al, Nanoscale, 2014, 6, 12250
B. Radisavljevic et al., Nature Nanotechnology 2-D Crystals
20Å
Van der Waals

• Interesting properties for ultra-thin body devices

• Especially the Metal-Se2 or Metal-S2: High Band gap &
reasonably high mobility
Wide band gap High DOS &
reasonable
Low-defectivity MoS2
mobility for ultra-thin
molecular doping
channels CONFIDENTIAL
WHY 2D MATERIALS?
MOSFET TFET
VG

High-k 2D’
VD
VS ԦI

2D
Characteristic length of short channel FETs:
𝜖𝑐ℎ 0V
𝜆= 𝑡 . 𝑡𝑜𝑥
𝜖𝑜𝑥 𝑐ℎ
Reduced short channel effects in planar devices

Choice of bandgaps and band alignment

No dangling bonds at interfaces

25 CONFIDENTIAL
2D MATERIAL SYNTHESIS AND METROLOGY
CMOS and TFET require both n-type and p-type semiconductors
Theoretical limit (RT)
MoS2 SnS
MX2 μ (cm2/Vs)
MoS2 340-410
1E-6
1E-7
CVD up to 200mm
CVD up to 200mm
MoSe2 240 1E-8

Id(A/mm)
1E-9

WS2 1,103 1E-10

1E-11

WSe2 705 1E-12

SnS2 306
-30 -15 0 15 30 45 60 75
Vg (V)

HfS2 1,833
WS2 WSe2
HfSe2 3,579
W. Zhang et al, Nano
1E-5

1E-6

Research 2014, 7, 1731 CVD 300mm 1E-7

MBE up to 200mm

Drain Current, Id (A)

1E-8

1E-9

1E-10 Id PG floating
Id Vpg=10
1E-11 Id Vpg=-12
1E-12 Ig_CG

1E-13

1E-14

1E-15

2D material synthesis and bulk/interface metrology are key. -10 -5 0 5

Control Gate Voltage, VCG (V)

10
CONFIDENTIAL
SUMMARY

 CMOS scaling was/is/will be continued by

 CD and pitch scaling,
 Device architecture evolution from 2D to 3D,
 and New materials.

 Metrologies required to characterize parameters, which impact device performance &

yield.
 Smaller CD and pitch,
 High aspect ratio 3D structures
 and New materials.

27 CONFIDENTIAL
CONFIDENTIAL