A 12.

47 kV Medium Voltage Input 350 kW

EV Fast Charger using 10 kV SiC MOSFET
Xinyu Liang, Srdjan Srdic, Jehyuk Won, Erick Aponte, Kristen Booth and Srdjan Lukic
FREEDM Systems Center in Department of Electrical and Computer Engineering
North Carolina State University
Raleigh, North Carolina, USA
xliang5@ncsu.edu, ssrdic@ncsu.edu, jwon2@ncsu.edu, eaponte2@ncsu.edu , kegarcia@ncsu.edu, smlukic@ncsu.edu

Abstract—This paper presents a medium-voltage (MV) based dual active bridge (DAB) modular approach which
(12.47 kV), 350 kW electric vehicle (EV) fast charger using boosts the system switching frequency to 20 kHz. In
10 kV SiC MOSFETs. Detailed system design procedure [2], a higher device utilization multi-cell boost (MCB)
based on the 10 kV SiC MOSFET characterization is
presented to provide a guide on the 10 kV SiC MOSFET based modular topology was selected to build a 50 kW
converter development. Taking the advantage of the 10 MV fast charger using 1.2 kV silicon carbide (SiC)
kV SiC MOSFET’s high voltage blocking capability and MOSFETs which achieved 50 kHz switching frequency
efficient switching performance, a single module high with smaller number of modules and power density
power density system is designed with the DC/DC stage higher than 0.5 kW/L. Though using SiC MOSFETs
operates at 25 kHz and the simulated system efficiency
exceeds 98%, input current THD lower than 2%. With helps improve the system efficiency due to reduced
all the passive components selected, the designed system switching and conduction losses, the limited blocking
power density is 1.6 kW/L. voltage requires the connection of many modules in
Index Terms—component, formatting, style, styling, in- series in order to block the MV input. This modular
sert approach increases the system complexity and highly
affects the reliability of the MV fast charger, due to the
I. I NTRODUCTION
increased component count.
With ever increasing electric vehicle (EV) battery
capacity, high-power chargers are needed to provide In recent years, Wolfspeed has developed and pack-
a gas-station like refueling experience for EVs. Fast aged 10 kV SiC device prototypes and have made
chargers with a 150 kW-350 kW capacity have recently these devices available to researchers. These devices
been introduced to the marketplace as product offerings have substantially lower switching loss and specific on-
[1]. The approach to designing chargers is to supply resistance compared to the Si IGBT of the same voltage
low voltage 3-phase service (480 V in the US) to these level [8]. With the maturity of the device gate drivers
chargers. This approach requires a step down transformer and characterization techniques [9], [10], a number of
and handling of very larger currents on the AC side, prototypes that use these devices have been developed
especially on site supplies multiple 350kW chargers. and demonstrates including 100 kW rating MV ac SST
Recently [2] researchers have proposed connecting EV [11], MV dc SST [12], [13] and impedance measurement
fast charger directly to the MV line, through a solid- unit [14].
state transformer, thus improving system efficiency, and
Based on the published data, five prospective MV
reducing system footprint [3].
rectifier topologies are selected and some of their basic
Though the SST based MV fast charger eliminates the
feasures are summarized and compared in Table I. In
need for a service transformer and provides a significant
this paper, a modification topology of [2] shown in Fig.
reduction in system footprint, the direct connection to
1 is selected to build the standard 12.47 kV voltage level
MV requires high voltage blocking capability of the
input 3 phase 350 kW dc fast charger. The 10 kV device
converters. As a result, many MV fast charger proto-
blocking capability enables direct connection to the 7.2
types use high-voltage IGBTs with the overall switch-
kV line-to-neutral voltage using the topology. In this pa-
ing frequency lower than 10 kHz with bulky passive
per we present a detailed design procedure including the
components and relatively low power density [4]–[6].
semiconductor selection and characterization, operating
Researchers in [7] use more efficient silicon MOSFET
frequency and passive component design as well as the
system efficiency optimization.

978-1-5386-8330-9/19/$31.00 ©2019 IEEE 581

 TABLE I
BASIC M ETRICS S UMMARY AND C OMPARISON FOR C ANDIDATE T OPOLOGIES

Metric CVR MCB Active MCB HB Single Stage ANPC

10 kV MOSFETs 20 18 24 12 18
1.2 kV MOSFETs 0 0 12 12 12
10 kV Diodes 16 12 6 0 0
1.2 kV Diodes 8 12 0 0 0
SiC Semiconductor Devices Total 44 78 78 72 66
Medium Frequency Transformers 2 3 3 6 3
Hard-Switched MOSFETs 16 12 6 0 0
Control Complexity High Medium Medium Medium High

Fig. 1. The topology of MV 350 kW EV fast charger

II. E VALUATION AND C HARACTERIZATION OF 10 K V

S I C MOSFET S
The semiconductors selected for the MV fast charger
prototype are shown in Fig. 1. Each input rectifier diode
consists of three series connected silicon SK Na 47/45
diode from SEMIKRON. A boost type and a buck type
connected 10 kV SiC MOSFET and Schottky Diode are
packaged in XHV-9 module to form a three level boost
(TLB) circuit as the front PFC stage. Three separate
half bridge legs are packaged in a XHV-6 module to
form the primary side of the active NPC (ANPC) based
dual active bridge (DAB) converter. Because of the
high voltage conversion ratio, the RMS current on the
secondary side of the ANPC DAB is very large, so two
CAS325M12HM2 module 1.2 kV SiC MOSFET with
RdsON = 12mΩ are used to form a full bridge on the
secondary side. Fig. 2. (a) Circuit for the double pulse test with parasitic component
Devices were characterized using the double pulse values, (b) DPT setup for the 10 kV SiC MOSFETs characterization
tester (DPT) shown in Fig. 2. The DPT was used to
measure the device switching losses so that passive
component values and operating frequencies could be
determined. The DPT uses P6015A high-voltage passive

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Fig. 3. (a) 10 kV SiC MOSFETs double pulse test waveforms at 15 A conduction current with variable input voltage, (b) 10 kV SiC MOSFETs
double pulse test waveforms at 7 kV input voltage with variable conduction current

probe for the voltage sensing. A 0.1017Ω SSDN-414-

10 shunt resistor with 2 MHz bandwidth is used for
the current sensing after de-skewing with the voltage
probe. As shown in Fig. 2(a), since the device under
test (DUT) is operating at medium voltage, a large air-
core inductor with a large inductance is needed for the
freewheeling. The air core inductor parasitic capacitance
must be as small as possible so as not to introduce
additional discharging current during the turn OFF test.
Based on [15], the Coss of the DUT is around 160 nF.
By separating the multi-layer distance, a 3 mH inductor
with 25 nF stray capacitance was designed and built.

Fig. 5. Switching loss model for the 10 kV SiC MOSFET used in the
PLECS simulation

Fig. 4. 10 kV SiC MOSFET switching energy with respect to different Fig. 6. Die temperature captured by thermal image camera during a
gate resistance, and different current tested at 7 kV, 25◦ C 105◦ C double pulse test

Complete device characterization considering gating

resistance, input voltage and die temperature was per- blue trace is half of the input voltage source measured on
formed using the DPT setup. Fig. 3 shows the experi- one of the two series connected dc-link capacitor. Figure
mental waveform for the 7 kV double pulse test with 4 shows that the switching energy decreases significantly
a gate resistor 5Ω at die temperature 25◦ C, where the as the gate resistance reduces from Rg = 20Ω to
green trace is Vds of the DUT’s lower switch, pink trace Rg = 5Ω. Further gate resistance reduction does not
is the voltage measured on the shunt resistor and the dark lead to major loss reduction, while leading to significant

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voltage overshoot during the switching transient, which must be larger than 10.2 kV. We selected 13.8 kV to
may cause severe EMI issues. As a result, Rg = 5Ω provide enough operating margin for the boost converter.
is chosen as the gate resistance. To develop a loss vs Since each 10 kV device in the NPC configuration
temperature dynamic model of the switching device with only needs to block half of the voltage 6.9 kV, each
given gate resistance, double pulse tests with variable die device operates well within its safe operating area. On
temperature have been conducted. In order to regulate the secondary side of the DAB, the nominal voltage
the die temperature, a die, module and ambient steady should be close to primary side nominal voltage, so
state is reached by heating up the entire module with that RMS current and the reactive power is minimized
hotplate. The double pulse frequency is set to 1 Hz so [18]. With the transformer turn ratio of 8:1, the 850
that the switching and conduction losses don’t provide V secondary side voltage induces 6.8 kV in the pri-
significant transient temperature change. Thus a device mary side of the transformer. The electrolytic capacitor
loss look up table model with respect to Vdd , Id and T 500MXH390MEFCSN30X60 of 390 µF /500 V were
is created and is shown in Fig. 5. Fig. 6 shows the die selected as the dc link capacitors. 16 capacitors are
temperature of the DUT during the testing captured by connected in series to support the full voltage of 6900
a thermal camera. V. Two of the electrolytic capacitors are connected in
parallel to enlarge the overall capacitance which gives a
III. S YSTEM PARAMETER D ESIGN AND PASSIVE
50 µF dc link capacitance. An additional film capacitor
C OMPONENT S ELECTION
bank which consist of 8 parallel 4 series connected
Using the thermal model shown in Fig. 5, we devel- PHE450SD6100JR06L2 capacitors rated at 0.1 µF /2 kV
oped a complete system simulation in PLECS, which gives an overall 1.12 µF decoupling capacitance. The
allowed us to select the device switching frequency and film capacitors 944U470K122AAM of 47 µF /1200V
the values of the passive components. For the control of were used for the secondary side output voltage filtering.
the TLB PFC stage, the predictive current control method 6 capacitors are connected in parallel to enlarge the
described in [16] is implemented so that low THD could output capacitance.
be achieved with relatively small input inductance. For The input inductor and the high frequency transformer
the DAB stage, a traditional triple phase shift (TPS) were custom designed for the specific application. The
control method [17] is implemented to achieve output input inductor was made by using 10 stacked MPP toroid
voltage regulation as well as soft-switching. The system cores 0055868A2 with 120 turns of 10 AWG litz wire.
control scheme is shown in Fig. 7. The designed inductance at 20 A current was around 4
mH. The high frequency transformer was made by using
10 N87 Ferriet U-shape cores with the transfer ratio of
80:10 turns of high voltage side 10 AWG low voltage
side 7 thread twisted 10 AWG litz wire. The transformer
parameters were measured using AP Instruments’ Model
300 Frequency Response Analyzer with a coupling ca-
pacitance 57 pF and leakage inductance 2.5 mH. The
transformer loss was determined experimentally using
the setup and circuit shown in Fig. 8. The single N87
core with 10:10 turn ratio is tested with the secondary
side opened at both 25 kHz and 50 kHz to determine the
magnetic core loss. Fig. 9 shows a testing waveform at
50 kHz 300 V input voltage where the dark blue trace
is the voltage of the primary side of the transformer,
light blue trace is the voltage of the secondary side of
the transformer and the purple trace is the current on
the primary side. The system hardware and component
selection is shown in TABLE. II.
Switching frequency optimization has been done
Fig. 7. per phase system control scheme for 10 kV 350 kW EV fast
charger through the loss model based thermal simulations. Since
the boost PFC stage is hard switching, a lower switching
For the correct operation of the boost converter, the frequency is preferred. However, the switching frequency
DC-link voltage at the output must be larger than the can not be too low since the current ripple increases
peak value of the input waveform. Therefore, for the with the decrease of the switching frequency resulting
rectified 7.2 kV RMS input system, the DC bus voltage a higher switch off current to provide higher switching

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 TABLE II
S YSTEM H ARDWARE AND C OMPONENT S ELECTION R ESULTS

ITEM PART NO. VALUE

Input Diode Heatsink Fischer Elektronik K 5 M8 Rth =5 K/W
10 kV SiC MOSFET Heatsink Fischer Elektronik SK 497 200 Rth =0.55 K/W
1.2 kV SiC MOSFET Heatsink Fischer Elektronik LA 7/150 Rth =0.75 K/W
DC-Link Capacitor 500MXH390MEFCSN30X60 390 µF , 500 V
Decoupling Capacitor PHE450SD6100JR06L2 0.1 µF , 2000 V
Output Capacitor 944U470K122AAM 47 µF , 1200 V
Input Inductor Core 0055868A2 MPP Toroid 026
Transformer Core B67385G0000X187 Ferrite U-shape N87

Fig. 10. boost stage switching frequency optimization shown in

normalized value where heatsink temp base is 70.36◦ C, input current
ripple base is 29 A, input diode loss base is 214 W, input current THD
base is 19% and boost stage loss base is 716 W

Fig. 8. (a) Circuit for the transformer core loss characterization, (b)
Hardware setup for the transformer core loss test, (c) Transformer built
based on the system design using N87 U-shape cores

Fig. 11. dual active bridge stage switching frequency and leakage
inductance optimization results
Fig. 9. Transformer core loss test waveform at 50 kHz, 300V

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 Fig. 12. Detailed system loss breakdown and heatsink temperature of the rated power thermal simulation

losses. Also, low switching frequency results in high

THD which deficit PFC function. Based on electrical and
thermal simulations, the TLB stage switching frequency
was selected to be 10 kHz which is shown in Fig. 10
where a maximum THD and current ripple requirement
is set. High switching frequency helps to reduce the pas-
sive component value which reflects as a lower magnetic
loss in the high frequency transformer. However, higher
switching frequency provides higher switching losses as
well. At the same time, leakage inductance affects the
reactive power which is related to the conduction losses
of the system. The DAB optimization is shown in Fig. Fig. 14. (a) 3D rendering for one phase of the proposed 350 kW
EV fast charger with the proposed design (b) stack design of the
11. Considering the feasibility of the leakage inductance high voltage side dc bus bar and capacitor bank to minimize the loop
in 90 kV level insulation the DAB stage is chosen to inductance
operate at 25 kHz to allow sufficient power transfer,
given the moderate (1.5 mH) leakage inductance. With IV. C ONCLUSION
this operating frequency a primary to secondary side This paper presents the design procedure of a 12.47
phase shift of 50◦ , delivers the target 350 kW. Fig. 12 kV Input 350 kW EV fast charger using 10 kV SiC
shows the detailed simulated loss breakdown, where the MOSFET. The 10 kV SiC MOSFET switching perfor-
system shows 98.1% efficiency at rated power. mance has been characterized through the double pulse
Fig. 13 shows the three phase input inductor current test and loss model of the semiconductor has been
simulation waveform and DAB stage transformer voltage developed for thermal simulations. A simulation based
and current waveform at rated 350 kW power. Fig. system optimization helped determine the correct passive
14 shows the 3D rendering with the designed passive components and switching frequencies and a high fidelity
components, heatsink and semiconductors where a 1.6 thermal simulation based on the experimental validated
kW/L power density is achieved. loss model has shown the system efficiency exceeds
98%.
ACKNOWLEDGMENT
The information, data, or work presented herein was
funded in part by the Office of Energy Efficiency and
Renewable Energy (EERE), U.S. Department of Energy,
under Award Number DE-EE0006521 with North Car-
olina State University, PowerAmerica Institute.
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