www.fairchildsemi.

com

ML4800
Power Factor Correction and PWM Controller
Combo

Features General Description

• Internally synchronized leading-edge PFC and trailing- The ML4800 is a controller for power factor corrected,
edge PWM in one IC switched mode power supplies. Power Factor Correction
• TriFault Detect™ for UL1950 compliance and enhanced (PFC) allows the use of smaller, lower cost bulk capacitors,
safety reduces power line loading and stress on the switching FETs,
• Slew rate enhanced transconductance error amplifier for and results in a power supply that fully complies with
ultra-fast PFC response IEC1000-3-2 specification. Intended as a BiCMOS version
• Low power: 200µA startup current, 5.5mA operating of the industry-standard ML4824, the ML4800 includes
current circuits for the implementation of leading edge, average
• Low total harmonic distortion, high PF current, “boost” type power factor correction and a trailing
• Reduced ripple current in storage capacitor between PFC edge, pulse width modulator (PWM). It also includes a
and PWM sections TriFault Detect™ function to help ensure that no unsafe
• Average current, continuous boost leading edge PFC conditions will result from single component failure in the
• PWM configurable for current-mode or voltage mode PFC. Gate-drivers with 1A capabilities minimize the need
operation for external driver circuits. Low power requirements improve
• Current fed gain modulator for improved noise immunity efficiency and reduce component costs.
• Overvoltage and brown-out protection, UVLO, and soft
start An over-voltage comparator shuts down the PFC section in
the event of a sudden decrease in load. The PFC section also
includes peak current limiting and input voltage brownout
protection. The PWM section can be operated in current or
voltage mode, at up to 250kHz, and includes an accurate
50% duty cycle limit to prevent transformer saturation.

Block Diagram
16 1 13
VEAO IEAO POWER FACTOR CORRECTOR VCC
VCC
TRI-FAULT OVP
VFB VEA 0.5V + 17V VREF
+ 7.5V
15 - 14
1.6kΩ IEA - REFERENCE
2.75V -
2.5V + +
+ S Q
IAC -
2 - -1V +
VRMS GAIN R Q
MODULATOR -
4 PFC OUT
1.6kΩ
ISENSE PFC ILIMIT S Q 12
3

RAMP 1 R Q
7 OSCILLATOR

RAMP 2
DUTY CYCLE
8 LIMIT

-
VDC 1.25V
6 + PWM OUT
VCC S Q
- VIN OK 11

SS 25µA VFB -
+ 1.0V -
R Q
5 2.45V +
+
DC ILIMIT

DC ILIMIT VREF
9 VCC UVLO
PULSE WIDTH MODULATOR

REV. 1.0.5 9/25/01

ML4800 PRODUCT SPECIFICATION

Pin Configuration
ML4800
16-Pin PDIP (P16)
16-Pin Narrow SOIC (S16N)

IEAO 1 16 VEAO

IAC 2 15 VFB

ISENSE 3 14 VREF

VRMS 4 13 VCC

SS 5 12 PFC OUT

VDC 6 11 PWM OUT

RAMP 1 7 10 GND

RAMP 2 8 9 DC ILIMIT
TOP VIEW

Pin Description
Pin Name Function
1 IEAO Slew rate enhanced PFC transconductance error amplifier output
2 IAC PFC AC line reference input to Gain Modulator
3 ISENSE Current sense input to the PFC Gain Modulator
4 VRMS PFC Gain Modulator RMS line voltage compensation input
5 SS Connection point for the PWM soft start capacitor
6 VDC PWM voltage feedback input
7 RAMP 1 Oscillator timing node; timing set by RTCT
8 RAMP 2 When in current mode, this pin functions as the current sense input; when in voltage mode,
it is the PWM modulation ramp input.
9 DC ILIMIT PWM cycle-by-cycle current limit comparator input
10 GND Ground
11 PWM OUT PWM driver output
12 PFC OUT PFC driver output
13 VCC Positive supply
14 VREF Buffered output for the internal 7.5V reference
15 VFB PFC transconductance voltage error amplifier input
16 VEAO PFC transconductance voltage error amplifier output

2 REV. 1.0.5 9/25/01

PRODUCT SPECIFICATION ML4800

Abolute Maximum Ratings

Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum rat-
ings are stress ratings only and functional device operation is not implied.

Parameter Min. Max. Units

VCC 18 V
ISENSE Voltage -5 0.7 V
Voltage on Any Other Pin GND - 0.3 VCCZ + 0.3 V
IREF 10 mA
IAC Input Current 10 mA
Peak PFC OUT Current, Source or Sink 1 A
Peak PWM OUT Current, Source or Sink 1 A
PFC OUT, PWM OUT Energy Per Cycle 1.5 µJ
Junction Temperature 150 °C
Storage Temperature Range -65 150 °C
Lead Temperature (Soldering, 10 sec) 260 °C
Thermal Resistance (θJA)
Plastic DIP 80 °C/W
Plastic SOIC 105 °C/W

Operating Conditions
Temperature Range Min .Max. Units
ML4800CX 0 70 °C
ML4800IX -40 85 °C

Electrical Characteristics
Unless otherwise specified, VCC = 15V, RT = 52.3kΩ, CT = 470pF, TA = Operating Temperature Range (Note 1)

Symbol Parameter Conditions Min. Typ. Max. Units

Voltage Error Amplifier
Input Voltage Range 0 5 V
µΩ
Ω
Transconductance VNON INV = VINV, VEAO = 3.75V 30 65 90
Feedback Reference Voltage 2.43 2.5 2.57 V
Input Bias Current Note 2 -0.5 -1.0 µA
Output High Voltage 6.0 6.7 V
Output Low Voltage 0.1 0.4 V
Source Current VIN = ±0.5V, VOUT = 6V -40 -140 µA
Sink Current VIN = ±0.5V, VOUT = 1.5V 40 140 µA
Open Loop Gain 50 60 dB
Power Supply Rejection Ratio 11V < VCC < 16.5V 50 60 dB
Current Error Amplifier
Input Voltage Range -1.5 2 V
µΩ
Ω
Transconductance VNON INV = VINV, VEAO = 3.75V 50 100 150
Input Offset Voltage 0 4 15 mV

REV. 1.0.5 9/25/01 3

ML4800 PRODUCT SPECIFICATION

Electrical Characteristics (Continued)

Unless otherwise specified, VCC = 15V, RT = 52.3kΩ, CT = 470pF, TA = Operating Temperature Range (Note 1)

Symbol Parameter Conditions Min. Typ. Max. Units

Input Bias Current -0.5 -1.0 µA
Output High Voltage 6.0 6.7 V
Output Low Voltage 0.65 1.0 V
Source Current VIN = ±0.5V, VOUT = 6V -40 -104 µA
Sink Current VIN = ±0.5V, VOUT = 1.5V 40 160 µA
Open Loop Gain 60 70 dB
Power Supply Rejection Ratio 11V < VCC < 16.5V 60 75 dB
OVP Comparator
Threshold Voltage 2.65 2.75 2.85 V
Hysteresis 175 250 325 mV
Tri-Fault Detect
Fault Detect HIGH 2.65 2.75 2.85 V
Time to Fault Detect HIGH VFB = VFAULT DETECT LOW to 2 4 ms
VFB = OPEN. 470pF from VFB to
GND
Fault Detect LOW 0.4 0.5 0.6 V
PFC ILIMIT Comparator
Threshold Voltage -0.9 -1.0 -1.1 V
(PFC ILIMIT VTH - Gain 120 220 mV
Modulator Output)
Delay to Output 150 300 ns
DC ILIMIT Comparator
Threshold Voltage 0.95 1.0 1.05 V
Input Bias Current ±0.3 ±1 µA
Delay to Output 150 300 ns
VIN OK Comparator
Threshold Voltage 2.35 2.45 2.55 V
Hysteresis 0.8 1.0 1.2 V
GAIN Modulator
Gain (Note 3) IAC = 100µA, VRMS = VFB = 0V 0.60 0.80 1.05
IAC = 50µA, VRMS = 1.2V, VFB = 0V 1.8 2.0 2.40
IAC = 50µA, VRMS = 1.8V, VFB = 0V 0.85 1.0 1.25
IAC = 100µA, VRMS = 3.3V, VFB = 0V 0.20 0.30 0.40
Bandwidth IAC = 100µA 10 MHz
Output Voltage IAC = 350µA, VRMS = 1V, VFB = 0V 0.60 0.75 0.9 V
Oscillator
Initial Accuracy TA = 25°C 71 76 81 kHz
Voltage Stability 11V < VCC < 16.5V 1 %
Temperature Stability 2 %
Total Variation Line, Temp 68 84 kHz
Ramp Valley to Peak Voltage 2.5 V

4 REV. 1.0.5 9/25/01

PRODUCT SPECIFICATION ML4800

Electrical Characteristics (Continued)

Unless otherwise specified, VCC = 15V, RT = 52.3kΩ, CT = 470pF, TA = Operating Temperature Range (Note 1)

Symbol Parameter Conditions Min. Typ. Max. Units

PFC Dead Time 350 650 ns
CT Discharge Current VRAMP 2 = 0V, VRAMP 1 = 2.5V 3.5 5.5 7.5 mA
Reference
Output Voltage TA = 25°C, I(VREF) = 1mA 7.4 7.5 7.6 V
Line Regulation 11V <VCC <16.5V 10 25 mV
Load Regulation 0mA <I(VREF) < 10mA; 10 20 mV
TA = 0°C to 70°C
0mA < I(VREF) < 5mA; 10 20 mV
TA = –40°C to 85°C
Temperature Stability 0.4 %
Total Variation Line, Load, Temp 7.35 7.65 V
Long Term Stability TJ = 125°C, 1000 Hours 5 25 mV
PFC
Minimum Duty Cycle VIEAO > 4.0V 0 %
Maximum Duty Cycle VIEAO < 1.2V 90 95 %
Output Low Voltage IOUT = -20mA 0.4 0.8 V
IOUT = -100mA 0.7 2.0 V
IOUT = 10mA, VCC = 9V 0.4 0.8 V
Output High Voltage IOUT = 20mA VCC - 0.8V V
IOUT = 100mA VCC - 2V V
Rise/Fall Time CL = 1000pF 50 ns
PWM
Duty Cycle Range 0-44 0-47 0-49 %
Output Low Voltage IOUT = -20mA 0.4 0.8 V
IOUT = -100mA 0.7 2.0 V
IOUT = 10mA, VCC = 9V 0.4 0.8 V
Output High Voltage IOUT = 20mA VCC - 0.8V V
IOUT = 100mA VCC - 2V V
Rise/Fall Time CL = 1000pF 50 ns
Supply
Start-up Current VCC = 12V, CL = 0 200 350 µA
Operating Current 14V, CL = 0 5.5 7 mA
Undervoltage Lockout 12.4 13 13.6 V
Threshold
Undervoltage Lockout 2.5 2.8 3.1 V
Hysteresis
Notes
1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
2. Includes all bias currents to other circuits connected to the VFB pin.
3. Gain = K x 5.3V; K = (IGAINMOD - IOFFSET) x [IAC (VEAO - 0.625)]-1; VEAOMAX=5V.

REV. 1.0.5 9/25/01 5

ML4800 PRODUCT SPECIFICATION

Typical Performance Characteristics

180

160

TRANSCONDUCTANCE (µ )
140

Ω
120

100

80

60

40

20

0
0 1 2 3 4 5
VFB (V)

Voltage Error Amplifier (VEA) Transconductance (gm)

180 480
VARIABLE GAIN BLOCK CONSTANT (K)

160 420
TRANSCONDUCTANCE (µ )

140
Ω

360
120
300
100
240
80
180
60
120
40

20 60

0 0
–500 0 500 0 1 2 3 4 5

IEA INPUT VOLTAGE (mV) VRMS(V)

Current Error Amplifier (IEA) Transconductance (gm) Gain Modulator Transfer Characteristic (K)

( I GAINMOD – 84µA ) –1
K = ----------------------------------------------------- mV
IAC × ( 5 – 0.625 )

6 REV. 1.0.5 9/25/01

PRODUCT SPECIFICATION ML4800

Functional Description line voltage. One of these conditions is that the output volt-
age of the boost converter must be set higher than the peak
The ML4800 consists of an average current controlled, value of the line voltage. A commonly used value is
continuous boost Power Factor Corrector (PFC) front end 385VDC, to allow for a high line of 270VACrms. The other
and a synchronized Pulse Width Modulator (PWM) back condition is that the current drawn from the line at any given
end. The PWM can be used in either current or voltage instant must be proportional to the line voltage. Establishing
mode. In voltage mode, feedforward from the PFC output a suitable voltage control loop for the converter, which in
buss can be used to improve the PWM’s line regulation. turn drives a current error amplifier and switching output
In either mode, the PWM stage uses conventional trailing- driver satisfies the first of these requirements. The second
edge duty cycle modulation, while the PFC uses leading- requirement is met by using the rectified AC line voltage to
edge modulation. This patented leading/trailing edge modu- modulate the output of the voltage control loop. Such
lation technique results in a higher usable PFC error ampli- modulation causes the current error amplifier to command a
fier bandwidth, and can significantly reduce the size of the power stage current that varies directly with the input
PFC DC buss capacitor. voltage. In order to prevent ripple, which will necessarily
appear at the output of the boost circuit (typically about
The synchronization of the PWM with the PFC simplifies the 10VAC on a 385V DC level), from introducing distortion
PWM compensation due to the controlled ripple on the PFC back through the voltage error amplifier, the bandwidth of
output capacitor (the PWM input capacitor). The PWM sec- the voltage loop is deliberately kept low. A final refinement
tion of the ML4800 runs at the same frequency as the PFC. is to adjust the overall gain of the PFC such to be propor-
tional to 1/VIN2, which linearizes the transfer function of the
In addition to power factor correction, a number of protec- system as the AC input voltage varies.
tion features have been built into the ML4800. These include
soft-start, PFC overvoltage protection, peak current limiting, Since the boost converter topology in the ML4800 PFC is of
brownout protection, duty cycle limiting, and under-voltage the current-averaging type, no slope compensation is
lockout. required.

Power Factor Correction PFC Section

Power factor correction makes a nonlinear load look like a
resistive load to the AC line. For a resistor, the current drawn Gain Modulator
from the line is in phase with and proportional to the line Figure 1 shows a block diagram of the PFC section of the
voltage, so the power factor is unity (one). A common class ML4800. The gain modulator is the heart of the PFC, as it is
of nonlinear load is the input of most power supplies, which this circuit block which controls the response of the current
use a bridge rectifier and capacitive input filter fed from the loop to line voltage waveform and frequency, rms line volt-
line. The peak-charging effect, which occurs on the input fil- age, and PFC output voltage. There are three inputs to the
ter capacitor in these supplies, causes brief high-amplitude gain modulator. These are:
pulses of current to flow from the power line, rather than a
sinusoidal current inphase with the line voltage. Such sup- 1. A current representing the instantaneous input voltage
plies present a power factor to the line of less than one (i.e. (amplitude and waveshape) to the PFC. The rectified
they cause significant current harmonics of the power line AC input sine wave is converted to a proportional
frequency to appear at their input). If the input current drawn current via a resistor and is then fed into the gain
by such a supply (or any other nonlinear load) can be made modulator at IAC. Sampling current in this way
to follow the input voltage in instantaneous amplitude, it will minimizes ground noise, as is required in high power
appear resistive to the AC line and a unity power factor will switching power conversion environments. The gain
be achieved. modulator responds linearly to this current.

To hold the input current draw of a device drawing power 2. A voltage proportional to the long-term RMS AC line
from the AC line in phase with and proportional to the input voltage, derived from the rectified line voltage after
voltage, a way must be found to prevent that device from scaling and filtering. This signal is presented to the gain
loading the line except in proportion to the instantaneous line modulator at VRMS. The gain modulator s output is
voltage. The PFC section of the ML4800 uses a boost-mode inversely proportional to VRMS2 (except at unusually
DC-DC converter to accomplish this. The input to the con- low values of VRMS where special gain contouring takes
verter is the full wave rectified AC line voltage. No bulk fil- over, to limit power dissipation of the circuit
tering is applied following the bridge rectifier, so the input components under heavy brownout conditions). The
voltage to the boost converter ranges (at twice line fre- relationship between VRMS and gain is called K, and is
quency) from zero volts to the peak value of the AC input illustrated in the Typical Performance Characteristics.
and back to zero. By forcing the boost converter to meet two
simultaneous conditions, it is possible to ensure that the cur- 3. The output of the voltage error amplifier, VEAO. The
gain modulator responds linearly to variations in this
rent drawn from the power line is proportional to the input
voltage.

REV. 1.0.5 9/25/01 7

ML4800 PRODUCT SPECIFICATION

The output of the gain modulator is a current signal, in the cycle until the voltage on ISENSE is adequately negative to
form of a full wave rectified sinusoid at twice the line fre- cancel this increased current. Similarly, if the gain modula-
quency. This current is applied to the virtual-ground (nega- tor’s output decreases, the output duty cycle will decrease, to
tive) input of the current error amplifier. In this way the gain achieve a less negative voltage on the ISENSE pin.
modulator forms the reference for the current error loop, and
ultimately controls the instantaneous current draw of the Cycle-By-Cycle Current Limiter
PFC from the power line. The general form for the output of The ISENSE pin, as well as being a part of the current feed-
the gain modulator is: back loop, is a direct input to the cycle-by-cycle current
limiter for the PFC section. Should the input voltage at this
I AC × VEAO pin ever be more negative than -1V, the output of the PFC
I GAINMOD = −−−−−−−−−−−−−−2−−−−− × 1V (1)
V RMS will be disabled until the protection flip-flop is reset by the
clock pulse at the start of the next PFC power cycle.
More exactly, the output current of the gain modulator is
TriFault DetectTM
given by:
To improve power supply reliability, reduce system compo-
I GAINMOD = K × ( VEAO – 0.625V ) × I AC nent count, and simplify compliance to UL 1950 safety
standards, the ML4800 includes TriFault Detect. This feature
monitors VFB (Pin 15) for certain PFC fault conditions.
where K is in units of V-1.
In the case of a feedback path failure, the output of the PFC
Note that the output current of the gain modulator is limited could go out of safe operating limits. With such a failure,
to 500µA. VFB will go outside of its normal operating area. Should
VFB go too low, too high, or open, TriFault Detect senses the
Current Error Amplier
error and terminates the PFC output drive.
The current error amplifier’s output controls the PFC duty
cycle to keep the average current through the boost inductor TriFault detect is an entirely internal circuit. It requires no
a linear function of the line voltage. At the inverting input to external components to serve its protective function.
the current error amplifier, the output current of the gain
modulator is summed with a current which results from a Overvoltage Protection
negative voltage being impressed upon the ISENSE pin. The The OVP comparator serves to protect the power circuit
negative voltage on ISENSE represents the sum of all currents from being subjected to excessive voltages if the load should
flowing in the PFC circuit, and is typically derived from a suddenly change. A resistor divider from the high voltage
current sense resistor in series with the negative terminal of DC output of the PFC is fed to VFB. When the voltage on
the input bridge rectifier. In higher power applications, two VFB exceeds 2.75V, the PFC output driver is shut down.
current transformers are sometimes used, one to monitor the The PWM section will continue to operate. The OVP
ID of the boost MOSFET(s) and one to monitor the IF of the comparator has 250mV of hysteresis, and the PFC will not
boost diode. As stated above, the inverting input of the cur- restart until the voltage at VFB drops below 2.50V. The VFB
rent error amplifier is a virtual ground. Given this fact, and should be set at a level where the active and passive external
the arrangement of the duty cycle modulator polarities inter- power components and the ML4800 are within their safe
nal to the PFC, an increase in positive current from the gain operating voltages, but not so low as to interfere with the
modulator will cause the output stage to increase its duty boost voltage regulation loop.

16 1
VEAO IEAO
OVP
TRI-FAULT
VFB VEA 0.5V + +
15 – IEA
1.6kΩ – 2.75V –
2.5V +
+ +
IAC – S Q
–
2
GAIN –1V +
VRMS R Q
MODULATOR –
4 PFC OUT
1.6kΩ
ISENSE PFC ILIMIT S Q 12
3

RAMP 1 R Q
7 OSCILLATOR

Figure 1. PFC Section Block Diagram

8 REV. 1.0.5 9/25/01

PRODUCT SPECIFICATION ML4800

Error Amplier Compensation significantly, as shown in the Typical Performance Charac-

The PWM loading of the PFC can be modeled as a negative teristics. This raises the gain-bandwidth product of the
resistor; an increase in input voltage to the PWM causes a voltage loop, resulting in a much more rapid voltage loop
decrease in the input current. This response dictates the response to such perturbations than would occur with a
proper compensation of the two transconductance error conventional linear gain characteristic.
amplifiers. Figure 2 shows the types of compensation
networks most commonly used for the voltage and current The current amplifier compensation is similar to that of the
error amplifiers, along with their respective return points. voltage error amplifier with the exception of the choice of
The current loop compensation is returned to VREF to crossover frequency. The crossover frequency of the current
produce a soft-start characteristic on the PFC: as the amplifier should be at least 10 times that of the voltage
reference voltage comes up from zero volts, it creates a amplifier, to prevent interaction with the voltage loop.
differentiated voltage on IEAO which prevents the PFC It should also be limited to less than 1/6th that of the
from immediately demanding a full duty cycle on its boost switching frequency, e.g. 16.7kHz for a 100kHz switching
converter. frequency.

There are two major concerns when compensating the There is a modest degree of gain contouring applied to the
voltage loop error amplifier; stability and transient response. transfer characteristic of the current error amplifier, to
Optimizing interaction between transient response and increase its speed of response to current-loop perturbations.
stability requires that the error amplifier’s open-loop cross- However, the boost inductor will usually be the dominant
over frequency should be 1/2 that of the line frequency, or factor in overall current loop response. Therefore, this
23Hz for a 47Hz line (lowest anticipated international power contouring is significantly less marked than that of the
frequency). The gain vs. input voltage of the ML4800’s voltage error amplifier. This is illustrated in the Typical
voltage error amplifier has a specially shaped non-linearity Performance Characteristics.
such that under steady-state operating conditions the
transconductance of the error amplifier is at a local For more information on compensating the current and
minimum. Rapid perturbations in line or load conditions voltage control loops, see Application Notes 33 and 34.
will cause the input to the voltage error amplifier (VFB) to Application Note 16 also contains valuable information for
deviate from its 2.5V (nominal) value. If this happens, the the design of this class of PFC.
transconductance of the voltage error amplifier will increase

VREF

VBIAS

RBIAS
PFC
OUTPUT
16 1
VEAO IEAO VCC 0.22µF
CERAMIC 15V
VFB VEA ML4800 ZENER
15 – IEA
+
2.5V + + GND
–
IAC –
2
VRMS GAIN
MODULATOR
4
ISENSE
3

Figure 2. Compensation Network Connections for the Figure 3. External Component Connections to VCC
Voltage and Current Error Amplifiers

REV. 1.0.5 9/25/01 9

ML4800 PRODUCT SPECIFICATION

Oscillator (RAMP 1) output stage, and is thereby representative of the current

The oscillator frequency is determined by the values of RT flowing in the converter’s output stage. DC ILIMIT, which
and CT, which determine the ramp and off-time of the provides cycle-by-cycle current limiting, is typically con-
oscillator output clock: nected to RAMP 2 in such applications. For voltage-mode
operation or certain specialized applications, RAMP 2 can
1 be connected to a separate RC timing network to generate a
f OSC = ---------------------------------------------------- (2) voltage ramp against which VDC will be compared. Under
t RAMP + t DEADTIME
these conditions, the use of voltage feedforward from the
PFC buss can assist in line regulation accuracy and response.
The dead time of the oscillator is derived from the following As in current mode operation, the DC ILIMIT input is used
equation: for output stage overcurrent protection.
V REF – 1.25
t RAMP = C T × R T × In ------------------------------ (3) No voltage error amplifier is included in the PWM stage of
V REF – 3.75
the ML4800, as this function is generally performed on the
output side of the PWM’s isolation boundary. To facilitate
at VREF = 7.5V: the design of optocoupler feedback circuitry, an offset has
been built into the PWM’s RAMP 2 input which allows VDC
t RAMP = C T × R T × 0.51 to command a zero percent duty cycle for input voltages
below 1.25V.
The dead time of the oscillator may be determined using:
PWM Current Limit
2.5V
t DEADTIME = ----------------- × C T = 450 × C T (4) The DC ILIMIT pin is a direct input to the cycle-by-cycle
5.5mA
current limiter for the PWM section. Should the input
The dead time is so small (tRAMP >> tDEADTIME) that the voltage at this pin ever exceed 1V, the output of the PWM
operating frequency can typically be approximated by: will be disabled until the output flip-flop is reset by the clock
pulse at the start of the next PWM power cycle.
1
f OSC = ---------------- (5)
t RAMP VIN OK Comparator
The VIN OK comparator monitors the DC output of the PFC
EXAMPLE: and inhibits the PWM if this voltage on VFB is less than its
For the application circuit shown in the data sheet, with the nominal 2.45V. Once this voltage reaches 2.45V, which
oscillator running at: corresponds to the PFC output capacitor being charged to its
rated boost voltage, the soft-start begins.
1
f OSC = 100kHz = ----------------
t RAMP PWM Control (RAMP 2)
When the PWM section is used in current mode, RAMP 2
Solving for RT x CT yields 1.96 x 10-4. Selecting standard is generally used as the sampling point for a voltage
components values, CT = 390pF, and RT = 51.1kΩ. representing the current in the primary of the PWM’s output
transformer, derived either by a current sensing resistor or a
The dead time of the oscillator adds to the Maximum PWM current transformer. In voltage mode, it is the input for a
Duty Cycle (it is an input to the Duty Cycle Limiter). With ramp voltage generated by a second set of timing compo-
zero oscillator dead time, the Maximum PWM Duty Cycle is nents (RRAMP2, CRAMP2), that will have a minimum value of
typically 45%. In many applications, care should be taken zero volts and should have a peak value of approximately 5V.
that CT not be made so large as to extend the Maximum Duty In voltage mode operation, feedforward from the PFC output
Cycle beyond 50%. This can be accomplished by using a buss is an excellent way to derive the timing ramp for the
stable 390pF capacitor for CT. PWM stage.

PWM SECTION Soft Start

Start-up of the PWM is controlled by the selection of the
Pulse Width Modulator
external capacitor at SS. A current source of 25µA supplies
The PWM section of the ML4800 is straightforward, but the charging current for the capacitor, and start-up of the
there are several points which should be noted. Foremost PWM begins at 1.25V. Start-up delay can be programmed by
among these is its inherent synchronization to the PFC the following equation:
section of the device, from which it also derives its basic
timing. The PWM is capable of current-mode or voltage
25µA
mode operation. In current-mode applications, the PWM C SS = t DELAY × --------------- (6)
ramp (RAMP 2) is usually derived directly from a current 1.25V
sensing resistor or current transformer in the primary of the

10 REV. 1.0.5 9/25/01

PRODUCT SPECIFICATION ML4800

where CSS is the required soft start capacitance, and tDELAY function, it is important to limit the current through the
is the desired start-up delay. Zener to avoid overheating or destroying it. This can be
easily done with a single resistor in series with the Vcc pin,
It is important that the time constant of the PWM soft-start returned to a bias supply of typically 18V to 20V. The
allow the PFC time to generate sufficient output power for resistor’s value must be chosen to meet the operating current
the PWM section. The PWM start-up delay should be at least requirement of the ML4800 itself (8.5mA, max.) plus the
5ms. current required by the two gate driver outputs.

Solving for the minimum value of CSS: EXAMPLE:

With a VBIAS of 20V, a VCC of 15V and the ML4800 driving
25µA
Css = 5ms × --------------- = 100nF (6a) a total gate charge of 90nC at 100kHz (e.g., 1 IRF840
1.25V MOSFET and 2 IRF820 MOSFETs), the gate driver current
required is:
Caution should be exercised when using this minimum soft
start capacitance value because premature charging of the SS I GATEDRIVE = 100kHz × 90nC = 9mA (7)
capacitor and activation of the PWM section can result if
VFB is in the hysteresis band of the VIN OK comparator at V BIAS – V CC
start-up. The magnitude of VFB at start-up is related both to R BIAS = --------------------------------- (8)
I CC + I G + I Z
line voltage and nominal PFC output voltage. Typically, a
1.0µF soft start capacitor will allow time for V FB and PFC 20V – 15V
R BIAS = -------------------------------------------------- = 250Ω
out to reach their nominal values prior to activation of the 6mA + 9mA + 5mA
PWM section at line voltages between 90Vrms and
265Vrms.
Choose RBIAS = 240Ω.
Generating VCC
The ML4800 should be locally bypassed with a 1.0µF
The ML4800 is a voltage-fed part. It requires an external ceramic capacitor. In most applications, an electrolytic
15V, ±10% (or better) shunt voltage regulator, or some other capacitor of between 47µF and 220µF is also required across
VCC regulator, to regulate the voltage supplied to the part at the part, both for filtering and as part of the start-up bootstrap
15V nominal. This allows low power dissipation while at the circuitry.
same time delivering 13V nominal gate drive at the PWM
OUT and PFC OUT outputs. If using a Zener diode for this

L1 SW2 I2 I3

I1
+ I4
VIN

DC SW1 RL

C1
RAMP

VEAO
REF U3
+
–EA
DFF TIME
+ VSW1
RAMP – R Q
OSC U1 D U2
CLK
Q
U4 CLK

TIME

Figure 4. Typical Trailing Edge Control Scheme

REV. 1.0.5 9/25/01 11

ML4800 PRODUCT SPECIFICATION

Leading/Trailing Modulation One of the advantages of this control technique is that it

requires only one system clock. Switch 1 (SW1) turns off
Conventional Pulse Width Modulation (PWM) techniques and switch 2 (SW2) turns on at the same instant to minimize
employ trailing edge modulation in which the switch will the momentary “no-load” period, thus lowering ripple volt-
turn on right after the trailing edge of the system clock. The age generated by the switching action. With such synchro-
error amplifier output voltage is then compared with the nized switching, the ripple voltage of the first stage is
modulating ramp. When the modulating ramp reaches the reduced. Calculation and evaluation have shown that the
level of the error amplifier output voltage, the switch will be 120Hz component of the PFC’s output ripple voltage can be
turned OFF. When the switch is ON, the inductor current will reduced by as much as 30% using this method.
ramp up. The effective duty cycle of the trailing edge modu-
lation is determined during the ON time of the switch. Figure
4 shows a typical trailing edge control scheme. Typical Applications
Figure 6 is the application circuit for a complete 100W
In the case of leading edge modulation, the switch is turned power factor corrected power supply, designed using the
OFF right at the leading edge of the system clock. When the methods and general topology detailed in Application Note
modulating ramp reaches the level of the error amplifier out- 33.
put voltage, the switch will be turned ON. The effective
duty-cycle of the leading edge modulation is determined dur-
ing the OFF time of the switch. Figure 5 shows a leading
edge control scheme.

L1 SW2 I2 I3

I1
+ I4
VIN

DC SW1 RL

C1
RAMP

VEAO

U3
+
EA
–
REF VEAO TIME
DFF
CMP
+ VSW1
RAMP – R Q
OSC U1 D U2
CLK
Q
U4 CLK

TIME

Figure 5. Typical Leading Edge Control Scheme

12 REV. 1.0.5 9/25/01

 D1 D12
8A
F1 L1 FES16JT VBUSS
3.15A
BR1 Q1G C5
C1 4A, 600V Q2G Q2
IRF840A 100µF R19
AC INPUT 0.47µF KBL06 IRF820A T2C
R27 33Ω
85 TO 260V 82kΩ Q1 R13
R1 C4
IRF840A 4.7nF 383kΩ C25 R24
357kΩ
R20 0.1µF

REV. 1.0.5 9/25/01

10kΩ
22Ω D5
R9 600V
249kΩ T1B
ISENSE R14 D7 12V
383kΩ 16V
PRODUCT SPECIFICATION

R2 R28 D11A L2 L3
357kΩ 240Ω
C26 12V, 100W
47µF MBR2545CT
R8 D2
R7 C12
1.2Ω 15V Q3G
R6 1.2Ω 10µF R18 C24 C21 C32 C30
R5 1N4744A D11B
1.2Ω 35V 33Ω IRF820A 0.47µF 1500µF 0.47µF 1000µF
1.2Ω
Q3 D6
C3 C20 600V
R3 R10
0.22µF 100kΩ 249kΩ 0.47µF

PWM R34
R17 R29
ILIMIT 240Ω
R38 3Ω 1.2kΩ
42.2kΩ R21 R22
2.2Ω 2.2Ω

R16 10kΩ T1A R32

C22
R23 R30 8.66kΩ
10µF
C2 R4 C7 150pF 220Ω 1.5kΩ
R37 1kΩ
0.47µF 13.2kΩ
R39 2N3904
R12 68.1k C6 1.5nF Q4
33Ω
D4 MOC8112
5.1V U2
R25
ML4800
10kΩ R44
1 16 1N4733A
IEAO VDC 10kΩ
U1 VFB
2 15 VCC REF
IAC VFB
3 14 R40
ISENSE VREF R11 R26 470Ω
4 13 412kΩ 10kΩ
VRMS VCC
5 12
RT/CT SS PFC OUT R31
6 11 J8 10kΩ
VDC PWM OUT
C15 C13 C8 C9
7 10 1.0µF 0.22µF 150µF 15nF C10
RAMP1 GND C31
D8 D10 10µF
8 9 330pF
D14 RAMP 2 DC ILMIT C23
1N914 10nF
R15
4.99kΩ VDC
C19 C18
D13 1.0µF 470pF U3
1N914 TL431A
R33 12V RET
C11 C28 2.26kΩ
D15 220pF 220pF
1N914 PRI GND 12V
RETURN

NOTE: D7, D8, D10; 1N966B

D3, D5, D6, D12; UF4005
D4; 1N4733A
D2; 1N4744A
D11; MBR2545CT
L1; PREMIER MAGNETICS TSD-1047
L2; PREMIER MAGNETICS VTP-05007

Figure 6. 100W Power Factor Corrected Power Supply, Designed Using Micro Linear Application Note 33
L3; PREMIER MAGNETICS TSD-904
T1; PREMIER MAGNETICS PMGD-03
T2; PREMIER MAGNETICS TSD-735
UNUSED DESIGNATORS; C14, C16, C17, C27, C29, C33, D3, D9, R42, R43, R36, R35
ML4800

13
ML4800 PRODUCT SPECIFICATION

Ordering Information
Part Number Temperature Range Package
ML4800CP 0°C to 70°C 16-Pin PDIP (P16)
ML4800CS 0°C to 70°C 16-Pin Narrow SOIC (S16N)
ML4800IP -40°C to 85°C 16-Pin PDIP (P16)
ML4800IS -40°C to 85°C 16-Pin Narrow SOIC (S16N)

DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:

1. Life support devices or systems are devices or systems 2. A critical component is any component of a life support
which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be
or (b) support or sustain life, or (c) whose failure to perform reasonably expected to cause the failure of the life support
when properly used in accordance with instructions for use device or system, or to affect its safety or effectiveness.
provided in the labeling, can be reasonably expected to
result in significant injury of the user.

www.fairchildsemi.com
9/25/01 0.0m 001
Stock#DS30004800
 2001 Fairchild Semiconductor Corporation