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Question Paper Code:: Sri Vidya College of Engineering & Technology, Virudhunagar

This document is a question paper for a Computer Science and Engineering exam from Sri Vidya College of Engineering & Technology in Virudhunagar, India. It contains 15 questions in two parts - Part A contains 10 short answer questions worth 2 marks each (total 20 marks), and Part B contains 5 long answer questions worth 16 marks each (total 80 marks). The questions cover topics related to computer organization and architecture, including instruction types, adder designs, control unit organization, pipelining hazards, caching, I/O interfacing, and parallel ports.

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85 views2 pages

Question Paper Code:: Sri Vidya College of Engineering & Technology, Virudhunagar

This document is a question paper for a Computer Science and Engineering exam from Sri Vidya College of Engineering & Technology in Virudhunagar, India. It contains 15 questions in two parts - Part A contains 10 short answer questions worth 2 marks each (total 20 marks), and Part B contains 5 long answer questions worth 16 marks each (total 80 marks). The questions cover topics related to computer organization and architecture, including instruction types, adder designs, control unit organization, pipelining hazards, caching, I/O interfacing, and parallel ports.

Uploaded by

rajesh5500
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Sri Vidya College of Engineering & Technology, Virudhunagar Course Material (University Question)

Question Paper Code : 11257

B.E./B.Tech. DEGREE EXAMINATION, APRIL/MAY 2011

Fourth Semester

Computer Science and Engineering

CS 2253 - COMPUTER ORGANIZATION AND ARCHITECTURE

(Common to Information Technology)

(Regulation 2008)

Time: Three hours Maximum: 100 marks

Answer ALL questions

PART A - (10 x 2 = 20 marks)

1. What is an opcode? How many bits are needed to specify 32 distinct


operations?

2. Write the logic equations of a binary half adder.

3. Write the difference between Horizontal and Vertical Microinstructions.

4. In what ways the width and height of the control memory can be reduced?

5. A=5 A 3+A

B 4xA
What hazard does the above two instructions createwhen executed
concurrently?

6. What are the disadvantages of increasing the number of stages in pipelined processing?

7. What is the use of EEPROM?

8. State the hardware needed to implement the LRU in replacement algorithm.

9. What is distributed arbitration?

10. How interrupt requests from multiple devices can be handled?

CS8491 – COMPUTER ARCHITECTURE Page 1

STUDENTSFOCUS.COM
Sri Vidya College of Engineering & Technology, Virudhunagar Course Material (University Question)

PART B - (5 x 16 = 80 marks)

11. (a) With examples explain the Data transfer, Logic and Program Control
Instructions? (16)

Or
(b) Explain the Working of a Carry-Look Ahead adder. (16)

12. (a) (i) Describe the control unit organization with a separate Encoder and
Decoder functions in a hardwired control. (8)
(ii) Generate the logic circuit for the following functions and explain. (8)

Or
(b)Write a brief note on nano programming. (16)

13. (a) What are the hazards of conditional branches in pipelines? how it can be
resolved? (16)

Or
(b) Explain the super scalar operations with a neat diagram. (16)

14. (a) What is a mapping function? What are the ways the cache can be
mapped? (16)

Or
(b) Explain the organization and accessing of data on a Disk. (16)

15. (a) (i) How data transfers can be controlled using handshaking technique?
(8)
(ii) Explain the protocols of USB. (8)

Or
(b) How the parallel port output interface circuit works? (16)

CS8491 – COMPUTER ARCHITECTURE Page 2

STUDENTSFOCUS.COM

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