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    1916eid 203

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    Vamshidhar Reddy
    This document is a past exam paper for the third semester B.Tech. degree examination in Computer Organization and Architecture. It covers 5 modules, with 2 questions provided for each module. The questions assess a range of topics related to computer organization and architecture, including shifter and adder/subtractor circuit design, instruction cycles, pipelining, multiplication algorithms, memory addressing, cache memory design, memory hierarchies, and interrupt handling. Students must answer one question from each module, with each part of the selected questions answered together.

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    1916eid 203

    Uploaded by

    Vamshidhar Reddy
    28 views2 pages
    This document is a past exam paper for the third semester B.Tech. degree examination in Computer Organization and Architecture. It covers 5 modules, with 2 questions provided for each module. The questions assess a range of topics related to computer organization and architecture, including shifter and adder/subtractor circuit design, instruction cycles, pipelining, multiplication algorithms, memory addressing, cache memory design, memory hierarchies, and interrupt handling. Students must answer one question from each module, with each part of the selected questions answered together.

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    1916EID-203

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    This document is a past exam paper for the third semester B.Tech. degree examination in Computer Organization and Architecture. It covers 5 modules, with 2 questions provided for each module. The questions assess a range of topics related to computer organization and architecture, including shifter and adder/subtractor circuit design, instruction cycles, pipelining, multiplication algorithms, memory addressing, cache memory design, memory hierarchies, and interrupt handling. Students must answer one question from each module, with each part of the selected questions answered together.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    28 views2 pages

    1916eid 203

    Uploaded by

    Vamshidhar Reddy
    This document is a past exam paper for the third semester B.Tech. degree examination in Computer Organization and Architecture. It covers 5 modules, with 2 questions provided for each module. The questions assess a range of topics related to computer organization and architecture, including shifter and adder/subtractor circuit design, instruction cycles, pipelining, multiplication algorithms, memory addressing, cache memory design, memory hierarchies, and interrupt handling. Students must answer one question from each module, with each part of the selected questions answered together.

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    [Oct-17]

    [EID-203]
    B.Tech. Degree Examination
    CSE & IT
    III SEMESTER
    COMPUTER ORGANIZATION AND ARCHITECTURE
    (Effective from the admitted batch 2015–16)
    Time: 3 Hours Max.Marks: 60
    ----------------------------------------------------------------------------------------------------
    Instructions: Each Unit carries 12 marks.
    Answer all units choosing one question from each unit.
    All parts of the unit must be answered in one place only.
    Figures in the right hand margin indicate marks allotted.
    --------------------------------------------------------------------------------------- ------------
    MODULE-I
    1. a) Give the design of 4 bit shifter 4
    b) Explain data manipulation operations of a basic computer 4
    c) Design a 4 bit adder/subtractor circuit using full adders 4
    OR
    2. a) Explain the operation of half adder and full adder with diagrams 6
    b) What is shit register? Explain the general capabilities of shift
    registers 6
    MODULE-II
    3. Explain the following:
    a) Address sequencing in control memory 6
    b) Micro program sequencer 6
    OR
    4. a) Explain the phases of an instruction cycle with necessary control
    functions and micro operations 6
    b) Discuss the memory reference instruction in detail 6
    MODULE-III
    5. a) Write a note on vector processing 6
    b) Briefly explain the speed up performance models for pipelining 6
    OR
    6. a) Explain the Booth’s algorithm for multiplication of signed two’s
    complement numbers 6
    b) Write a program to evaluate arithmetic statement: 6
    X=(A+B)*(C+D)
    i) Using an accumulator type computer with one address
    instruction
    ii) Using two, three instruction format
    iii) Using stack organized computer with zero address instruction

    MODULE-IV
    7. a) Draw the block diagram and explain how data is transferred with
    the help of DMA 6
    b) Explain Input-Output Processor with neat block diagram 6
    OR
    8. a) Explain the following in detail: 6
    i) Priority Interrupt
    ii) Daisy-Chaining Priority
    iii) Priority Encoding
    b) Describe I/O peripherals of a computer 6
    MODULE-V
    9. a) A digital computer has a memory unit of 64*16 and a cache
    memory of 1K words. The cache uses direct mapping with a
    block size of four words 6
    i) How many bits are there a in tag, index, block and word
    fields of address format
    ii) How many bits are there in each words of cache and how are
    they divided into functions? Include a valid bit
    iii) How many blocks the cache can accommodate?
    b) Explain memory hierarchy in detail 6
    OR
    10. a) Explain segmented page mapping with the help of suitable
    example 6
    b) Explain the associative memory with a neat diagram and derive
    the match logic for one word of association memory 6

    [3,7/III S/117]

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