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    CE 419

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    CE 419

    Uploaded by

    mahashankar2123
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    CE 419

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    mahashankar2123

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    You are on page 1of 3

    Date:28/12/2022 Enrolment No.

    :___________________

    RK UNIVERSITY
    B.TECH./SEM-III/REMEDIAL/DEC-2022

    CE419: COMPUTER ORGANIZATION AND ARCHITECTURE

    Time: 01:30 PM TO 04:30 PM Total Marks: 100

    Instructions:
    1. Attempt all questions.
    2. Make suitable assumptions wherever necessary.
    3. Figures to the right indicate full marks.
    4. Programmable calculator is not permissible.

    SECTION – I

    Q.1 (a) Select the most appropriate option: (Each of one mark) 06
    1. Which of the following is a type of computer architecture?
    a. Microarchitecture
    b. Harvard Architecture
    c. Von-Neumann Architecture
    d. All of the mentioned
    2. Which of the following is the subcategories of computer architecture?
    a. Microarchitecture
    b. Instruction set architecture
    c. Systems design
    d. All of the mentioned
    3. Which of the architecture is power efficient?
    a. RISC
    b. ISA
    c. IANA
    d. CISC
    4. In CISC architecture most of the complex instructions are stored in _____
    a. CMOS
    b. Register
    c. Transistors
    d. Diodes
    5. Which of the following is the fullform of CISC?
    a. Complex Instruction Sequential Compilation
    b. Complete Instruction Sequential Compilation
    c. Complete Instruction Sequential Compilation
    d. Complex Instruction Set Computer

    Page 1 of 3
    6. The memory devices which are similar to EEPROM but differ in the cost
    effectiveness is ______
    a. CMOS
    b. Memory sticks
    c. Blue-ray devices
    d. Flash memory

    (b) Answer following questions: (Each of two mark) 10


    1. Define: Phases of instruction cycle
    2. What is status command?
    3. Define Address Space & Memory Space.
    4. Define Program counter.
    5. What is micro programmed control?

    Q.2 (a) Explain RISC and CISC. 06


    (b) Explain LDA and BUN instruction in detail. 05
    (c) Draw and explain one stage of arithmetic logic shift unit. 05
    OR
    Q.2 (a) Explain the general register organization of CPU. 06
    (b) Explain register reference instruction. 05
    (c) Draw and explain memory hierarchy. 05

    Q.3 (a) List out 8 registers using in common bus system. 06


    (b) Explain Address sequencing 06
    (c) Explain the stack organization of CPU. 06
    OR
    Q.3 (a) What is program interrupt with flowchart? 06
    (b) List and explain any seven addressing modes with example. 06
    (c) Explain assembler and subroutine. 06

    SECTION – II

    Q.4 (a) Select the most appropriate option: (Each of one mark) 06
    1. Dynamic pipeline allows
    a. Multiples functions to evaluate
    b. Only stream line connection
    c. To perform fixed function
    d. None of these
    2. What is the Basic difference between vector and array processors?
    a. Register
    b. Pipelining
    c. Both A & B
    d. None of these

    Page 2 of 3
    3. Sign bit 1 represents
    a. Positive number
    b. FALSE
    c. TRUE
    d. Negative Number
    4. Half adder is an example of
    a. Combinational Circuits
    b. Sequential Circuits
    c. Asynchronous Circuits
    d. Synchronous Circuits
    5. In J-K flip flop the function K=J is used to realize ?
    a. D flip flop
    b. S-R flip flop
    c. T flip flop
    d. Master slave flip flop
    6. The registers of the controller are ______
    a. 16 bit
    b. 32 bit
    c. 64 bit
    d. 128 bit

    (b) Answer following questions: (Each of two mark) 10


    1. Define peripherals.
    2. How many bit the registers of the controller are using?
    3. Explain cache memory
    4. Define: Subroutine Call.
    5. Explain CPU-IOP communication.

    Q.5 (a) Describe methods of Asynchronous Data Transfer in detail with diagrams. 06
    (b) Explain I/O interface unit. 05
    (c) Write short note on Array Processors 05
    OR
    Q.5 (a) Explain Modes Of Transfer. 06
    (b) Explain Priority Interrupt. 05
    (c) Explain Floating Point Arithmetic Operations with suitable Example. 05

    Q.6 (a) What is Serial communication. 06


    (b) Define DMA. 06
    (c) Explain Virtual Memory. 06
    OR
    Q.6 (a) What is Associative Memory? Explain in detail. 06
    (b) Explain Booth Multiplication Algorithm. 06
    (c) What is Parallel Processing. 06
    *************
    Page 3 of 3

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