ECE 450:DIGITAL SIGNAL

PROCESSORS AND APPLICATIONS

Lecture 11:
DSP Architectures
 Last Session
Amrita School of Engineering, Bangalore

• Block Floating point format

• Comparision of data formats
• Guard Bits
• Sources of Error in DSP Implementations

04/ 02/ 14 © Dr.Shikha Tripathi,ASE, Bangalore 2

 Today’s Session
Amrita School of Engineering, Bangalore

• DSP Architectures
– General architectures
• Architectural aspects
– H/W and S/W aspects
– RISC, CISC
– Endianess

04/ 02/ 14 © Dr.Shikha Tripathi,ASE, Bangalore 3

 Digital Signal Processors
Amrita School of Engineering, Bangalore

• Application Specific • Programmable

– Designed to perform one – Can be programmed for
function more accurately, different applications
faster and is more cost – Cost effective than GPP
effective – Architecture is designed
– Ex.: Digital filters, FFT for repetitive nature of
chips signal processing by
pipelining & parallelism
– Performs certain
operations like MAC
faster than GPP

04/ 02/ 14 © Dr.Shikha Tripathi,ASE, Bangalore 4

 Architecture models
Amrita School of Engineering, Bangalore

• Von-Neumann
– Single memory space
– Inefficient for memory
intensive operations

04/ 02/ 14 © Dr.Shikha Tripathi,ASE, Bangalore 5

Amrita School of Engineering, Bangalore
Architecture models

• Harvard
– Split memory space,
separate prog. & data
buses
– Faster

04/ 02/ 14 © Dr.Shikha Tripathi,ASE, Bangalore 6

Amrita School of Engineering, Bangalore
Architecture models
• Modified Harvard
– Split memory space,
separate buses
– Parallel memory access
(using DARAM/DPRAM)
– Used in TMS320C54x,
1 program & 3 data buses

Data buses Prog. bus

04/ 02/ 14 © Dr.Shikha Tripathi,ASE, Bangalore 7

Amrita School of Engineering, Bangalore
VLIW Architecture
P
• Very Long R Multiported register file
Instruction Word O
G
architecture R
A
• Parallel / serial M Read / write cross bar
execution
C
• Has multiple O
functional units N
T Functional …... Functional
• For signal & IP R Unit 1 Unit n
applications/for O
L
media processors
• Ex. TMS320C6x U
N Instruction cache
I
T 8
04/ 02/ 14 © Dr.Shikha Tripathi,ASE, Bangalore
 Hardware Aspects
Amrita School of Engineering, Bangalore

• CPU
– MAC
– ALU
– Shifter
– Pipelining and parallelism
– Buses
– Data address generator
• Memory
– DARAM/DPRAM/SARAM
• Multiport memories are costlier than multiple access due to
more number of pins and larger chip area but permit parallel
access of memory locations
– Cache
– ROM
04/ 02/ 14 © Dr.Shikha Tripathi,ASE, Bangalore 9
 Hardware Aspects…
Amrita School of Engineering, Bangalore

• Peripherals and Input Output

– Serial port
• Standard serial port
• Buffered serial port
• TDM serial port
• Multi channel buffered serial port( auto-buffering unit supports high
speed transfers & reduces overhead of servicing interrupts)
– Host port interface
– DMA controller
– Parallel port
– Hardware timer
– Power management
• Clock frequency control
• Power-down mode
• Disabling of unused peripherals

04/ 02/ 14 © Dr.Shikha Tripathi,ASE, Bangalore 10

 Software Aspects
Amrita School of Engineering, Bangalore

• Instruction set
– CISC: Complex Instruction Set Computing
– RISC: Reduced Instruction Set Computing
• Programming languages
– Assembly programs
– C programs
• Software development tools
– C compiler
– Assembler
– Linker
– Simulator
– Code Composer Studio (CCS)

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 RISC Vs CISC
• Instruction set is simple. • It is complex.
(>1000 instns.)
Amrita School of Engineering, Bangalore

(typically <100 instructions)

• Simple opcodes (ADD,SUB) • Instructions are tailored to
DSP(FIR,CONV,MACD)
• Compilers for HLL is shorter &
simple. Control unit is small (hard • Compilers for HLL are costly. Control
wired). unit is large (micro prog).

• More no. of registers. • Less no. of registers

• Programs are large • Programs are compact.

• Less time to execute. • More time to execute.

• Easy to pipeline • Difficult to pipeline.

• Programming is complex. • Programming is simple.

• Ex. TMS320C6X • Ex. ADSP 2100X, TMS320C54X,

12
TMS320C8X(RISC/CISC) M563XX
 Endians
Amrita School of Engineering, Bangalore

• Depending on the way bytes are ordered

within a larger object, a Processor can be:
– Big Endian
– Little Endian

• Depends on the way multi byte data is stored.

04/ 02/ 14 © Dr.Shikha Tripathi,ASE, Bangalore 13

Amrita School of Engineering, Bangalore

Eg:- 12345678 can be stored in 4x8bit locations as follows:

Address Big Endian Little Endian

1000 12 78

1001 34 56

1002 56 34

1003 78 12

04/ 02/ 14 © Dr.Shikha Tripathi,ASE, Bangalore 14

 Endians in DSPs
Amrita School of Engineering, Bangalore

• Little Endian → LS Byte first

– TI DSP Processors

• Big Endian → MS Byte first

– Motorola DSP 56k

04/ 02/ 14 © Dr.Shikha Tripathi,ASE, Bangalore 15

 Programmable DSP
Amrita School of Engineering, Bangalore

• Aprogrammable DSP device should provide

instructions similar to Microprocesors
• The computational capabilities provided by these
instructions should inlcude:
– Arithmetic operations like add,subtract &
multiply
– Logic operations like AND,OR,XOR & NOT
– MAC operations
– Signal scaling operations before & after DSP

04/ 02/ 14 © Dr.Shikha Tripathi,ASE, Bangalore 16

 Programmable DSP Cont..
Amrita School of Engineering, Bangalore

• Support Architecture should include:

– On-chip registers for storage of
intermediate results
– On-chip memories for signal
samples(RAM)
– On-chip program memory for programs &
fixed data such as filter coefficients

04/ 02/ 14 © Dr.Shikha Tripathi,ASE, Bangalore 17

 Computational building blocks
Amrita School of Engineering, Bangalore

• Key issue: Speed and accuracy

• DSP computational building blocks
– Multiplier
– Shifter
– MAC Unit
– ALU

04/ 02/ 14 © Dr.Shikha Tripathi,ASE, Bangalore 18

 Next Session
Amrita School of Engineering, Bangalore

• DSP Computational building blocks

– Multiplier
– Shifter

04/ 02/ 14 © Dr.Shikha Tripathi,ASE, Bangalore 19

Amrita School of Engineering, Bangalore

Thank You

04/ 02/ 14 © Dr.Shikha Tripathi,ASE, Bangalore 20