FT/GN/68/01/23.01.

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SRI VENKATESWARA COLLEGE OF ENGINEERING

COURSE DELIVERY PLAN - THEORY Page 1 of 7

LP: CP7103
Department of Electronics and Communication Engineering
Rev. No: 02
B.E/B.Tech/M.E/M.Tech: EC Regulation: 2013 Date: 29/01/2016
PG Specialisation : Applied Electronics
Sub. Code / Sub. Name : CP7103 - Multicore Architectures
Unit :I
Unit Syllabus:
FUNDAMENTALS OF QUANTITATIVE DESIGN AND ANALYSIS:
Classes of Computers – Trends in Technology, Power, Energy and Cost- Dependability-Measuring, Reporting
and Summarizing Performance- Quantitative Principles of Computer Design- Classes of Parallelism- ILP, DLP,
TLP and RLP- Multithreading- SMT and CMP Architectures-Limitations of Single Core Processors- The Multi
core era- Case Studies of Multi core Architectures.

Objective:
This unit gives an introduction to the recent trends in the field of Computer Architecture and identify
performance related parameters.

Session Teaching
Topics to be covered Ref
No * Aids
Introduction to Fundamentals of quantitative design and analysis, Classes of
1. Computers- Personal Mobile Devices, Desktop Computing, Servers, Clusters and 1 PPT
Embedded Computers.

2. Trends in Technology, Power, Energy and Cost. 1 PPT

Dependability- Measuring, Benchmarks, Reporting and Summarizing

3. 1 PPT
Performance.
Quantitative Principles of Computer Design- Amdahl’s Law, Processor
4. 1 PPT/BB
Performance equation

Classes of Parallelism and Parallel Architectures- DLP, TLP and exploitation of 1

5. PPT
Application Parallelism.

6. Instruction Level Parallelism and its exploitation. 1 PPT

7. Tomasulo’s Algorithm - Hardware-based speculation. 1 PPT

8. Multithreading- Fine and Coarse Grained Multithreading. 1 PPT

9. CMP Architectures - Architectures and Advantages. 1 PPT

Limitations of Single Core Processors, The Multi core era- Case studies of Multi
10. 1 PPT
core Architectures.
Content beyond syllabus covered (if any): Nil

* Session duration: 50 minutes

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SRI VENKATESWARA COLLEGE OF ENGINEERING

COURSE DELIVERY PLAN - THEORY Page 2 of 7

Sub. Code / Sub. Name: CP7103- Multicore Architectures

Unit : II

Unit Syllabus:
DLP IN VECTOR, SIMD AND GPU ARCHITECTURES:
Vector Architecture- SIMD Instruction Set Extensions for Multimedia- Graphics Processing Units- Detecting
and Enhancing Loop Level Parallelism- Case Studies.
Objective:
This Unit provides in-depth knowledge about Vector Architecture and the need for parallel processing.

Session Teaching
Topics to be covered Ref
No * Aids

11. Introduction to Vector Architecture, Vector Execution time. 1 PPT

Multiple lanes, Vector length registers, Vector mask register, memory banks,
12. 1 PPT/BB
programming vector architectures.
SIMD Instruction Set extensions for Multimedia, Programming Multimedia
13. 1 PPT
SIMD architecture.
Graphics Processing Units, Programming the GPU, NVIDIA GPU
14. 1 PPT
computational structures.

Graphic Processing Units- Conditional branching in GPU’s, Fermi GPU

15. 1 PPT
Architecture.

16. Similarities and differences between Vector Architectures and GPU’s. 1 PPT

Continuous Assessment Test-I - -

Detecting and Enhancing Loop Level Parallelism- finding dependences,

17. 1 PPT
Eliminating Dependent computations.
Detecting and Enhancing Loop Level Parallelism- Issues, comparison of a
18. 1 PPT
GPU and a MIMD with multimedia SIMD.

19. Case Studies- Implementing a Vector Kernel on a Vector processor and GPU. 1 PPT

Content beyond syllabus covered (if any): Implementing a Vector Kernel on a Vector processor and GPU.

* Session duration: 50 mins

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COURSE DELIVERY PLAN - THEORY Page 3 of 7

Sub. Code / Sub. Name: CP7103- Multicore Architectures

Unit : III

Unit Syllabus:
TLP AND MULTIPROCESSORS:
Symmetric and Distributed Shared Memory Architectures – Cache Coherence Issues- Performance Issues-
Synchronization Issues- Models of Memory Consistency- Interconnection Networks- Buses, Crossbar and
Multi-stage Interconnection Networks.
Objective:
In this Unit, the students are exposed to the problems related to Multiprocessing.

Session Teaching
Topics to be covered Ref
No * Aids
Symmetric and Distributed Shared Memory Architectures –Centralized Shared
20. 1&4 PPT
Memory Architecture.
Cache Coherence Issues – Basic Schemes for enforcing Coherence – Directory 1&4
21. PPT
based and Snooping.

22. Performance Issues – Directory- Based Cache Coherence Protocols. 1 PPT

23. Synchronization Issues – Implementing Locks using Coherence. 1 PPT

24. Models of Memory Consistency – Relaxed Consistency Models. 1 PPT

25. Interconnection Networks - Interconnecting two and more devices. 1 PPT

26. Various interconnection Networks - Buses, Crossbar 2&3 PPT

27. Multistage Interconnection Networks - Design issues 2&3 PPT

28. Summary. - PPT

Content beyond syllabus covered (if any): Nil

* Session duration: 50 mins

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SRI VENKATESWARA COLLEGE OF ENGINEERING

COURSE DELIVERY PLAN - THEORY Page 4 of 7

Sub. Code / Sub. Name: CP7103- Multicore Architectures

Unit : IV

Unit Syllabus:
RLP AND DLP IN WAREHOUSE-SCALE ARCHITECTURES:
Programming Models and Workloads for Warehouse-Scale Computers- Architectures for Warehouse-Scale
Computing- Physical Infrastructure and Costs- Cloud Computing- Case Studies.
Objective:
Students gain knowledge about the different types of Multicore Architectures.

Session Teaching
Topics to be covered Ref
No * Aids
Warehouse-Scale Computers shared and not shared goals and requirements with
29. 1 PPT
server architects.
1
30. Programming Models and Workloads for Warehouse-Scale Computers PPT

31. Computer Architecture of Warehouse - Scale Computers. 1 PPT

32. Physical Infrastructure and Costs of Warehouse-Scale Computers. 1 PPT

33. Measuring efficiency and Cost of a WSC. 1 PPT

34. Cooling and Power in the Google WSC. 1 PPT

Continuous Assessment Test-II - -

35. Cloud Computing - Basic considerations, Clusters and providers issues. 1 PPT

36. Case Studies. 1 PPT

37. Summary. - PPT

Content beyond syllabus covered (if any): Cooling and Power in the Google WSC.

* Session duration: 50 mins

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SRI VENKATESWARA COLLEGE OF ENGINEERING

COURSE DELIVERY PLAN - THEORY Page 5 of 7

Sub. Code / Sub. Name: CP7103- Multicore Architectures

Unit : V

Unit Syllabus:
ARCHITECTURES FOR EMBEDDED SYSTEMS:
Features and Requirements of Embedded Systems – Signal Processing and Embedded Applications- The Digital
Signal Processor- Embedded Multiprocessors- Case Studies.
Objective:
This Unit gives exposure to warehouse- scale and embedded architectures.

Session Teaching
Topics to be covered Ref
No * Aids

38. Introduction to Embedded Systems. 1 PPT

Features and Requirements of Embedded Systems – Hardware and Software

39. 1 PPT
Characteristics of Embedded Systems.

40. Case Studies of Signal Processing and Embedded Applications. 1 PPT

1
41. The Digital Signal Processor- Von Neumann and Harvard Architecture. PPT

Embedded Multiprocessors- Need for Embedded Multiprocessors, Processing 1

42. PPT
Elements and Accelerators.
1
43. Case Studies. PPT

1
44. Case Studies. PPT

1
45. Case Studies. PPT

46. Summary. - PPT

Continuous Assessment Test-III - -

Content beyond syllabus covered (if any):Nil

* Session duration: 50 mins

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SRI VENKATESWARA COLLEGE OF ENGINEERING

COURSE DELIVERY PLAN - THEORY Page 6 of 7

Sub Code / Sub Name: CP7103- Multicore Architectures

REFERENCES:
1. John L. Hennessey and David A.Patterson, “Computer Architecture – A Quantitative
Approach”, Morgan Kaufmann/Elsevier, 5th edition, 2012.
2. Kai Hwang, “Advanced Computer Architecture”, Tata McGraw-Hill Education, 2003.
3. Richard Y.Kain, “Advanced Computer Architecture a System Design Approach”, PHI,
2011.
4. David E.Culler, Jaswinder Pal Singh, “Parallel Computing Architecture: A
Hardware/Software Approach”, Morgan Kaufmann/Elsevier, 1997.

Prepared by Approved by
Signature
Name M.Athappan Dr.S.Muthukumar
Designation Assistant Professor HOD - EC
Date 29.01.2016 29.01.2016
Remarks *:

Remarks *:
* If the same lesson plan is followed in the subsequent semester/year it should be mentioned
and signed by the Faculty and the HOD.
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SRI VENKATESWARA COLLEGE OF ENGINEERING

COURSE DELIVERY PLAN - THEORY Page 7 of 7

Department of Electronics and Communication Engineering

CO: CP7103
B.E/B.Tech/M.E/M.Tech : EC
Rev. No: 02
Regulation : 2013
Date: 29/01/2016
PG Specialisation : Applied Electronics
Sub. Code / Sub. Name : CP7103- Multicore Architectures

Module Coordinator :Ms.S.R.Malathi

CO Statements RBT*
Level
Students will be able to analyze various classes of parallelism and also assess the potential &
L5
limitations of Multiprocessors.
Students will be able to design Multiprocessors with optimal architecture that incorporates various
classes of parallelism and give programming solutions in practical applications. L5
Students will be able to analyze the architecture of Graphic Processing Units, Warehouse Scale
Computers and Embedded Processors. L4
* Revised Bloom’s Taxonomy

Mapping CO – PO - PSO:

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO-1 PSO-2

CO1 A A A A A C

CO2 A A A A A A A

CO3 C A C A C

A – Strong ; B – Moderate; C - weak

Course Requirements
1. Scientific Calculator
Assessment Methods
1. Assignment 1 + CAT 1
2. Assignment 2 + CAT 2 Internals - 20 Marks
3. Assignment 3 + CAT 3
4. Attendance (Not applicable for R2013)
5. End semester exam - 80 Marks

Signature of Faculty / Course Coordinator Signature of Module Coordinator