Chapter 7

Conclusion and Future Research

Directions
 Chapter 7 Conclusion and Future Research…..

7.1 Conclusion
The continuous miniaturization of the CMOS technology resulted in ultra fast
processors and will also degrade the device performance due to Short Channel Effects
(SCEs). In order to overcome these problems, various device engineering techniques
were proposed like source drain engineering (LDD MOSFET) lateral channel
engineering (i.e. graded channel MOSFET, halo and Dielectric Pocket MOSFET),
gate dielectric engineering (i.e. gate stack MOSFET), substrate engineering (i.e.
Silicon On Insulator and Silicon On Nothing MOSFET) and gate electrode
engineering (i.e. double gate MOSFET). The work presented in this dissertation was
mainly focused on Dielectric Pocket MOSFET from lateral channel engineering,
Silicon On Nothing MOSFET from substrate engineering and Double Gate MOSFET
from gate electrode engineering techniques that can overcome the demerits associated
with bulk MOSFET and also offers improve device performance.
In addition, CMOS circuit design demands the accurate modeling of non-classical
devices for describing the behavior of various electrical parameters prior to the device
fabrication. This requires exact solution of the basic semiconductor equation i.e.
Poisson’s equation, continuity equation, current transport equation and other related
equations. The solution of these equations invariably involved numerical analysis.
The situation becomes even more complex for nano-scale devices where 2-
dimensional or 3- dimensional effects are to be accounted in modeling. Thus, a two
dimensional analytical model which can give approximately same results as obtained
from the device simulation within acceptable tolerance would be very useful.
Furthermore, in nano-scale regime, the process variation has also major impact on the
device behavior.
Thus the conclusions derived from the present dissertation are divided into two
sections, namely, (a) Impact of dielectric pockets (or insulating layers) on the Single
Gate geometry and (b) on Double Gate geometry. These dielectric pockets (or
insulating layers) are either present at the side wall of the channel (i.e. inside the
Source/Drain region) or inside the channel region. Physics based analytical model of
the different non-classical architectures are used to study the electrical characteristics
of the device and the same is verified with the numerical simulations obtained from

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the ATLAS 3D device simulator.

Chapter 1 provides the overview about the various non-classical device architectures
used in this dissertation, their merits and demerits and also the possible solution to
overcome the demerits associated with the devices. The fabrication related issues of
the devices are also discussed in chapter 1.

7.1.1 Impact of Dielectric Pockets (Insulating Layers) on Single Gate Geometry

Insulated Shallow Extension (also known as Dielectric pocket MOSFET) MOSFET in

which the dielectric pockets (Insulating layer) are presents at the side wall of
source/drain regions suppresses the lateral electric field penetration from heavily
doped drain to source region and thereby showing reduction in Drain Induced Barrier
Lowering (DIBL) and Hot Carrier Effects. Silicon On Nothing MOSFET (or Empty
Space in Silicon MOSFET) in which the ultra thin layer of silicon channel rest over
the insulating layer (or dielectric pocket which is air in medium) i.e. Buried Oxide
(commonly called BOX) suppresses the back channel coupling from heavily doped
drain to channel region and thereby reducing the SCEs.
Chapter 2 describes potential advantage of Insulated Shallow Extension Silicon On
Nothing (ISESON) MOSFET that combines the advantages of both Silicon On
Nothing and Insulated Shallow Extension/Dielectric Pocket (DP) MOSFET through
an efficient physics based analytical drain current model. The developed model is
further extended for investigating the impact of operating temperature on the device
performance. It was also observed that introduction of gate stack architecture on
ISESON MOSFET exhibits significant enhancement in terms of improved gate
controllability over the channel (i.e. higher Ion), reduced DIBL, sub-threshold slope
resulting in better immunity of electrical parameters against temperature variation.
Device performance can be enhanced further by tuning the device geometry
parameters like channel thickness, permittivity of buried oxide, side pillar thickness.
Results also reveal that ISESON MOSFET shows better scalability even at the higher
operating temperature. ISESON MOSFET with buried oxide when filled with air and
SiO2 are compared and it was observed that air provides a better electrical isolation of
the channel from the substrate.
The chapter also deals with the development of 2-D analytical drain current model for

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Ultra-Thin Body ISESON architecture. The accuracy of the proposed model is

verified using ATLAS 3D device simulator results for channel length down to 32 nm.
Results reflect that by tuning the back gate bias voltage of UTB ISESON architecture,
significantly improvement in terms of reduced DIBL, Sub-threshold Slope (S),
threshold voltage (Vth) lowering and leakage current (Ioff) along with the improvement
in Ion/Ioff ratio were observed.
The proposed device (ISESON) also shows superior performance in terms of Voltage
Transfer Characteristics (VTCs) and propagation delay (τ) of NMOS inverter and
VTCs of CMOS inverter, as compared to SON and ISE MOSFETs and hence justifies
its possible usage for high-speed digital, switching applications.
Chapter 3 deals with the analog and linearity performance investigations of ISESON
architecture at higher operating temperatures and also compared the same with other
conventional devices i.e. ISE and SON MOSFET through numerical simulation using
ATLAS 3D device simulator. The significant improvement in various analog
performance metrics like a) device efficiency (gm/Ids), b) device gain (gm/gd), c) early
voltage (Vea) and d) output resistance (Rout) can be observed in ISESON MOSFET as
compared to SON and ISE MOSFETs optimized at the same threshold voltage.
Results show that lower value of shallow extension depth (Xe) and thicker dielectric
pillar will further enhance the device performance for analog and RF applications.
The behavior of the devices for RF applications in terms of VIP2, VIP3 and IIP3 are
also assessed in this chapter. The impact of parametric variation on linearity
performance metrics of ISESON architecture has also been examined to determine
optimum bias point. Gate stack configuration further improves the device
performance for analog and RF application by lowering leakage current and DIBL
effect. The performance degradation at higher operating temperatures is also lower in
ISESON MOSFET as compared to other devices thereby proving its efficacy for high
temperature operations.
In Chapter 4 extensive consideration has been given to demonstrate the advantage of
ISESON MOSFET for high speed digital applications through exhaustive mixed
mode simulation using ATLAS 3D device simulation. The advantage of smaller sub-
threshold slope, lower leakage current and reduced DIBL effect for a ISESON
MOSFET improves the switching characteristics of the device in the form of lower

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propagation delay that boost the speed of the device in comparison to SON and ISE
MOSFET.
The results also show that ISESON MOSFET has better Voltage Transfer
Characteristics and higher noise margin than conventional SON and ISE MOSFET.
The analysis predicts that ISESON MOSFET is more reliable in terms of variation in
supply voltage and channel length and is also more resistant towards temperature
variation as the device exhibits better circuit performance as compared to other
devices. The impact of process variation in the position of dielectric pockets (i.e.
either it was present inside the S/D region or inside the channel region) on the circuit
performance is also marginal in ISESON MOSFET resulting in immunity against
process variation.
Moreover the improved performance of ISESON based various logic gates (NAND,
NOR and XOR) in terms of propagation delay is also observed in chapter 4. It was
also found that performance of sequential circuits (i.e. R-S Flip Flop and D Flip Flop)
based on ISESON MOSFET has minimum propagation delay in comparison to SON
and ISE based circuits. In addition, ISESON MOSFET also shows relatively lower
parasitic capacitances and improved device reliability in comparison to SON, and ISE
MOSFETs for channel length down to 22 nm.

7.1.2 Impact of Dielectric Pockets (Insulating layers) on Double Gate Geometry

The impact of insulating layers (or dielectric pockets) on the performance of double
gate MOSFET has been discussed by considering two cases: 1) presence of dielectric
pocket at the side wall of the source/drain regions i.e. Dielectric Pocket Double Gate
MOSFET and 2) presence of insulating layer inside the channel region i.e. Empty
Space in Double Gate MOSFET.
Chapter 5 explores the impact of Dielectric Pocket on the performance of Double
Gate i.e. DP-DG MOSFET through an efficient 2-D analytical model solved using
superposition technique and consequentially comparing the results with the
conventional double gate and dielectric pocket MOSFETs. The discussed model is
also useful for estimating the drain current from sub-threshold to saturation region of
operation. The proposed model includes evaluation of surface potential, electric field,
threshold voltage (Vth), Drain Induced Barrier Lowering (DIBL), sub-threshold slope

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(S), drain current (Ids), trans-conductance (gm), device efficiency (gm/Ids) and Voltage
Transfer Characteristics (VTCs) of NMOS inverter that greatly simplifies the device
characteristics assessment. Analytical results of temperature dependent drain current
model have also been verified with the simulated results. With increasing
temperature, leakage current of the device also increases because of two additional
current components i.e. 1) current due to thermal generation and 2) impact ionization
current.
The results reflect that, DP-DG MOSFET offers better sub-threshold performance
along with improved device reliability in terms of lower electron temperature and
lateral electric field and better linearity distortion metrics like VIP2, VIP3 and IIP3 as
compared to bulk, DP and DG MOSFETs. The higher Ion/Ioff ratio in DP-DG
MOSFET indicates faster switching response (i.e. lower propagation and intrinsic
delay) as compared DG, DP and bulk MOSFETs. The results also highlight the lower
sensitivity of DP-DG MOSFET against temperature variation as compared to other
devices i.e. DP and DG MOSFETs. This is so because of the 1) presence of dielectric
pocket at the side walls that can increase the breakdown voltage of the device, 2)
double gate architecture which can enhance the gate controllability over the channel
resulting in lower leakage current.
DP-DG MOSFET also exhibits potential advantages in terms of lower parasitic
capacitances (Cgs and Cgd), higher noise margin, and lower static and dynamic power
dissipation as compared to other devices for high speed digital applications. In
addition to this, the impact of structural modification (i.e. either dielectric pocket is
present at the S/D junctions i.e. partially inside the channel region or partially inside
the S/D region or inside the drain region) on the performance of DP-DG MOSFET is
also studied. It was found that the presence of DP inside the S/D region shows
enhanced linearity and digital performance. The chapter, thus, presents DP-DG
MOSFET as a viable candidate for analog and high speed digital circuits at 60-nm
technology node.
Chapter 6 explores the impact of Empty Space layer (present inside the channel
region) on the performance of Double Gate MOSFET known as Empty Space in
Double Gate (ESDG) MOSFET through physics based analytical drain current model.
The accuracy of the proposed model calculated using EMA technique is verified using

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ATLAS 3D device simulation results. Lower leakage current, higher drive current and
lower threshold voltage roll-off with device scaling pertained by the ESDG MOSFET,
extends its applicability at shorter channel length in comparison to DG, bulk ESS
MOSFET and conventional bulk MOSFET. The impact of varying the length of
empty space layer on the sub-threshold performance like sub-threshold slope (S),
threshold voltage (Vth), DIBL and leakage current has also been examined to
determine optimum length of the empty space layer for efficient device performance.
It was also found that, ESDG MOSFET has improved device performance such as
higher device gain (gm/gd), device efficiency (gm/Ids), output resistance (Rout), early
voltage (Vea), Ion/Ioff ratio, and noise margin and lower delay time (  d ) and on

resistance (Ron), as compared to other devices even at higher operating temperature.

ESDG architecture also shows remarkable performance improvement in terms of the
propagation delay of various logic circuits such as NAND gate, NOR gate and 3-stage
ring oscillator as compared to other devices.
Thus ESDG MOSFET architecture is a best choice for future analog and digital
circuits design because of improved short channel immunity, and better analog and
digital performance metrics.
Chapter 7 deals with the overall summary or conclusion drawn from the present
dissertation and the future research directions.

7.2 Future Research Directions

Scaling CMOS towards sub-100 nm channel length generation necessitates the need
for innovative alternative MOSFET architectures, as proposed in this dissertation, to
circumvent the major problems of scaled MOSFET i.e. undesirable SCEs and leakage
current. The work presented in this dissertation mainly focused on analog and digital
performances of proposed non-classical MOSFETs. Various imperative issues and
applications of proposed devices still need exploration at nano-scale regime. Thus the
suggestions for future work related to this dissertation are highlighted below.
 The device reliability issues of ISESON MOSFET can be further suppressed
by using lower work function of the metal gate near the drain side i.e. DMGISESON
MOSFET. Thus the impact of DMG on the performance of ISESON MOSFET will be

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studied in near future by developing the physics based analytical model.

 Noise analysis of the proposed architecture can also be performed.
 A lot of scope lies in studying the impact of quantum confinement on the
various non-classical devices i.e. ISESON MOSFET, DP-DG MOSFET and ESDG
MOSFET.
 The development of the small/large signal equivalent model of the different
devices can also be thought of for calculating the Y-parameters. The S-parameters can
also be calculated from equivalent circuit model which is further used to analyzed the
device behavior for RF application.

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