Solid-State Electronics 49 (2005) 965–975

www.elsevier.com/locate/sse

A numerical study of scaling issues for trench power MOSFETs

a,*
J. Roig , I. Cortés a, D. Jiménez b, D. Flores a, B. Iñiguez c, S. Hidalgo a, J. Rebollo a

a
Centro Nacional de Microelectrónica, CNM-CSIC, Campus UAB, 08193 Bellaterra, Barcelona, Spain
b
Departament d’Enginyeria Electrònica, ETSE, Universitat Autònoma de Barcelona, 08193 Bellaterra, Barcelona, Spain
c
Departament d’Enginyeria Electrònica, Elèctrica i Automàtica, ETSE, Universitat Rovira i Virgili, 43007-Tarragona, Spain

Received 20 October 2004; received in revised form 14 February 2005; accepted 28 March 2005

The review of this paper was arranged by Prof. S. Cristoloveanu

Abstract

The effect of the scaling down on the electrical performance of trench power MOSFET structures is investigated in this work by
means of numerical simulation tools. Layout dimensions of trench power MOSFETs have been continuously reduced in order to
decrease the specific on-resistance, maintaining equal vertical dimensions. Nowadays, the last scaling efforts provide trench width
and distance between two consecutive trenches in the submicron range. The resultant short distance between gates is expected to
induce significant modifications in the device electrical performances, since the fully depletion condition will be feasible in the body
region. Hence, the influence of the fully depleted body on the on-state resistance, threshold voltage, breakdown voltage, parasitic
bipolar transistor and internal capacitances are features of particular interest. Furthermore, device reliability aspects, such as hot-
carrier and self-heating effects, are evaluated by numerical simulation in trench power MOSFETs for the first time.

2005 Elsevier Ltd. All rights reserved.

Keywords: Power MOSFETs; Trench semiconductor devices; Gate–drain charge; Double-gate devices

1. Introduction cm2 [3] range due to its superior scalability. Recently,

the gate-to-drain capacitance (Crss) has become the key
Trench power MOSFETs for applications ranging parameter for high operation frequency of power MOS-
from 5 to 100 V emerged in the last decade with FET devices, thus being improved by implementing new
improved electrical performances in comparison with con- technological processes [4]. Indeed, the new require-
ventional planar DMOSFETs. The widespread growth ments of power supplies operating at high switching
of trench architecture has been driven by the increase frequency can be matched by using trench power MOS-
in communication, portable computer and automotive FETs as the control switch [5].
electronics, requiring voltage regulator modules for The layout dimensions of trench power MOSFETs
power supplies with reduced power consumption [1,2]. have been drastically reduced in order to maximise the
The power MOSFET device engineering has been current capability. Nowadays, the trench width (Ltrench)
mostly focused on the reduction of the specific on- and the distance between trenches (Dtrench), defined in
resistance (RON · S) at a given voltage capability. As a Fig. 1, are both scaled to 0.4 lm [3,6] using power MOS-
matter of fact, the arrival of the trench MOSFET struc- FET technologies. Further reduction of these geometri-
ture allowed a reduction of the RON · S to the 0.1 mX cal parameters will lead to problems for the contact
window opening in the gate and source electrodes. How-
*
Corresponding author. Tel.: +34 935947700; fax: +34 935801496. ever, recent low power technologies implement vertical
E-mail address: jaume.roig@cnm.es (J. Roig). MOSFETs in silicon pillars whose thickness about

0038-1101/$ - see front matter
2005 Elsevier Ltd. All rights reserved.
doi:10.1016/j.sse.2005.03.026
966 J. Roig et al. / Solid-State Electronics 49 (2005) 965–975

the state-of-the-art [3,14,15], is examined in this paper.

The parameters used in the performed simulations are
an Na Gaussian decay from 1017 to 1016 cm
3, a drift
doping concentration (Nd) of 2 · 1016 cm
3, a drift
length (Ldrift) of 0.8 lm, a channel length (Lchannel) of
0.8 lm, an accumulation length (Lacc) of 0.2 lm, a gate
oxide thickness (Tox) of 30 nm, and a trench width
(Ltrench) of 0.5 lm. The work analyses the impact of a
Dtrench reduction from 0.5 to 0.1 lm on the relevant elec-
trical parameters. The conduction state characteristics
(threshold voltage, specific on-resistance and FBSOA)
are discussed in Section 2, the blocking state character-
istics (breakdown voltage and leakage current) in Sec-
tion 3, the capacitance evaluation is found in Section 4
and, finally, a reliability study (hot-carrier and self-
heating effects) is reported in Section 5. The use of alter-
native models in Section 2 is remarkable to increase the
Fig. 1. (a) Half of the trench power MOSFET structure with the prediction accuracy of RON · S.
relevant geometrical and technological parameters. (b) Doping con- This work is focused on the effect of the layout scal-
centration profile and RON · S components along the AA 0 cut. ing down. However, an additional scaling down study
could be done when considering the vertical reduction
of the body diffusion. Indeed, the vertical dimensions
0.1 lm [7,8]. As a result, trench power MOSFETs with of the trench power MOSFETs have never been reduced
Dtrench about 0.1 lm seem feasible by increasing the to the submicron range in order to avoid the punch
technological processing cost. Hence, there is a trade- through effect in the body [16]. It is well known that
off between process technology development addressed the decrement of the distance between the two gates in
to a further scaling down and the electrical perfor- a DG MOSFET structure reduces the short channel
mances of trench power MOSFETs. This work is basi- effect and enables the shortening of Lchannel [17]. Recent
cally focused on the impact of Dtrench reduction on the research on trench power MOSFETs supports the
electrical characteristics. importance of the Lchannel reduction for decreasing
The shrinkage of Dtrench below a certain thickness RON · S [18]. In that case, Lchannel was reduced by
value leads to a fully depleted gate-to-gate silicon region. implementing the P body with a retrograde doping pro-
Consequently, a Double Gate (DG) MOSFET configu- file. Nevertheless, this analysis has not been addressed in
ration has to be considered in the body of the trench this paper since this work is devoted to study the pure
power MOSFET, accounting for the Gaussian doping influence of Dtrench reduction, isolating this effect from
concentration decay (Na) shown in Fig. 1. The advanta- other possible improvements due to different structure
ges of the DG MOSFET have been widely reported in modifications. Moreover, the complexity of the RON · S
the literature [9] and some of them can be extended to modelling increases when appearing short channel
the trench power MOSFET. In this sense, the nearly effects. In fact, this subject would require an extensive
ideal subthreshold swing, the increased saturation cur- study which deserves further analysis in the future.
rent, and the reduced short channel and floating body
effects can provide superior electrical performances.
Moreover, a significant reliability improvement in DG 2. Conduction-state analysis
MOSFETs has also been reported due to the elimination
of the hot-carrier effect [10] which is also crucial in 2.1. Threshold voltage and subthreshold swing
trench power MOSFETs at long time operation [11].
Note that the reduced hot-carrier and short channel Trench power MOSFET structure described in Fig.
effects are additionally improved when implementing 1a and b has been simulated to extract the threshold
the Gaussian Na decay in comparison with the uniform voltage (Vth) and the subthreshold swing (S) values for
doping profile case [12]. Dtrench = 0.5 and 0.1 lm. It can be observed in Fig. 21
The impact of the gate-to-gate distance reduction on that Vth is reduced from 1.56 to 1.09 V (a 30% reduc-
the trench power MOSFET electrical characteristics as tion) when scaling down Dtrench from 0.5 to 0.1 lm. As
well as on the device reliability is analysed by means
of DESSIS-ISE device simulator [13]. A stripe configu-
ration structure with the geometrical and technological 1
The current density plotted in all the figures refers to the current
parameters defined in Fig. 1a and b, in accordance with density per unit active area.
 J. Roig et al. / Solid-State Electronics 49 (2005) 965–975 967

ture. For this purpose, numerical simulations with the

DG MOSFET structure depicted in Fig. 3a have been
performed. In this case, the simulated structure has a
uniform doping body concentration (Na) thus simplify-
ing the simulation process. The RON_channel vs. Dtrench
set of curves in Fig. 3b have been obtained by using
Tox = 50 nm, Lchannel = 1 lm and Na = 1 · 1017 cm
3 as
a function of Dtrench. It can be clearly observed from
the simulation values that RON_channel shows a linear
dependence for Dtrench values above 0.3 lm and Vg
above 5 V (extremely high Vg values in this case2). This
linear behaviour is already predicted by the classical
charge sheet (CCS) model. The CCS approach which
describes RON_channel in a stripe layout configuration is
Lchannel Dtrench þ Ltrench 1
Fig. 2. Id vs. Vg for Dtrench = 0.1 and 0.5 lm at Vd = 0.01 V. RON channel ¼ ð1Þ
ln C ox 2 V g
V th
where Cox is the gate oxide capacitance (Cox = eoxeo/Tox)
expected from [7], the Vth decrement is due to the cur- and ln is the electron mobility in the inversion layer
rent following the weak inversion mechanism which (ln = 500 cm2/sV).
becomes important at Dtrench = 0.1 lm. A theoretical For Dtrench values below 0.3 lm and Vg under 5 V,
expression to calculate Vth was reported in [9], predict- the obtained RON_channel values are lower than those pre-
ing 1.04 V value in the Dtrench = 0.1 lm case, while the dicted by the CCS model. The basic reason for this dec-
typical expression for bulk MOSFETs gives a Vth value rement is the current conduction in the volume [9] which
of 1.67 V. Apart from the Vth shift, S also changes from is neglected in the CCS model. Indeed, minority carriers
144 to 78 mV/dec, thus approaching to the ideal S value are no longer confined to the interface and they spread
(60 mV/dec). out across the silicon film. In some cases, the simulated
values are less than a half of the theoretically predicted
2.2. Specific on-resistance ones. As inferred from Fig. 3b, the discrepancies
between the CCS model and the simulation results
Although the specific on-state resistance inherent to are not observed at extremely high gate bias (i.e.
the trench power MOSFET is the sum of several contri- Vg = 10 V), where Vth is less significant in front of Vg.
butions, as plotted in Fig. 1b, the most important are In order to provide an accurate model of RON_channel
those related to the resistance of channel (RON_channel) for devices with small Dtrench values, the moderate
and drift (RON_drift) regions. The resistances accounting surface inversion model3 for Ultra-Thin DG MOSFETs
for source (RON_source), drain (RON_drain) and accumula- has been used [9]. According to this model, the
tion (RON_acc) regions are usually neglected when reduc- RON_channel can be expressed as
ing the basic cell pitch in a trench power MOSFET Lchannel Dtrench þ Ltrench
structure [2,19]. RON channel ¼
ln 2
In general, RON · S decreases when reducing Dtrench.
On the other side, and in accordance with [2,19], the 1
 ð2Þ
RON · S evolution with Ltrench exhibits a minimum for esi Es
ðqN a Dtrench =2Þ
Dtrench values above 1 m. Thus, for values below a given where Es is the surface electric field which can be found
Ltrench, RON · S is degraded and it is not worth to by numerically solving the following set of equations
reduce the trench width. This is a consequence of the esi
opposite trend of RON_channel and RON_drift with Ltrench; Es ¼ V g
V FB
/s ð3Þ
C ox
i.e. RON_channel decreases and RON_drift increases when
reducing Ltrench. However, the existence of a minimum
RON · S value is no longer observed when Dtrench is
strongly reduced [2] because RON_drift is almost constant 2
Note that, owing to the relative small Vth (about 1 V), Vg voltages
with Ltrench. Hence, it is convenient to reduce both lower than 5 V are commonly applied in trench power MOSFETs
Dtrench and Ltrench to obtain a satisfactory current capa- presenting similar channel structures [6]. Higher Vg values result in loss
bility increment. of gate control as well as high electrical stress and dielectric breakdown
in the worst case.
As a previous step to the total RON · S evaluation, 3
The name ‘‘moderate surface inversion model’’ has been used to
the RON_channel dependence with Dtrench is analysed sep- follow the same nomenclature as in [9]. However, this model is
arately from the whole trench power MOSFET struc- demonstrated to be suitable in moderate and strong inversion regimes.
968 J. Roig et al. / Solid-State Electronics 49 (2005) 965–975

Fig. 3. (a) DG MOSFET structure used to analyse the Channel Resistance in trench power MOSFETs (b) Channel Resistance vs. distance between
trenches at Vd = 0.1 V and Vg = 3, 5 and 10 V.

n2i ðkTq Þ/s After analysing RON_channel, the effect of Dtrench

ns ¼ e ð4Þ
Na shrinkage in the global specific on-resistance (RON ·
S = RON_channel + RON_drift) is evaluated using the trench
q kT power MOSFET structure described in Fig. 1a and b.
/s ¼ V g
V FB

esi q This structure shows a Gaussian profile at the channel
 
ns esi
ð
q=kT ÞðDtrench =2ÞEs  qN Dtrench region which corresponds to the body diffusion.4
 e
1
a Apart from RON_channel, the RON_drift is typically
Es C ox C ox 2
modelled by [2,19]
ð5Þ   
1 Dtrench þ Ltrench Dtrench þ Ltrench
Eq. (3) is derived from the GaussÕs Law at the Si/SiO2 RON drift ¼ ln
qld N d 2 Ltrench
interface, Eq. (4) comes from the PoissonÕs equation
and Eq. (5) is the result of using a TaylorÕs development 
Dtrench
of the potential distribution (x) around the surface, þ Ldrift
ð7Þ
2
dropped to the first order term. In Eqs. (3)–(5), /s is
the surface potential, VFB is the flatband voltage, ns is assuming a 45 current spreading angle, which is defined
the electron concentration at surface and ni is the intrin- as a. In this case, ld accounts for the electron mobility in
sic electron concentration. the drift region at low electric field values (ld =
The good match between the DG MOSFET theory 1000 cm2/sV). Eq. (7) is recommended to be applied
and the simulation results, in the range where the CCS when Ldrift > Dtrench/2, which is the case of the analysed
model fails, can be observed in Fig. 2. On the other trench power MOSFET.
hand, the DG MOSFET theory is limited to the fully The comparison between simulation and theoretical
depleted case thus giving for a high discrepancy at large RON · S values is reported in Table 1 at different gate
Dtrench values. Hence, we propose to use Eq. (2) instead values. From this table it can be inferred that using
of Eq. (1) when the fully depletion is reached at the typical models (Eqs. (1) and (7)) severe discrepancies
2Wg P Dtrench, Wg being the gate-induced depletion in all cases are obtained. The use of Eq. (2) instead of
length [20], represented by Eq. (1) introduces higher accuracy in the Dtrench =
sffiffiffiffiffiffiffiffiffiffiffiffi 0.1 lm case. However, the match between theory and
4es /F simulation is not as good as in the DG MOSFET former
Wg ¼ ð6Þ
qN a case (where only the RON_channel component was consid-
ered). In that case, an error less than 15% was found
where /F is the Fermi potential. In the case under study using Eqs. (1) and (2) for Dtrench = 0.5 and 0.1 lm,
2Wg is 0.21 lm, which coincides with the Dtrench value of
Fig. 3b where RON_channel is drastically reduced. It is
worth to remark that the present modelling analysis is 4
Eq. (1) is commonly adopted to model channel regions accounting
limited to Dtrench values above 50 nm. For smaller for a Gaussian profile in trench power MOSFETs [2,19]. For this
Dtrench values, the ballistic transport and the quantum purpose, Eq. (1) requires an average ln value and the use of the Vth
corrections must be considered. value evaluated at the maximum doping concentration.
 J. Roig et al. / Solid-State Electronics 49 (2005) 965–975 969

respectively. Since the RON_channel component has been dominance of RON_drift or RON_channel depends on the
demonstrated to be accurate, the discrepancies are basi- gate bias. For instance, in Dtrench = 0.1 lm case, the
cally due to the rough approach when calculating the RON_drift value ranges from 25% at Vg = 2 V to more
RON_drift value. Indeed, Eq. (7) has been obtained than 60% at Vg = 4 V. Note also from Table 1 that the
assuming that the current spreads into the drift with a DG MOSFET model is not applied to the Dtrench =
constant 45 angle. In order to obtain a major accuracy, 0.5 lm case since the fully depletion is not achieved. In
some works have introduced a spreading angle or a fit- addition, there are no data for Vg = 2 V in Dtrench =
ting parameter [11,21] which has to be tuned depending 0.5 lm because the transistor is still not conducting, as
on the structure characteristics. Therefore, a more gen- inferred from Fig. 3.
eral expression for Eq. (7) is
8 h  i 2.3. Forward biasing safe operating area
>
> 1 Dtrench þLtrench
 ln Dtrench þLtrench
þ L
Dtrench
;
> qld N d
> 2tana Ltrench drift 2tana
>
>
< trench < L
D In order to avoid the parasitic bipolar activation in
2tana drift
RON drift ¼ h  i trench power MOSFETs, the grounded source contact
> 1 Dtrench þLtrench  ln Dtrench þLtrench ;
>
>
> qld N d 2tana Ltrench is normally connected to the body region. Subsequently,
>
>
: Dtrench the N+ source area is lower than the contact source area
2tana
P L drift
(see Fig. 1a). In the performed simulations, Dtrench is
ð8Þ
reduced preserving the percentage of the source elec-
where a is related with the trench power MOSFET geo- trode area (about 50%) directly connected to the body;
metrical parameters by i.e. trench power MOSFET with shorted source. How-
  ever, the scaling down process inherently increases the
Ltrench Ldrift
tan a ¼ c  1
 ð9Þ complexity of the source engineering design. Hence,
Dtrench þ Ltrench Ldrift þ ðLtrench =2Þ
trench power MOSFET structures without shorted
This expression has been previously applied in the heat source with Dtrench = 0.1 and 0.5 lm have been analysed.
spreading effect modelling [22] to correct the constant Although the source-to-body connection is not relevant
spreading angle approach. Thus, an analogy between in the final RON · S value, it is expected to have an
the current and the heat spreading effects is used to pro- important impact in the activation of the parasitic bipo-
vide a general expression for RON_drift. The c factor has lar transistor.
been introduced in Eq. (9) to fit the a value at Ldrift  The IdVd curves for Dtrench = 0.1 and 0.5 lm are de-
Ltrench  Dtrench condition, where 45 is usually fixed. picted in Fig. 4 at different gate bias for the with shorted
Combining Eq. (8) with Eq. (1) or Eq. (2) and fixing source (with s.s.) and without shorted source (w.o. s.s.)
c = 0.42 (i.e. a = 23 when Ldrift  Ltrench  Dtrench), a structures. As reckoned in conventional trench power
higher accuracy is obtained in all the cases, as demon- MOSFETs, a great difference between the IdVd family
strated in Table 1. Nevertheless, there is a 20% error curves is found in Dtrench = 0.5 lm structure. In this
for Vg = 4 V and Dtrench = 0.1 lm. This error is basically case, the decrease of the body-to-source potential barrier
due to the neglected dependence of a with the gate volt- because of the impact ionization current (which injects
age. The relation of the current flow line distribution charge in the body) leads to a reduction of the threshold
with Vg has been demonstrated in [13,23]. voltage, which in turn originates a sudden increase of
It is worth to point out that the theoretical RON_drift the drain current (kink effect) [24,25]. At higher values
values extracted from Eq. (8) are 0.032 and of the impact ionization, current the source-to-body
0.068 mX cm2 for Dtrench = 0.1 and 0.5 lm, respectively. junction can become sufficiently forward-biased in order
This means that the RON_drift component has always a to activate the parasitic bipolar transistor. This also
significant contribution to the total RON · S. The pre- explains the premature breakdown observed in this

Table 1
Simulation and theoretical RON · S values for the trench MOSFET structure depicted in Fig. 1 at Vd = 0.1 V
Vg (V) Simulation (mX cm2) Theory (mX cm2)
Eqs. (1) + (7) Eqs. (2) + (7) Eqs. (1) + (8) Eqs. (2) + (8)
Dtrench = 0.5 lm
2 – – – – –
3 0.142 0.080 – 0.120 –
4 0.104 0.058 – 0.098 –
Dtrench = 0.1 lm
2 0.124 0.152 0.126 0.158 0.132
3 0.070 0.057 0.056 0.064 0.062
4 0.066 0.043 0.043 0.050 0.050
970 J. Roig et al. / Solid-State Electronics 49 (2005) 965–975

parts. The behaviour of trench power MOSFETS con-

ducting very high current densities is extensively
explained in [14]. As stated in [14], the current density
at quasi-saturation behaves like Jn / W
1, where W is
the width of the existing current paths. It seems obvious
that, in general, small W values are obtained when the
current flows along the drift region in reduced Dtrench
values and, as a consequence, high Jn is originated.

3. Blocking-state analysis

As stated in other works [2], the voltage capability of

a trench power MOSFET structure is not influenced by
the layout scaling down on condition that the break-
down is purely due to avalanche by impact ionization
process. The drain voltage is assumed to be only sup-
ported in the vertical direction across the drift region
and, as a result, the reduction of Dtrench or Ltrench does
not affect the drift voltage capability. The invariability
of Vbr when Dtrench is scaled down from 0.5 to 0.1 lm
has been observed by numerical simulation. The simu-
lated Vbr values, summarised in Table 2, are in the range
of 32 V, in the case of ‘‘with s.s.’’ structure.
The importance of the body-to-source electrode con-
nection to obtain a high voltage capability has been cor-
roborated by numerical simulations in the case of ‘‘w.o.
s.s.’’ structure. For Dtrench = 0.5 and 0.1 lm, the voltage
capability decreases more than 30% due to the activa-
tion of the parasitic bipolar transistor and, as a conse-
Fig. 4. FBSOA for Dtrench = 0.1 and 0.5 lm at different Vg values. quence, the premature breakdown. In the Dtrench =
0.1 lm case, the bipolar activation cannot be suppressed
since Vg = 0 V and the fully depletion does not occur.
Concerning the leakage current density (Ileakage),
device. Therefore, the FBSOA is reduced. On the other
about 30% reduction (at Vbr/2) for Dtrench = 0.1 lm is
hand, similar IdVd family curves at Dtrench = 0.1 lm have
obtained with the ‘‘with s.s.’’ structure, as inferred from
been obtained for the ‘‘with s.s.’’ and ‘‘w.o. s.s.’’ struc-
the values summarised in Table 2. This is a consequence
tures. This is because of the reduction of floating body
of the reduction in the area percentage accounting for
effects, in particular the kink effect, when fully depletion
P/N
junction between body and drift regions. How-
is reached. The body-to-source potential barrier is lower
and more stable under the influence of the impact ioni-
zation current, compared to partially depleted devices
(such as the 0.5 lm device). Higher impact ionization Table 2
current from the drain is needed to produce a change Simulation values of basic electrical parameters for the trench
in the body-to-source potential [24,25]. This reduces MOSFET structure depicted in Fig. 1
the floating-body effect, in particular the kink effect. An- Dtrench = 0.5 lm Dtrench = 0.1 lm
other point in the Dtrench = 0.1 lm case is the reduction with s.s. w.o. s.s. with s.s. w.o. s.s.
of the FBSOA when comparing with Dtrench = 0.5 lm,
Vth (V)
as shown in Fig. 4. The impact ionization process is 1.56 1.56 1.09 1.09
accelerated by the higher current density thus giving
S (mV/dec)
for a restricted FBSOA. The maximum impact ioniza-
144 144 78 78
tion region at breakdown is located below the midpoint
of the space between the accumulation regions. Vbr (V)
32 20.5 31.5 17.4
Concerning the quasi-saturation regime, the IdVd
2
16
curve for Dtrench = 0.1 lm at Vg = 4 V shows a strong Ileakage (A/lm · 10 ) at Vbr/2
6 – 4.3 –
quasi-saturation in comparison to their 0.5 lm counter-
 J. Roig et al. / Solid-State Electronics 49 (2005) 965–975 971

ever, the Ileakage value is increased when using the ‘‘w.o. 5. Reliability analysis
s.s.’’ structure because of the bipolar activation. In such
a case, the leakage current substantially increases due to 5.1. Self-heating effect
the bipolar transistor gain in both Dtrench = 0.1 and
0.5 lm. Thermal management study at device level has been
scarcely done in trench power MOSFET structures.
Hence, in this section physical insight into the heat gen-
4. Capacitance analysis eration and heat flow mechanisms is provided by numer-
ical simulations to qualitatively analyse the scaling
Small-signal numerical simulations have been used to influence. The same device structure as in the previous
extract the gate-to-drain (Crss), source-to-gate (Ciss) and sections has been used.
source-to-drain (Coss) capacitance values. The different It is worth to remark that, differently from other
capacitance curves as a function of the drain voltage DMOS structures, such as VDMOS [26] and LDMOS
at Vg = 0 V and frequency of 1 MHz are plotted in [27], the trench power MOSFET structure does not
Fig. 5 for the ‘‘with s.s.’’ cases. An important reduction show current crowding owing to the JFET action in
of all the capacitance values is observed when reducing the drift region. In fact, hot spots are found between lat-
the Dtrench value. The Crss capacitance, which is crucial eral depletion regions when this effect is present. As a
to improve the device performance at high frequency consequence, the highest heat generation and maximum
operation, is reduced by 30% approximately when temperature is always placed at the channel region in
reducing Dtrench to 0.1 lm. This is due to the smaller conduction mode (see Fig. 6a and c).
depletion volume in the drift region and, as a result, Regarding the heat generation (see Figs. 6a and 7), an
smaller depletion charge. In some cases, the depletion anomalous behaviour in the heat generation profiles is
charge represents the 45% of the total charge in Crss observed in the Dtrench = 0.1 lm case. The typical heat
[5]. The charge contributions coming from inversion generation in a MOSFET channel normally exhibits a
and accumulation layers are expected not to be signifi- peak in the region where the channel is strangulated
cantly modified at Vg > Vth since the drift and body dop- due to the higher current density. This behaviour can
ing concentrations and the gate length remain equal. be clearly observed in Dtrench = 0.5 lm heat generation
Moreover, a 67% reduction is obtained in the Ciss value curves from Fig. 7. However, the shrinkage of Dtrench
while Coss is reduced three orders of magnitude. The rea- produces the increment of the current density at the
son for the Ciss reduction is similar than in Crss case source contact, thus translating the heat generation peak
when considering the depletion charge in the source- at the source side of the channel region.
body junction. Note that Ciss and Crss are influenced In order to analyse the heat flow in trench power
when shortening the source and drain lengths, respec- MOSFET structure, a very thin heat source (almost
tively, while the gate remains identical. The huge
decrease in the Coss value is due to the reduction of both
source and drain lengths otherwise. In this case, the
reduction of all depletion charge contributions is
important.

Fig. 6. Heat generation distribution (a), heat flow paths scheme

Fig. 5. Ciss, Crss and Coss vs. drain voltage for Dtrench = 0.1 and 0.5 lm. (b) and temperature distribution (c) in a trench power MOSFET.
972 J. Roig et al. / Solid-State Electronics 49 (2005) 965–975

heat spreading. Although Rth-substrate2 depends on

the substrate thickness and on the dimensions of
the die and the active region, its value is fixed to
1 · 10
3 Kcm2/W in the performed simulations. This
value is reasonable when regarding the following con-
siderations: a 1D case without spreading effect is
reached when the active region extends through all
the die surface (unrealistic case); in the 1D case the
value for Rth-substrate2 is in the order of 10
2Kcm2/
W for silicon substrate thickness ranging between
200 and 500 lm; there is always a peripheral region
(including the termination surface) which leads to
the heat spreading and the consequent lowering in
Rth-substrate2.

Fig. 7. Temperature increment and Heat Generation distributions in With the defined boundary conditions, electro-ther-
Dtrench = 0.5 and 0.1 lm. The biasing conditions are Vg = 3 V mal simulations have been carried out in steady-state
(Dtrench = 0.1 lm), Vg = 3 and 4 V (Dtrench = 0.5 lm) and Vd = 12 V conditions. The obtained temperature profiles perpendic-
in both cases.
ular to the surface are plotted in Fig. 7. Although the heat
generation is smaller in the Dtrench = 0.1 lm case, a higher
temperature is obtained in comparison with the Dtrench =
planar) attached to the gate oxide is considered in the 0.5 lm case. The maximum temperature increments are
channel region. Although a non-uniform heat distribu- 170 and 246 K for Dtrench = 0.5 lm (Vg = 4 V) and
tion in the channel has been discussed before, a uniform Dtrench = 0.1 lm (Vg = 3 V), respectively. The tempera-
heat source is now considered only for illustrative pur- ture peak as well as the maximum heat generation point
poses. The main heat flow paths and the thermal resis- is placed at the channel region in all the cases. Although
tances of a trench power MOSFET structure, drawn in temperature decay towards the bulk substrate bottom is
Fig. 6b, are defined as follows: observed, the variation of the temperature in the direc-
tion parallel to the surface is almost inexistent, as inferred
• Heat flow path 1: the heat flows towards the from Fig. 6c.
source electrode which is set to the room temperature The heat removal through the heat flow paths is
(300 K) through the electrode thermal resistance of paramount importance to determine the reason
(Rth-electrode). The Rth-electrode value depends on the for the temperature increment in the channel region.
type, thickness and layout of the metal layers. In this sense, the Ltrench reduction basically alters the
According to the literature [28], Rth-electrode = 5 · 10
3 Rth-substrate1 value while the Dtrench reduction influ-
Kcm2/W is a reasonable value. Before reaching to ences both Rth-substrate1 and Rth-body values. It is also
reach the Rth-electrode, the heat flows through Rth-body true that the importance of Rth-substrate1 and Rth-body
which represents the thermal resistance of the body is related to the magnitude of Rth-substrate2 and
region. Rth-electrode, respectively. Hence, Dtrench reduction
• Heat flow path 2: the heat flows towards, the drain can substantially degrade the device thermal perfor-
electrode which is directly set to the room tempera- mance in the case of low Rth-electrode and high
ture; i.e. ideal cooling conditions at bottom substrate. Rth-substrate2 values. In other words, the heat flow path
Hence, the heat flow has to flow through Rth-substrate1 1 is less important when the distance between trenches
and Rth-substrate2, which have been separated for the is reduced.
sake of clarity. Rth-substrate1 is defined as the thermal The electro-thermal coupling effect, which reduces the
resistance corresponding to the substrate part (below electron mobility, can be observed in Fig. 8 from the
the trench bottom) where the heat coming from a IdVd curves corresponding to the Dtrench = 0.1 and
single basic cell is allowed to spread. Differently, 0.5 lm cases. The comparison between the IdVd curves
Rth-substrate2 is the thermal resistance accounting for with and without self-heating effect (SHE) shows a
the part of the substrate where the heat coming from 42% saturation current reduction in the Dtrench = 0.1 lm
the whole active area is spread. As Rth-substrate1 is case at Vd = 12 V, while the decrement in Dtrench =
extended to few microns, it can be easily analysed 0.5 lm is about 29%. These values have been obtained
by 2D numerical simulation considering a striped lay- for a similar dissipated power. In Fig. 8 it is also shown
out configuration. On the other hand, the silicon that the thermal resistance of a single trench power
material included in Rth-substrate2 corresponds to the MOSFET basic cell (Rth = DT/2 · (Id · Vd)) is doubled
main part of the substrate and accounts for the 3D when reducing Dtrench from 0.5 to 0.1 lm.
 J. Roig et al. / Solid-State Electronics 49 (2005) 965–975 973

Fig. 8. Drain current (with and without self-heating effect) and Fig. 9. Vertical distribution of interface traps density and normal
thermal resistance vs. drain voltage for Dtrench = 0.5 and 0.1 lm. electric field at the gate. The biasing conditions are Vg = 3 V
(Dtrench = 0.1 lm), Vg = 3 and 4 V (Dtrench = 0.5 lm) and Vd = 12 V
in both cases.

5.2. Hot-carrier effect

Like in conventional VDMOS and LDMOS transis-

tors, the hot carrier effect is also an important issue in
trench power MOSFETs with regard to the long time
reliability [11]. As a matter of fact, two degradation
mechanisms in general DMOS structures due to the cur-
rent flowing at Si/SiO2 interface have been previously
reported [29]. One of the degradation mechanisms,
which reduces the electron mobility, takes place in the
channel region while the other one, which produces
hot-hole trapping, occurs in the accumulation region.
In this section, the importance of these mechanisms in
trench power MOSFETs is analysed by means of
numerical simulations. The Power Law and Kinetic
Equation models are included in the device simulation
software, using the experimental fitting parameters
extracted from [30]. Following the data provided from
[29], the traps have been defined as neutral and their Fig. 10. Percentage reduction of Id_sat. The biasing conditions are
Vg = 3 V (Dtrench = 0.1 lm), Vg = 3 and 4 V (Dtrench = 0.5 lm) and
initial concentration value is 1 · 109 cm
2. Vd = 12 V in both cases.
After stressing the trench power MOSFETs at
Vd = 12 V and Vg = 3 and 4 V during 1 · 105 s, the
resulting trap density generation profiles at Si/SiO2
interface are shown in Fig. 9. There is a correlation be- hot-carrier immunity as it has already been demon-
tween the trap density distribution and the electric field strated in DG MOSFETs [10]. This phenomenon is basi-
normal to the Si/SiO2 interface. However, the difference cally due to the more straight potential lines, from gate
between the normal electric field curves is more accentu- to gate, at the drain side when the body width is reduced.
ated than that obtained in the interface trap density As stated before, the trap generation reduces the elec-
ones. This is due to the influence of many other para- tron mobility thus giving for lower Id_sat values. The per-
meters in the heat trap generation as longitudinal elec- centage of Id_sat degradation with time is shown in Fig.
tric field and current density. Hence, the interface trap 10 for the cases discussed in Fig. 9. An identical percent-
density profiles are similar in all the cases, with an aver- age reduction of Id_sat for Dtrench = 0.5 and 0.1 lm at
age value in the range of 9 · 109 cm
2 after the stress. In Vg = 4 and 3 V, respectively, has been achieved (about
all the analyzed cases, the trap density in the accumula- 0.5 at 1 · 105 s). Both trench MOSFET structures with
tion region is completely absent as in conventional similar Id_sat degradation exhibit identical current
VDMOS transistors [29]. It is worth to mention that density values and trap density distributions in the
further reduction on Dtrench is believed to improve the channel region. The percentage reduction of Id_sat for
974 J. Roig et al. / Solid-State Electronics 49 (2005) 965–975

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