EXPERIMENT #3

HIGH LEVEL PROGRAMMING AND SYSTEM MEMORY EXPANSION

3.1 OBJECTIVE
The purpose of this experiment is getting familiar with high level microcontroller programming
using C, basic memory operations, tri-state buffers, and memory expansion in an AVR ATMega128
based system.

3.2 PRELIMINARY WORK

3.2.1 Read through Section 3.3 to obtain background information on tri-state buffers, and memories.
3.2.2 You may download a free version of the mikroC Pro for AVR for compiling your C programs:
http://www.mikroe.com/mikroc/avr/.
3.2.3 Find information about following types of random access memories, define them in 1 or 2
sentences, and comment on their application area. Stress distinctive features.
a. SRAM
b. DRAM
c. SDRAM
d. DDR SDRAM
Review the HY6116 RAM (Or equaly LH5116H) specifications provided in the Appendix (better
to download complete datasheet from METUClass). What type of RAM (pick from a-d) is
HY6116 (LH5116H)? Explain.
3.2.4 Propose a method to design a 4Kx8 bit memory system by using 1Kx4 bit memory chips (e.g.
2114 is a 1Kx4 bit memory chip). The address bus width is 16 bits. Sketch the connectivity of
the chips in a block diagram to illustrate the system.
3.2.5 Design decoding logic with NAND gates and inverters given in the part list that will select a
memory chip of 8K x 1-byte words if the starting address for the chip is D000. Address bus
width is 16-bits. Show your logic design by sketching.
3.2.6 Read through section External Memory Interface XMEM (P25), Alternate Functions of PortA and
External Memory devices timing requirements section in ATMega128_Datasheet. You can find it
in the lab or on METUClass. Study the example “Using all 64Kbytes Locations of External
Memory” in detail which is located at page 34 of the datasheet.

3.2.7 Write an AVR assembly program subroutine in assembly, which fills the external 6116 2K-
memory block with constant values, such as 0x55. Write another subroutine to read the full
content of the external memory 6116 and send each read value along with its memory address
to the external LEDs (similar to the ones on UNI-DS6) on one of the ports with 1 s of delay
between each value. This will be used to verify the added memory chip works correctly. Your
program should be written in a user-friendly style, e.g. the written value of 0x55 should be easily
modified through a constant declaration.
i. The assembly code and the Proteus project should be included into the .zip file you
will submit electronically. You should also bring these files with you to the lab.
ii. If you were to make a measurement on one of the microcontroller pins to validate the 1
second delay you coded into your program, which pin would be appropriate to monitor on
the oscilloscope? Explain.
 
3.2.8 The Fibonacci number sequence is defined by the following recurrence:

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That is, each Fibonacci number is the sum of the two preceding numbers, excluding initial two
numbers, which are constant.
Write a program in C that reads an 8-bit number n using a DIP switch pack (8-bit input) on UNI-
DS6 board, computes, then stores each Fibonacci number up to number n, to the external 6116
2KB memory block, starting with the first address. Your program should be able to handle 16-bit
unsigned numbers. Other requirements are:
 Your program should compute the Fibonacci sequence; lookup tables are not allowed in any
part of the solution.
 The main Fibonacci computation (of calculating the next number based on the previous two)
should be done in a recursive subroutine.
 The initially entered number n cannot be less than 1. Your program should check this
condition.
 After all numbers are stored to the memory the computed Fibonacci numbers should be
read from the memory, and displayed on the LCD display in pairs of numbers with a space
in between. There should be about 2 seconds of delay between the display of each pair. For
example, for n=3, the numbers are displayed in the following sequence in about 8 seconds:
01
11
12
23
 A warning message should appear on the LCD display if either of the two final numbers
required more than 16 bits.
You should submit a pseudocode or flowchart to illustrate the planning of your program.
3.2.9 Use the C compiler to generate and inspect the AVR assembly code corresponding to your C
program in 3.2.8. Are there any portions of the compiler generated code you could optimize for
performance and/or program memory savings? Indicate how you would modify the
assembly code, and explain any optimizations.

3.3 BACKGROUND INFORMATION

3.3.1 Three State (Tri-state) Outputs

The output stages of devices with tri-state outputs provide three output conditions. Two are
identical to those of standard TTL, and one of those two conditions exists whenever the device is
enabled; a logic 1 or logic 0 with a low impedance output. The third state, a high impedance output
exists when the device is not enabled. The high impedance state makes the output function as if it is
not electrically connected to any other device to which it is actually physically connected. If several tri-
state outputs are connected, all but one must be disabled; only the enabled output determines the logic
level of the connection. If the outputs of two tri-state devices are enabled simultaneously the
devices are subject to damage.
Tri-state outputs allow multiplexing of several outputs without the use of multiplexer ICs or pull
up resistors. The logic symbol for a tristate output buffer is shown in Figure 3.1. This device is enabled
with logic 1 at the enable input. The output of this device is the complement of its input. This is one of
four possible variations of enable levels and output levels. The logic symbols for all four possible
variations of a tri-state output buffer are shown in Figure 3.2. Many logic devices are designed with tri-
state outputs so that they can be multiplexed easily to a bus. For devices, which do not have tri-state
outputs, separate tristate buffer ICs between the output of the device and the bus carry out the same
function.

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 Figure 3.1. Logic schematic showing connection of tri-state outputs

Figure 3.2. Different variations of tri-state buffers: (a) Non-inverting buffer with active high enable,
(b) Non-inverting buffer with active low enable, (c) Inverting buffer with active high enable, (d) Inverting
buffer with active low enable.

Example: Suppose we want to design a 4x1 multiplexer using a 2x4 decoder and a tri-state buffer. The
logic table of the multiplexer is shown below.
E S1 S0 OUT
0 X X High-Z
1 0 0 I0
1 0 1 I1
1 1 0 I2
1 1 1 I3

Figure 3.3 shows the 4x1 multiplexer designed using decoder and tri-state buffers. Using the
below design, you can multiplex 4 input devices without tri-state outputs into a tristate bus.

Figure 3.3. A multiplexer designed using decoders and tri-state buffers.

3.3.2 Memories
Several equal length registers can be incorporated in a single IC and share a common set of
inputs, a common set of output, and a single clock line as shown in Figure 3.4. Each register occupies
a distinct location, which has a unique numerical address. Thus, a memory can be thought as a
collection of addressable registers. A conceptual representation of the memory in Figure 3.4 for n=3
and m=4 is shown in Table 3.1.

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 Figure 3.4. Register representation of a memory.

Table 3.1. Conceptual representation of memory (for n=3 and m=4)

3.3.3 Semiconductor RAM Device Organization

Semiconductor RAM devices are available with a limited number of bits of storage. In general a
single memory device may not be sufficient and hence, the requirements of the application for word
length and total number of words may necessitate the interconnection of several memory devices and
additional logic circuits to form a memory system.
Semiconductor memory devices are designed so that a single device meets all the functional
requirements of a memory system. To do so a device contains:
1. An array of memory cells each of which can store a single bit.
2. Logic to address any location in the memory.
3. Circuitry to allow the reading of the contents of any memory location.
4. For writable memories, circuitry to allow any memory location to be written.
Memory devices contain input devices, output buffers, and circuitry for address expansion for
easy interconnection with other memory devices or logic circuits.
Semiconductor memories are internally organized in several ways in an effort to obtain a
memory with high speed, a large bit capacity, and low peripheral circuitry and memory array cost.
A semiconductor memory can be thought as a bit matrix. For example a 2048x8-bit memory can
be thought as a matrix having 2048 rows and 8 columns. However, this is the logical organization of

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the memory. The physical organization may be different from the logical one. To make it clear let us
define the following abbreviations:
NL=Number of Logical Words
NP=Number of Physical Words
WL=Number of Bits in a Logical Word
WP=Number of Bits in a Physical Word
It is obvious that NLWL=NPWP=Number of bits in the memory.
Conceptually, the simplest organization is a word organized array with linear selection. In
such an organization NL=NP=N and WL=WP=W. The memory is designed as an NxW bit matrix as
shown in Figure 3.5(a). Word selection requires a 1-out-of N decoder. All address inputs are connected
to the select inputs of the row decoder. When an address is applied, only one of the outputs of the
decoder is active, selecting the corresponding word in the memory.
Although conceptually simple, the linear selection method requires a large decoder for large
number of words, which is very costly in chip area. For memories with small number of words, this
organization is acceptable and has advantage of a short access time.
Address decoder size is substantially reduced by organizing the memory matrix and the word
selection logic to allow two-level decoding.
In a memory utilizing two-level decoding, one level corresponds to a physical word and one to
a logical word.
A physical word consists of the number of bits in a row of the memory matrix. A logical word
consists of the number of bits of a physical word which are sensed and gated to the output at one time.
Two-level decoding requires two circuits: A row decoder which selects a physical word and a column
multiplexer which selects one logical word from the selected physical word.
A physical word is divided into S=WP/WL segments (logical words). The row decoder is a 1-out-
of NP decoder and the column multiplexer consists of WL 1-out-of S multiplexers.
The block diagram of a 2048x8 bit ROM organized for two level decoding is shown in Figure 3.5
(b). The memory array is 128x128 bits which means NP=128 and WP=128. Each physical word consists
of WP/WL=128/8=16 logical words. In the first level decoding a physical word is selected using a 7x128
decoder. Address lines A0-6 are used for that selection. In the second level, an 8-bit wide logical word
selected from a 128-bit wide physical word. This is accomplished by using eight 16x1 multiplexers, one
multiplexer for each bit in the logical word. For this selection, address bits A7 to A10 are used.

As observed, the bit organized memory results in a square memory matrix and row and column
decoders of equal complexity. Each row and column decoders decodes n/2 address bits, resulting in a
simplification of decoder required.

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Figure 3.5. 2048x8 ROM (a) using linear selection, (b) with 128x128 memory array using two level
decoding (e.g. 6116)

3.3.4 Memory Device Timings

To ensure proper operation there are timing constraints on the sequencing of address, data,
and control signals of a memory. Read and Write diagrams of a typical RAM are given in Figure 3.6.
The basic sequence of operations for writing to or reading a random access type memory is as follows:
1. An address is applied to the address inputs of the memory.
2. The chip is selected by application of proper logic level(s) at its chip select input(s).
3. Data to be written into the memory is applied at the data inputs for the write cycle. Then the
R/W line is pulsed low.
4. For the read cycle, the R/W line is pulsed high and then the contents of the selected memory
location appear at the data outputs of the memory after a period of time equal to its access
time.
5. The address and chip enable signals can then be changed to select another memory
location.

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Figure 3.6. (a) WRITE timing diagram for a R/W memory and (b) READ timing diagram for a R/W
memory.

3.3.5 Increasing the Vertical and Horizontal Capacity

The memory requirements of a typical microprocessor system frequently cannot be met with a
single memory device. Several memory devices must then be interconnected to form a memory
system.
In a memory system capacity can be expanded by increasing the number of words and/or
increasing the word length above that attainable from a single memory device.
Word length is increased by placing the outputs of two or more memory devices in parallel.
Example:
8 1024x1 bit read-write memories (RAM) are arranged in parallel to make 1024x8 bit (1K byte)
memory system.

Figure 3.7. 8 1024x1 bit read-write memories (RAM) are arranged in parallel to make 1024x8 bit (1K
byte) memory system.
Observe that the box with dashed lines may be thought as if it is a single chip 1K byte RAM.
Multiplexing outputs from two or more memory devices as shown in Figure 1.8 increases the
number of words in a memory system.

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 Figure 3.8. Multiplexing outputs from two or more memory devices to increase word count

Observe that if above chips are RAMs, and then one should implement bi-directional multiplexer
with tri-state capability, which apparently increases the complexity of the circuitry. Since the memory
chips are provided with chip select or chip enable type inputs and tri-state outputs, we can implement
the same memory system with a decoder as shown in Figure 3.9.

Figure 3.9. Same memory system implemented with a decoder.

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3.3.6 Address Space Organization of AtMega128
It is possible to use an optional external data SRAM with the ATmega128. This SRAM will occupy
an area in the remaining address locations in the 64K address space. This area starts at the address
following the internal SRAM. The Register file, I/O, Extended I/O and Internal SRAM occupies the
lowest 4352 bytes in normal mode so when using 64Kbyte (65536 bytes) of External Memory, 61184
bytes of External Memory are available.
Accessing external SRAM takes one additional clock cycle per byte compared to access of the
internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD, PUSH, and POP take
one additional clock cycle. One should be aware that this will increase the number of clock cycles
required to execute the program that needs to access to SRAM.

Figure 3.10. External SRAM connected to the AVR

Consider the problem of physically assigning a 6116 memory to a 2K block in the

microcontroller address space. The proper chip select signal for the 6116 needs to be generated so
that the MCU can correctly access the chosen 2K block. In order to use external SRAM, one should
activate the XMEM interface of the AVR processor and configure it according to the SRAM’s
specifications. When XMEM mode is activated, XMEM interface will override the setting in the data
direction registers which are dedicated to the XMEM interface.

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 Figure 3.11. AVR Memory Configuration modes.

ATmega128 has two memory configuration modes, which are shown in Figure 3.11. Memory
Configuration mode A is the non-ATmega103 compatibility mode. ATmega103 compatibility mode is
the Configuration mode B shown in the figure above.

3.3.7 External Memory Timing

External Memory devices have different timing requirements. To meet these requirements,
ATmega128 XMEM interface provides four different wait-states as shown below.

Table 3.2. Wait States.

SRWn1 SRWn0 Wait States

0 0 No wait-states
Wait one cycle during read/write
0 1
strobe
Wait two cycles during read/write
1 0
strobe
Wait two cycles during read/write
1 1 and wait one cycle before driving
out new address

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3.4 MCU I/O PORT CONNECTOR – Port A
The interconnection with AtMega128 microcontroller is accomplished via the pinhead I/O Port
Connector located on the development board. The connection between the development board and the
external prototype board is made using bit to bit wiring.

Figure 3.12. The MCU I/O Port Connector

3.5 EXPERIMENTAL WORK

3.5.1 Setup 1:
Construct your set-up from prework Section 3.2.7 using an external breadboard for interfacing
the external memory. Check the operation of your circuit by writing and reading data, and
observing the LEDs on UNI-DS6.
i. Demonstrate the functionality of your system to the lab instructor. How do the results
compare your simulations in Proteus?
ii. Make a measurement on an appropriate signal using the oscilloscope to verify your
programmed time delay between displaying different memory word contents on LEDs. Does
your measurement match the expectation? Show and explain any discrepancies to
your lab instructor. 

3.5.2 Setup 2:
Construct your designed system in 3.2.8 again using the external memory. Debug and verify
your system correctness. Then demonstrate to your lab instructor.

Note: If you cannot get any part of your systems to fully function, you are expected to take initiative to
debug, and demonstrate to your lab instructor which parts work and which parts do not. For example, if
you cannot communicate with the memory, you should find ways to demonstrate that the code works
correctly (signals at the memory interface are correct). Similarly, if you cannot write to the LCD, can you

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demonstrate your output through another means? Any debug success in rootcausing your problems will
return to you as partial credit.

3.6 PARTS LIST

1x 6116 2KB RAM (Or alternative LH5116H-10)
1 x 74HC373 Octal Latch (Or alternative DM74LS373)
Oscilloscope

REFERENCES:
 8-Bit Microcontroller AtMega128 Datasheet.

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APPENDIX: (Please Refere to METUClass and download complete data sheet of the elements if you need more detail)

DM74LS373N (D latch) 

 
 

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M74HC373B1 (D latch) 

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HY6116 (SRAM) 

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LH5116H‐10  (SRAM) 

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