8086 Microprocessor: Lec. 4: 8086 Pin Description Omar Zyad

8086
Microprocessor
LEC. 4: 8086 PIN DESCRIPTION
OMAR ZYAD
8086 PIN DESCRIPTION
Intel 8086 is a 16-bit HMOS microprocessor. It is available in 40 pin DIP
chip.
It uses a 5V d.c. supply for its operation.
The 8086 uses 20-line address bus.
It uses a 16-line data bus. The 20 lines of the address bus operate in
multiplexed mode.
The 16-low order address bus lines are multiplexed with data and 4
high-order address bus lines are multiplexed with status signals.
AD0-AD15 (Bidirectional) :
◦ Address/Data bus.
◦ These are low order address bus.
◦ They are multiplexed with data.
◦ When AD lines are used to transmit memory address the symbol A is used
instead of AD, for example A0-A15.
◦ When data are transmitted over AD lines the symbol D is used in place of AD,
for example D0-D7, D8-D15 or D0-D15.
A16-A19 (Output) :
◦ High order address bus. These are multiplexed with status signals.
BHE (Active Low)/S7 (Output) :
◦ Bus High Enable/Status.
◦ Pin 34
◦ It is used to indicate the transfer of data using data bus D8-D15.
◦ This is signal is low during the first cycle thereafter it is low.
RD
◦ Pin 32
◦ Read strobe indicates that the processor is performing a memory or I/O read
cycle.
READY
◦ Pin 22
◦ It is the acknowledgement from the addressed memory or I/O device that it
will complete the data transfer.
◦ It is an active high.
◦ It indicates that the device is ready to transfer data.
◦ When it is low, it indicates wait state.
RESET
◦ Pin 21
◦ It causes the processor to immediately terminate its present activity.
◦ The signal must be active HIGH for at least four clock cycles.
INTR
◦ Pin 18
◦ It is an interrupt request signal.
◦ Which is sampled during the last clock cycle of each instruction to determine
if the processor considered this as interrupt or not.
NMI
◦ Pin 17
◦ Non maskable interrupt
◦ This is an edge triggered input which results an interrupt request to the
microprocessor.
INTA
◦ Interrupt Acknowledge
◦ It is used as a read strobe for interrupt acknowledge cycles.
◦ Pin 24
TEST
◦ Pin 23
◦ If the TEST pin goes low(0), execution will continue, else the processor
remains in an idle state.
MN/MX’
◦ Minimum/Maximum. This pin signal indicates what mode the processor will
operate in.
◦ Pin 33
ALE
◦ Pin 25
◦ Address enable latch
◦ ALE is provided by the processor to latch the address into address latch.
◦ It is indicates the availability of a valid address on the address/data lines.
WR
◦ Pin 29
◦ Write: indicates that the processor is performing a write memory or write
I/O cycle
DEN
◦ Pin 26
◦ Data Enable
◦ It is used to enable Transreceiver 8286.
◦ The transreceiver is a device which is used to separate data from the
address/data bus.
DT/R
◦ It stands for Data Transmit/Receive signal
◦ Pin 27.
◦ It decides flow of data direction through the transreceiver. When it is high,
data is transmitted out and vice-a-versa.
M/IO
◦ This signal is used to differentiate between memory and I/O operations.
◦ When it is high, it indicates I/O operation and when it is low indicates the
memory operation.
◦ It is available at pin 28.
HLDA
◦ It stands for Hold Acknowledgement signal and is available at pin 30.
◦ This signal acknowledges the HOLD signal.
HOLD
◦ This signal gives hints to the processor that external devices are requesting
to access the address/data buses.
◦ It is available at pin 31.
S0, S1, S2
◦ These are the status signals that provide the status of operation, which is
used by the Bus Controller to produce memory & I/O control signals.
◦ These are available at pin 26, 27, and 28. Following is the table showing their
status
S2 S1 S0 Status
0 0 0 Interrupt
acknowledgement
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive
LOCK
◦ When it is active, it indicates to the other processor not ask the CPU to leave
the system bus.
◦ Pin 29
RQ/GT1 and RQ/GT0

◦ These are the Request/Grant signals used by the other processor requesting
the CPU to release the system bus.
◦ When the signal is received by the CPU, then it sends acknowledgment.
◦ RQ/GT0 higher priority than RQ/GT1.
CLK
◦ CLOCK: provides the basic timing for the processor and bus controller.
◦ It is asymmetric with a 33% duty cycle to provide optimized internal timing.
◦ Pin 19
VCC
◦ 5V power supply
◦ Pin 40
GND
◦ GROUND
◦ Pin 1,20

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RQ/GT1 and RQ/GT0

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