UVMF One Bite at a Time
UVM Framework Overview
Verification Academy Course
Bob Oden
UVM Field Specialist
Objectives & Results
Objectives
UVM Framework overview
Provide context for the remaining videos
Results
Understand the UVM Framework
— What it is
— What it provides
— It’s architecture
— Documentation available
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Agenda
Motivation for UVMF
What is the UVMF
Characteristics and use of UVMF
Technologies integrated into UVMF
Collaborative plan for adopting SV/UVM using UVMF
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Typical UVM Learning/Productivity Curve
A lot must be learned
Before a production
environment is operational
Learning Curve
Productivity Curve
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UVM Learning/Productivity Curve w/UVMF
A production environment
is in place
That is learned
while in use
Learning Curve
Productivity Curve
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What is the UVM Framework
UVM Code Generator
— Interface, environment, testbench
UVM Jumpstart
— Extensions of UVM to hide UVM details
— Avoid common mistakes at all levels
UVM Reuse methodology
— Horizontal reuse of components across projects
— Vertical reuse of environments from block to top
— Platform reuse from simulation to emulation
— Allows team to focus on verifying product
features
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UVMF Users Guide
UVMF Users Guide Table of Contents
1 Introduction to the UVM Framework (UVMF) 7
2 UVM Framework Examples 30
3 Makefiles 54
4 Using the Python Templates 55
5 Developing an Interface Package using the Python Templates 56
6 Developing an Environment Package using the Python Templates 62
7 Developing a Project Bench using the Python Templates 68
8 Using the Questa VIP Configurator in tandem with UVMF code generators 73
9 Resource Sharing within UVM Framework 84
10 Environment and Interface Initialization within the UVM Framework 89
11 Enabling Transaction Viewing within the UVM Framework 95
12 Creating the Top Level Modules 97
13 Creating Test Scenarios 99
14 Adding agents to an existing UVMF bench and environment 102
15 Making a non-UVMF Interface VIP Compatible with UVMF 106
16 Appendix A: UVM classes used within UVMF 108
17 Appendix B: UVMF Base Package Block Diagrams 109
$UVMF_HOME/docs/UVM_Framework_Users_Guide.pdf
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UVMF Code Generator YAML Reference
1 Introduction to the UVM Framework (UVMF) Code Generators 4
1.1 Overview 4
1.2 Generation flow 5
1.3 YAML Overview 6
2 Interface YAML Structure 7
3 Utility Component YAML Structure 12
3.1 Description 12
3.2 YAML Format 12
4 Environment YAML Structure 13
4.1 Description 13
4.2 YAML Format 13
5 Test Bench YAML Structure 19
5.1 Description 19
5.2 YAML Format 19
$UVMF_HOME/docs/UVM_Framework_Code_Generator_YAML_Reference.pdf
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UVM Framework Reuse Structure
Testbench Complete Home: DUT Specific Bench and Stimulus
Completed Rooms: Interface and Environment
Reusable IP Packages
Pre-Fabricated Rooms: UVM Use Model and
UVM Framework Reuse Methodology
UVM Building Supplies: Common Verification
Building Blocks
SystemVerilog Raw Materials: Abstract Programming
Language
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Key Characteristics of the UVMF
Accelerate environment development
— Better environments in less time
Reusable
— Across projects, sites, simulation levels
Scalable
— Across design size, complexity, and
target technology
Emulatable
— Same environment and stimulus
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UVMF’s proven track record
Deployed on production designs at over thirty companies
— Across projects within companies
— Across sites within companies
— One SOC project spanned multiple companies
— Used in many industries
— Used on FPGA and ASIC
— Used for Verilog/SV and VHDL designs
— Used by UVM experts and novices
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Technology Integrated into UVMF
Verification IP – QVIP Configurator
— GUI based QVIP configuration and UVMF environment generation
Graph based testing – Accelerated coverage closure
— inFact testbench import to create protocol sequences
Verification Management
— Coverage ranking, merging, reporting
Verification Run Manager
— Automated regression management
Vista
— SystemC model of ALU example
Visualizer
— Generates visualizer database
Veloce
— TB structure is emulation compliant
Catapult HLS
— Generates UVMF bench for verifying generated RTL
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UVMF – Environment Architecture
hdl_top test_top extends uvmf_test_base extends uvm_test
(module)
config (uvm_object) Env (uvm_env)
scoreboard predictor
spi_if() DUT_config
Spi_driver_bfm_if() DUT_Register_Model
Env Coverage
Spi_monitor_bfm_if() spi_agent_config
wb_agent_config spi_agent wb_agent
DUT() Cov M
virtual spi_if virtual wb_if
M Cov
initial begin SQR D D SQR
uvm_config_db::set
end
top_level_sequence
hvl_top (uvm_sequence) spi_slave_seq dut_config_seq wb_master_seq dut_stats_seq
(module)
initial run_test()
Legend
Env level reuse
Comp level reuse
Not reusable Restricted © 2018 Mentor Graphics Corporation
Block to Top Environment Reuse
hdl_top test_top extends uvmf_test_base extends uvm_test
(module)
Ahb2spi_config Ahb2spi_env (uvm_env)
spi_if() (uvm_object)
Spi_driver_bfm_if()
Ahb2wb_env Wb2spi_env
DUT_config
Spi_monitor_bfm_if()
DUT_Register_Model
DUT() Ahb2wb_config
initial begin Wb2spi_config
uvm_config_db::set
end
top_level_sequence
hvl_top (uvm_sequence) spi_slave_seq dut_config_seq ahb_master_seq dut_stats_seq
(module)
initial run_test()
Legend
Env level reuse
Comp level reuse
Not reusable Restricted © 2018 Mentor Graphics Corporation
UVM Framework in Veloce
dut_top test_top extends test_base extends uvm_test
(module)
config (uvm_object) Env (uvm_env)
spi_if()
DUT_config scoreboard predictor
Spi_driver_bfm_if()
DUT_Register_Model
Spi_monitor_bfm_if()
spi_agent_config
spi_agent wb_agent
wb_agent_config
virtual spi_if virtual wb_if
DUT ()
tb_top
(module)
Initial begin
run_test()
end
top_level_sequence
(uvm_sequence)
spi_slave_seq dut_config_seq
wb_master_seq dut_stats_seq
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UVM Framework in Veloce
dut_top test_top extends test_base extends uvm_test
(module)
cnfig (uvm_object) Env (uvm_env)
spi_if()
DUT_config
Spi_driver_bfm_if()
Spi_monitor_bfm_if()
DUT ()
tb_top
(module)
Initial begin
run_test()
end
top_level_sequence
(uvm_sequence)
spi_slave_seq dut_config_seq
wb_master_seq dut_stats_seq
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UVM Framework Directory Structure
UVMF_PROJECT_DIR UVMF_HOME – Points to UVMF installation
/project_benches
/wb2spi hdl_top
(module)
test_top extends test_base extends uvm_test
/doc cnfig (uvm_object) Env (uvm_env)
/sim DUT_config scoreboard predictor
/tb
spi_if()
/testbench Spi_driver_bf
m_if()
DUT_Register_M
odel
/sequences Spi_monitor_b
spi_agent_config
/tests
fm_if()
spi_agent wb_agent
wb_agent_config
virtual spi_if virtual wb_if
()
UVMF_VIP_LIBRARY_HOME
DUT
/verification_ip hvl_top
(module)
/Interface_packages Initial begin
run_test()
/spi_pkg
end
top_level_sequence
(uvm_sequence)
/wb_pkg spi_slave_seq dut_config_seq
wb_master_seq dut_stats_seq
/environment_packages
/ahb2wb_env_pkg
/wb2spi_env_pkg
/ahb2spi_env_pkg Restricted © 2018 Mentor Graphics Corporation
UVMF Adoption Process
Onsite UVMF overview
— Delivered by Mentor
— Couple hours
Onsite target design overview
— Delivered by customer
— Couple hours
Onsite generation of UVMF simulation bench
— Generated using UVMF code generator
— Couple hours
Add design specific components
— Familiarize design team with simulation bench
— Protocol signaling, prediction, coverage
— Create additional test cases
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UVMF Adoption Support
Local AE support
UVM Field Specialist support
UVMF consulting available from Mentor Consulting
UVM/UVMF training available from Mentor
NCSU graduates trained in UVMF
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University Level Education
ECE792-036 “Advanced Verification with UVM”
— Teaches UVM and UVMF architecture
— Projects in Questa and Veloce
— Offered each Fall Semester
— 140 students per class
– 120 onsite
– 20 remote
— Prerequisite:
– ECE745 “ASIC Verification with SystemVerilog”
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Summary
UVM Framework
— UVM code generator
— UVM jumpstart
— UVM use model that guarantees reuse
Auto-generate UVM infrastructure
— Add protocol and design specific code
— Start creating test cases much sooner
Industry proven success
— Twelve years of collected best-practices
— Adopted across sites, business units and
companies
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www.mentor.com
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