Approaches to Digital System Design

• In Digital Devices, you learned how to create a

logic network (Flip-flops + combinational gates)
to solve a problem
– The logic network was SPECIFIC to the problem. To
solve a different problem, needed a different logic
network
• Another approach is to design a logic network that
can used to solve many different problems
– This general purpose logic network might not be as
efficient (speed, cost) as a special purpose logic
network, but hopefully can be used to solve multiple
problems!

V 0.5 1
 A Computer!!
• A Computer is a digital system whose operation
can be specified via a Program .
– Changing the program changes the computer behavior!
(solves a different problem!!!).
• A Program is simply a sequence of binary codes
that represent instructions for the computer. The
Program is stored in a Memory .
• External inputs to the Computer can also alter the
behavior the computer. The computer will have
Outputs that can be set/reset via program
instructions.
– These external inputs/output are know as the I/O
section of the computer.
V 0.5 2
 Components of any Computer System
• Control – logic that controls fetching/execution of
instructions
• Memory – area where instructions/data are stored
• Input/Output – external interaction with computer
Address bus
C
o Databus bus Memory
n
t
r
o Input/Output
l devices

V 0.5 3
 Problem Definition

Build a Digital System based upon your phone number,

assumed to be of the form Y1Y2Y3-Z1Z2Z3Z4

The Digital System will have one external input called LOC.
If LOC is true, then the system will display only the digits
Z1Z2Z3Z4.
If LOC is false, then the system will display all seven digits.

V 0.5 4
 Two Approaches for Solving this Problem
Finite State Machine
Will only work for one
number sequence

Address bus
Computer System C
o Memory
n Databus bus
Will only work for any t
number sequence, r
o
change program to l Input/Output
change sequence devices

V 0.5 5
 ASM chart for
324 8561

Odd only affects sequence in State

S* (Reset state)

Copyright Thomson/Delmar Learning 2005. All Rights

Reserved.

V 0.5 6
 FSM Implementation

One-Hot encoding: one DFF per state, requires 1 DFF per state
but simplifies combinational logic.
Binary Encoding: use minimal number of DFFs, but makes
combinational logic more complex.
V 0.5 7
 FSM Implementation (cont.)
Use one hot encoding, D-FFs for the 8 states.

DOUT[3:0]
LOC
Combinational Outputs
Logic
Circuit
7-bit 7-bit
Dffs
Present State 7 Next State
Value Q D Value
7 Clk
Logic designed for
R, S
a particular number
sequence. Reset logic, DFF
S0 set to a ‘1’ on
See textbook for combinational reset, other DFFs
logic derivation. reset to ‘0’
V 0.5 8
 FSM Operation

Copyright 2005. Thomson/Delmar Learning, All rights

Each state requires one clock cycle reserved.

V 0.5 9
Computer System Implementation
What do We Need?
Input/Output First, same as FSM
DOUT[3:0]

4
LOC

DOUT[3:0] - 4 bit output bus that has the value of the digit
LOC – 1 bit input that controls whether or not the full number
sequence is displayed V 0.5 10
Register for holding DIGIT output value
D DOUT[3:0]
4 R
E
LD G 4
R
LOC

Register loads D on rising clock edge when LD = 1.

R is an asynchronous clear.
V 0.5 11
 Memory for holding instructions
D DOUT[3:0]
4 R
E
LD G 4
R
LOC

Address[?:0] Data[?:0]
M
E
M

Memory is KxN (K locations, each location N bits wide).

Don’t know values of K, N yet.
V 0.5 12
 Register for specifying address – Use counter
D DOUT[3:0]
4 R
E
Odd
LD G 4
Program
R
Counter
Din[?:0]
Program
? c Memory
n Addr[?:0] Data[?:0]
M
LD t E
INC r M
R

Counter increments on rising clock edge when INC = 1.

Loads on rising clock edge when LD = 1. R is an
asynchronous clear.
V 0.5 13
 What Instructions do we need?
Start:
If (LOC = 1) goto local
output Y1
output Y2 Psuedo Code for
output Y3 operations
local:
output Z1
output Z2
output Z3
output Z4
goto Start

V 0.5 14
 Needed Instructions
1. Jc location Jump conditionally
If LOC = 1, then jump to location (counter
set equal to specified location).
If LOC = 0, then fetch next instruction
(counter increments by 1).
2. Jmp location Jump unconditional
Fetch next instruction from location (counter
loaded with specified location).
3. out data
load output register with data. Used for
setting the DOUT[3:0] value.

V 0.5 15
 Instruction Encoding
The binary encoding for instructions is usually divided into
different fields; with each field representing part of the
information needed by the instruction.
Our instructions require two fields: Operation Code and Data
Opcode | Data
How many bits for the Opcode? Have 3 instructions, need at
least 2 bits! (2 bits can encode 22 items)
How many bits for Data? The data field must specify the 4 bits
for the DOUT number, and also specify a memory location.
For now, lets use 4 bits for data. Instruction is 6 bits total.
I5 I4 I3 I2 I1 I0
Opcode | Data
V 0.5 16
 means
Instruction Table memory
will have
I5 I4 I3 I2 I1 I0 maximum
JMP location 00 | 4-bit location of 24 = 16
locations.
JC location 01 | 4-bit location
Each
OUT data 10 | 4-bit data location
will
Note that Opcode = 11 is unused. contain 6
The opcode assignment was chosen so that the OUT bits.
instruction could be distinguished from the two jump
instructions by only the most significant bit of the opcode.
Could have chosen another opcode assignment, but this
could make the decode logic more complex.
V 0.5 17
 A Program for 324 8561

start: JC local ; jump only if LOC input=1

OUT 3
OUT 2
OUT 4
local: OUT 8
OUT 5
OUT 6
OUT 1
JMP start

V 0.5 18
Convert Program to Binary, Put in Memory
Memory Location Machine Code Instruction
0x0 01 ???? START: JC LOCAL

0x1 10 0011 OUT 3

0x2 10 0010 OUT 2

0x3 10 0100 OUT 4

0x4 10 1000 LOCAL: OUT 8

0x5 10 0101 OUT 5

0x6 10 0110 OUT 6

0x7 10 0001 OUT 1

0x8 00 0000 JMP START

V 0.5 19
Convert Program to Binary, Put in Memory
(final)
Memory Location Machine Code Instruction
0x0 01 0100 START: JC LOCAL

0x1 10 0011 OUT 3

0x2 10 0010 OUT 2

0x3 10 0100 OUT 4

0x4 10 1000 LOCAL: OUT 8

0x5 10 0101 OUT 5

0x6 10 0110 OUT 6

0x7 10 0001 OUT 1

0x8 00 0000 JMP START

V 0.5 20
Add control Logic to Execute Instructions

16 locations
by 6 bits
wide.

Copyright Thomson/Delmar Learning 2005. All Rights Reserved.

V 0.5 21
 What is control Logic?
Control logic controls count register, out register based on Op code
value (op[1:0] = Data[5:4]).
When does out register get loaded? When OP = 10!! (OUT
instruction):
VHDL:
out_ld <= ‘1’ when ( op = “10”) else ‘0’;
When does Counter Load? When JMP instruction (OP=00) or when
JC instruction and LOC = ‘1’!!!!
pc_ld <= ‘1’ when ( op=“00” or (op = “01” and LOC=‘1’))
else ‘0’;
When does counter increment? When NOT Loading!!
pc_inc <= not (c_ld);
pc_ld, pc_inc are LD, INC inputs to counter.
out_ld is LD input to output register.
V 0.5 22
 Decode Boolean Equations

out_ld <= op(1) -- don’t really need op(0)

pc_ld <= ( (not op(1)) and (not op(0)) or

( (not op(1)) and op(0) and LOC));

pc_inc <= not (c_ld);

pc_ld, pc_inc are LD, INC inputs to counter.

out_ld is LD input to output register.
V 0.5 23
 Final Hardware

Copyright Thomson/Delmar Learning 2005. All Rights Reserved. V 0.5 24

 Timing

Observe that DOUT value does not change each clock cycle as
with FSM implementation. This is because of the extra clock
cycles needed by the JC, JMP instructions.
Copyright Thomson/Delmar Learning 2005. All Rights Reserved. V 0.5 25
 Comments
• Notice that the RESET# line forces the processor
to fetch its first instruction from location 0.
– All processors have a RESET# line like this to force the
first instruction fetch from a particular location.
• Notice that execution never stops!!! Processor is
always fetching, executing instructions!
• Called the Fetch,Execute loop.
• Must make sure that memory is loaded with valid
instructions BEFORE execution starts!!!

V 0.5 26
 Program Counter
• The counter in this processor is a special purpose
register that exists in one form or another in every
processor
• Usually is called the Instruction Pointer (IP)
register or Program Counter (PC) register.
• This register contains the address of the next
instruction to be fetched.
– Normal operation is to fetch very next instruction in memory
– Jump instructions change the PC value so that fetch occurs from
some non-sequential memory location

V 0.5 27
 Implementation Comparisons
• FSM Implementation
– Only 7 DFFs + combinational logic
– Will only do one number sequence
– Will operate a faster clock rate than Processor
implementation because of simpler logic
• Processor Implementation
– Many more gates needed than FSM implementation
– Will execute at a slower clock rate than FSM
– General purpose: can implement any number sequence
by simply changing program.
• MANY applications are better suited for
implementation by general purpose digital systems
(Processors) than by dedicated logic
V 0.5 28
 Vocabulary
• Address bus – input bus to memory device
specifying location of data to read/write
• Data bus – input/output bus to memory device
containing data value being read or written.
• Program Counter – special register in a processor
specifying address of next instruction to be
executed.
• Instruction Mnemonic – the ASCII representation
of an instruction (i.e., OUT 4).
• Machine Code – the binary representation of an
instruction (I.e OUT 4 = 010100)

V 0.5 29
 Vocabulary (cont.)
• Operation code (Op code) – the part of the
machine code for an instruction that tells what the
instruction is ( JMP = 00).
• Assembly – the process of converting instructions
to their machine code representation
OUT 4 → 10 0100
• Disassembly – the process of converting machine
code to its instruction mnemonic
10 0100 → OUT 4
• Fetch/Execute - what processors do all day long
(fetch instruction from memory, execute it).
V 0.5 30
 How are modern Computers different
from Number Sequencing Computer?
• NSC processor had 4-bit registers. Com. processors have
registers with widths from 8 bits to 128 bits wide.
• NSC processor has 2 registers. Com. proc have many
registers, some general purpose, some special purpose.
• NSC processor has 3 instructions. Com. Proc have 10’s to
a few hundred instructions (arithmetic, logical, control,
Input/output, data movement,etc).
• NSC processor could address 16 memory locations. Com.
Proc can address billions of memory locations.
• NSC processor can be implemented in a few 10’s of gates.
Com. Processors can take millions of gates to implement.

V 0.5 31
 What do you need to know?
• Differences between specific logic networks and
general purpose logic networks for digital
systems.
• Basics of a computer system
• Logic Structure, timing of our NSC sequence
processor
• Instruction assembly,disassembly, execution of
NSC sequence processor
• Vocabulary

V 0.5 32