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Analysis, Design and Implementation of 4-Bit Full Adder using FinFET

Article  in  Journal of Convergence Information Technology · March 2015

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 Analysis, Design and Implementation of 4-Bit Full Adder using FinFET
Jency Rubia J, Gopal B.G, Prabhu V

Analysis, Design and Implementation of 4-Bit Full Adder using FinFET

1
Jency Rubia J, 2Gopal B.G, 3 Prabhu V
1,2,3
Veltech Multitech Dr.Rangarajan Dr.Sakunthula Engineering College, Avadi, Chennai – 600062,
1
jencyrubia@gmail.com, 2bgg1969@gmail.com, 3 prabhu.cvj@gmail.com

Abstract
This paper proposes a 4-Bit full adder using FinFET at 45nm technology. The CMOS has been used
widely in current technology. But scaling the CMOS will cause the short channel effects such as DIBL,
GIDL, Sub threshold swing, channel length modulation, mobility degradation etc. To replace nano-
scale CMOS, a multi gate device called FinFET is proposed. FinFET has its own advantages
over the CMOS such as reduction in leakage power, operating power, leakage current and
transistor gate delay, reduced threshold level and steeper subthreshold swing. The target of this
paper is to reduce and calculate leakage power of 4-Bit full adder using FinFET.

Keywords: 4-Bit full adder, FinFET, Circuit designing, Device simulation, Device Modeling,
CMOS Integrated Circuit, Low Power

1. Introduction
Today mobile and computing markets continue to innovate at a dramatic rate delivering more
performance in smaller form factors with higher power efficiencies. According to Moore’s law,
the number of transistors in an area should double every months. To make this into reality,
transistors should get shrink in size to accommodate double the number per unit area. While
scaling down the device channel length, the short channel effects are raised [1]. These drawbacks
are tackled by FinFET. FinFETs have been considered as a promising technology to reduce the
short channel effects of the scale down devices, due to their better electrostatic control over the
channel[15]. ADDITION is the most commonly used arithmetic operation in Central Processing
Unit(CPU) and Arithmetic Logic Unit(ALU). Therefore, careful designing of ADDER is of the
utmost relevance.
Back Gate is used to control the threshold voltage (VT) of the front gate, which is very important
parameter of the device [3]. This helps in optimizing the circuits in terms of delay, area and power. In
the paper [4], the logic gates and flip flops are designed and analysed in Short Gate (SG), Independent
Gate (IG), Low Power (LP) and Mixed Mode (MM) in 90 nm technology. Minimum delay has been
achieved in SG mode, low power in LP configuration at the expense of increased delay was also
discussed. In IG mode, inputs can be applied to two different gates; thus reduces the number of devices
in a circuit. An MM results in low leakage, reduced area and higher delay. 4-T SRAM cell was designed
to achieve effective static noise margin (SNM) without area penalty [5]. This paper is organized as
follows. Section II clarifies the FinFET technology, its model parameter and challenges in design.
Section III describes the 4-bit full adder using FinFET 45nm technology. Section IV shows the
simulation waveform and the results. Finally the conclusion and the future enhancement has been
explained in section V.

2. FinFET technology
FinFETs are quasi-planar field-effect transistors. The working principle is same as that of planar
MOSFET [6-13]. Figure 1 shows the structure of a FinFET. With SOI wafer as a basic platform, a thin
film of silicon having thickness TSI is patterned on it. The gate shawls around the fin. The channel is
formed perpendicular to the plane of the wafer. Its length is shown as LG. This is the reason that the
device is termed quasi-planar. The effective width of a FinFET is 2nHfin , where ‘n’ is the number of
fins and Hfin is the fin height. Multiple fins are used to made a high on-current transistors [13]. FinFET
width is quantized, in terms of number of fins. Some key design factors like performance, power and
functionality, profound on β ratio are also dealt.

Journal of Convergence Information Technology (JCIT) 71

Volume 10, Number 2, March 2015
 Analysis, Design and Implementation of 4-Bit Full Adder using FinFET
Jency Rubia J, Gopal B.G, Prabhu V

Beyond the technology-driven benefits offered by FinFETs, circuits can also benefit from the double
gate structure of FinFETs to further optimize power and performance. FinFET leads to some interesting
designs by means of etching out the top part of the device that achieves independent gate structure.

Figure 1. (a) SG-FinFET (b) IG-FinFET

2.1. FinFET model parameter

In FinFET, as in Figure 2, the gate straddles a thin, fin shaped body, forming three-aligned
channels along the top and vertical sidewall surfaces of the fin. The use of double or multiple
gates surrounding the fin ensures an excellent electrostatic control. When the channel length is
scaled down, the predominant short channel effects and off-state leakage current arises which are
suppressed by reducing the width of the fin.
The fin width is an additional scaling parameter to the gate oxide. The fin width should be
unevenly half the channel length.

W fin  L 2
(1)

Figure 2. Electrical Dimension of the 3D FinFET Structure

A FinFET can have multiple fins in parallel, all straddled by a single gate line, thus its
effective width [2] is given by,

Weff  n(2 H fin  W fin )

(2)

where ‘n’ is the number of fins, Hfin and Wfin is the fin height and width respectively.

2.2. Challenges in FinFET

In a conventional planar transistor, shown in Figure 3 the current flowing through channel depends
upon the width of the device (W). As we know, width of the device is half the channel length (L). If the
device scale is down, it is necessary to decrease its channel length, which improves the drive strength of
the transistor. However smaller gate length, transistors have less control over the channel and

72
 Analysis, Design and Implementation of 4-Bit Full Adder using FinFET
Jency Rubia J, Gopal B.G, Prabhu V

exponentially higher subthreshold leakage. To control leakage, the channel should be heavily doped,
which will leads to design fluctuations are important challenges in manufacturing FinFET.

Figure 3. Planar FinFET vs. Tri Gate FinFET

In tri-gate transistor, the gate surrounds the channel on all three sides. It gives much control over the
channel. So all the charges below the channel is removed (fully depleted). If the gate is controlled
strongly then sub threshold leakage can be reduced with the best control of dopant variation on the
channel. FinFETs cause considerable changes in physical IP design but their effect can mostly be hidden
from higher levels. Designers can take advantages of improved performance by working at lower
voltages.

3. 4-Bit full adder using FinFET

3.1. Full adder

The full adder circuit is designed using FinFET 45 nm technology. Power supply of 1volt is given to
the circuit. Full adder has three inputs and two outputs (sum and carry). Each inputs have 4 bits of data.
The simulation results are shown in Figure 4. The expression for sum and carry are,

Sumk  AK  Bk  CK (3)

Carry  Ak Bk  Ck ( Ak  Bk ) (4)

Where k is an integer 0 to n for an n-bit adder. Generally n-bit adders are from created by
combining together n of the 1-bit adder slices. In the previous work [14], they designed 1-bit full
adder using FinFET 45nm technology with power supply of 0.7V. In this paper, 4-bit full adder is
designed and calculated the leakage power using 45nm technology. The power dissipation is found to be
543.171 nwatts.
Table 1. Truth Table for Full Adder
Input Output
A B Carry In Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Using the above truth table, the full adder circuit is designed. We can also see that, carry output is
high if two of the three output is high.

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 Analysis, Design and Implementation of 4-Bit Full Adder using FinFET
Jency Rubia J, Gopal B.G, Prabhu V

3.2. Leakage Power Analysis

Leakage current (ILEAK) is directly proportional to the thickness of the silicon and moderately
independent of oxide thickness. However, for FinFETs under the short-channel regime with low silicon
thickness and gate length, this is inaccurate as it fails to account for the short-channel effect and quantum
confinement effect. Based on the short-channel effect and quantum confinement, the FinFETs are
inaccurate which occurs in the short-channel regime. Leakage current should then be obtained from the
general expression for sub-threshold leakage.

 qVDS

 H Fin k BT (1  e k BT
) (5)
I LEAK 
dy

LG

0 TSI
2


TSI
nc ( x, y )dx
2
where nc(x,y) is the effective channel concentration, using Taylor series expansion of log (nc(x,y)), an
analytical model is developed for leakage in individual transistors and transistor stacks. The model
correctly predicts an exponential loss in gate control over increasing silicon thickness or decreasing gate
length, and hence an exponential increase in ILEAK. From the above observations, we formulate a
macromodel for leakage in SG-mode FinFET as
b1 b2
a1TS 1 
I LEAK  I SG 0 .e .e LG TS 1
(6)

where a1,a2,b1 are the coefficients.

4. Simulation Results and Waveforms

Input and the output waveforms are shown in Figure 4, 5 and Figure 6 respectively for 4-bit full
adder circuit. The 4 bit full adder has 8 inputs and one carry input. The resulted output is Sum and Carry
out. The Figure 4 explains about the first 4 inputs which are a0,a1,a2,a3 waveforms and the last waveform
is input b0.

a0

a1

a2

a3

b
0

Input Waveform for 4-bit Full Adder

Figure 4. Input Waveform for 4-bit Full Adder

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 Analysis, Design and Implementation of 4-Bit Full Adder using FinFET
Jency Rubia J, Gopal B.G, Prabhu V

The following Figure 5 shows the three input waveforms b1, b2, b3 and the last one is carry input.

b1

b2

b3

c0

Input Waveform for 4-bit Full Adder

Figure 5. Input Waveform for 4-bit Full Adder

The output waveform of 4 bit full adder is shown in Figure 6. The inputs a0, b0 and carry input c0 is
added .The wavform s0 is the sum output and the carry output c1 is used as a next carry input. Likewise
the same procedure is followed and the sum s1, s2, s3 is taken out. The final carry output is cout.

s0

s1

s2

s3

cout

Output Waveform of 4-Bit Full Adder

Figure 6. Output Waveform of 4-Bit Full Adder

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 Analysis, Design and Implementation of 4-Bit Full Adder using FinFET
Jency Rubia J, Gopal B.G, Prabhu V

The power dissipation in each sub-circuit of full adder is exhibited in Figure 7. Initially, the power
dissipation of first sub-circuit is 176 n watts. Similarly the power dissipation has been calculated from
all the sub-circuits. The total voltage source power dissipation calculated is 543.123n watts.

Figure 7. Power Analysis from Netlist

5. Conclusion and Future Work

This paper presents designing of 4-bit full adder using FinFET 45nm technology. To minimize the
leakage power, leakage current and operating power of a 4-bit full adder FinFET technique has been
employed. It is realized from the power analysis of full adder circuit as shown in Figure 7, the leakage
power is found to be 543.121 nW. The HPICE EDA tool is used to get the simulation results.
A reliable future work can be carried out in designing the ALU and other processing circuits using
this 4-bit full adder.

6. References

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[3] M.Rostami and K.Mohanram, “ Dual-Vth independent-gate FinFETs for low power logic
circuits”, IEEE Trans. Computer Aided Design, volume 30, no 3, pp 337-349, March 2011.
[4] Ajay N.Bhoj and Niraj K.Jha, “Design of Logic Gates and Flip-Flops in High-performance FinFET
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[5] Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici, “FinFET Based SRAM Design”, in
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 Analysis, Design and Implementation of 4-Bit Full Adder using FinFET
Jency Rubia J, Gopal B.G, Prabhu V

[6] A.Datta, A.Goel , R.T.Cakichi , H.Mahmoodi, D.Lakshmanan, and K.Roy, “Modeling and circuit
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