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    Lab2 PDF

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    Muhammad Salman Shahid
    The document describes a lab experiment analyzing the characteristics of NMOS and PMOS transistors using Cadence Virtuoso software. The student created the circuit diagrams for both types of transistors, then generated I-V curves showing the drain current (ID) versus gate-source voltage (VGS) at constant drain-source voltage (VDS), versus VGS at varying VDS, and versus VDS at constant VGS. The curves showed the expected transfer and output characteristics for each device type. Analysis of the curves demonstrated how varying VGS and VDS impacts the different regions of operation for NMOS and PMOS transistors.

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    Lab2 PDF

    Uploaded by

    Muhammad Salman Shahid
    57 views12 pages
    The document describes a lab experiment analyzing the characteristics of NMOS and PMOS transistors using Cadence Virtuoso software. The student created the circuit diagrams for both types of transistors, then generated I-V curves showing the drain current (ID) versus gate-source voltage (VGS) at constant drain-source voltage (VDS), versus VGS at varying VDS, and versus VDS at constant VGS. The curves showed the expected transfer and output characteristics for each device type. Analysis of the curves demonstrated how varying VGS and VDS impacts the different regions of operation for NMOS and PMOS transistors.

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    The document describes a lab experiment analyzing the characteristics of NMOS and PMOS transistors using Cadence Virtuoso software. The student created the circuit diagrams for both types of transistors, then generated I-V curves showing the drain current (ID) versus gate-source voltage (VGS) at constant drain-source voltage (VDS), versus VGS at varying VDS, and versus VDS at constant VGS. The curves showed the expected transfer and output characteristics for each device type. Analysis of the curves demonstrated how varying VGS and VDS impacts the different regions of operation for NMOS and PMOS transistors.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    57 views12 pages

    Lab2 PDF

    Uploaded by

    Muhammad Salman Shahid
    The document describes a lab experiment analyzing the characteristics of NMOS and PMOS transistors using Cadence Virtuoso software. The student created the circuit diagrams for both types of transistors, then generated I-V curves showing the drain current (ID) versus gate-source voltage (VGS) at constant drain-source voltage (VDS), versus VGS at varying VDS, and versus VDS at constant VGS. The curves showed the expected transfer and output characteristics for each device type. Analysis of the curves demonstrated how varying VGS and VDS impacts the different regions of operation for NMOS and PMOS transistors.

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    NAME M.

    SALMAN SHAHID
    REGISTRATION # 170401026
    BATCH EE-16
    VLSI LAB #02
    SUBMITTED TO SIR MEER HAMZA
    Analysis of Characteristics of NMOS and PMOS on
    Virtuoso Software
    Introduction:
    P-type metal-oxide-semiconductor logic, PMOS or pMOS, is a type of digital circuit constructed
    using metal-oxide-semiconductorfield transistors (MOSFET) with a p-type semiconductor source
    and drain printed on a bulk n-type "well". When activated, by lowering the voltage on the gate,
    the resulting circuit allows the conduction of electron holes between the source and drain,
    turning the circuit "on".

    PMOS circuits are less susceptible to electronic noise than other types of MOSFETs, which
    makes them easy to fabricate. They were widely used in the early days
    of microprocessor development in the 1970s. They have a number of disadvantages compared to
    the NMOS and CMOS alternatives, including the need for several different supply voltages (both
    positive and negative), high power dissipation in the conducting state, and relatively large
    features. Also, the overall switching speed is lower.

    N-typemetal-oxide-semiconductorlogic uses n-type (-) MOSFETs (metal-oxide-


    semiconductor field-effect transistors) to implement logic gates and other digital circuits. These
    nMOS transistors operate by creating an inversion layer in a p-type transistor body. This
    inversion layer, called the n-channel, can conduct electrons between n-type "source" and "drain"
    terminals. The n-channel is created by applying voltage to the third terminal, called the gate.
    Like other MOSFETs, nMOS transistors have four modes of operation: cut-off (or subthreshold),
    triode, saturation (sometimes called active), and velocity saturation.

    Objective:
    • To get familiar with VMware and cadence virtuoso cad tool
    • Generate both NMOS and PMOS I-V device characteristics (I/P and O/P) using Cadence

    • Plot results. Compare the current levels for the two devices in saturation when they are
    minimum sized.
    Apparatus:
    Virtuoso Cadence Software

    In Class Activity
    We have to draw and anlayse the I-V characterictic curve of NMos

    NMOS

    Procedure:

    • Firstly, I created libraries and cell views as per instructed by our instructor.
    • Then I placed component including NMosv1, dc sources and ground.
    • I made the circuit diagram.
    • Then I made different characteristics graphs
    • First graph was ID VS Vgs at a constant Vds
    • Next graph was ID vs Vgs at different values of vds
    • Next graph was ID vs Vds at constant Vgs.
    • The last graph was ID vs Vds at constant Vgs
    • I used DC sweep analysis and parametric analysis for the purpose.
    Circuit Diagram
    ID VS VGS AT VDS=1
    PARAMETRIC (ID VS VGS at different Vds)
    ID VS VDS (at constant Vgs)
    \ID vs VDS at different Vgs

    Analysis:
    From these graphs, we analyze

    Transfer Characteristic curve


    In id vs vgs graph at constant Vds, we have first a cutoff region and when voltage is above Vt is
    started to flow current and entered into linear region.

    Change of Vds does not affect much the cutoff region but it affects the linear region.

    Output Characteristics curve


    In Output characteristics curve, value of vgs has a large impact on curve.

    Curve will become constant soon if vgs is less and if vgs is more than it will have more time to
    become constant.
    Pmos

    Procedure

    • Firstly, I created libraries and cell views as per instructed by our instructor.
    • Then I placed component including PMosv1, dc sources and ground.
    • I made the circuit diagram.
    • Then I made different characteristics graphs
    • First graph was ID VS Vgs at a constant Vds
    • Next graph was ID vs Vgs at different values of vds
    • Next graph was ID vs Vds at constant Vgs.
    • The last graph was ID vs Vds at constant Vgs
    • I used DC sweep analysis and parametric analysis for the purpose
    Cicrcuit Diagram
    ID VS VGS AT VDS=1
    PARAMETRIC (ID VS VGS at different Vds)
    ID VS VDS (at constant Vgs)

    As you can see it is basically an inverse graph which will be occurring in 3rd quadrant. So it
    basically inverse graph if it is seen, it is in 3rd quadrant as required.

    ID vs VDS at different Vgs


    Analysis:
    From these graphs, we analyze

    Transfer Characteristic curve


    In id vs vgs graph at constant Vds, we have first a cutoff region and when voltage is above Vt is
    started to flow current and entered into linear region.

    Change of Vds does not affect much the cutoff region but it affects the linear region.

    Output Characteristics curve


    In Output characteristics curve, value of vgs has a large impact on curve.

    Curve will become constant soon if vgs is less and if vgs is more than it will have more time to
    become constant.

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