Visvesvaraya Technological University, Belagavi

MODEL QUESTION PAPER- Set I

6th Semester, B.E (CBCS) ECE
Course: 15EC63- VLSI DESIGN
Time: 3 Hours Max. Marks: 80

Note: (i) Answer five full questions selecting any one full question from each Module.
(ii) Question on a topic of a Module may appear in either its 1st or/and 2nd question.
Module-1
1. a) What do you mean by static load inverters? Derive the output voltage for pseudo Inverter by discussing its dc
characteristics.
• Other than CMOS inverter there are also other forms of inverters. One such is shown in the fig. below which has an
nMOS with load as resistor.
• This is an nMOS inverter circuit. When Vin = 0, nMOS is OFF and output goes to Vdd through the Rload. When Vin = 1,
nMOS is ON and pulls the output to gnd.
• When we consider the transfer characteristics and I-V characteristics, we see that as load is increased VOL decreases
also the current decreases. Thus choosing load resistor compromises between current and VOL.

Fig. nMOS inverter with resistive load, I-V characteristics and DC transfer characteristics
• An alternate to this is using a more practical circuit called pseudo-nMOS inverter circuit, which uses a pMOS
transistor as a load with its gate terminal always grounded.
• Here pMOS will be in ON state. When Vin = 0, nMOS is OFF and as pMOS is ON the output rises to Vdd. When Vin
= 1, nMOS will be ON and pulls the output to gnd.
• When the transfer characteristics is observed as the W/L ratio is varied for pMOS in the pseudo-nMOS inverter
circuit, the shape of the transfer characteristics varies.
• As parameter P (i.e., as W is decreased sharper characteristics is obtained) is varied characteristics varies with
higher value of P less sharper characteristics is seen.
• In the circuit P/2 represents the W/L ratio.

Fig. pseudo-nMOS inverter with I-V characteristics and DC transfer characteristics

 • These types of gates are called as ratioed circuits as transfer function depends on the strength of pull down
(pMOS) to pull up (nMOS) devices.
• In these types of circuits ratios must be chosen properly so that circuit operates properly.
• Disadvantage seen with these ratioed circuits are
o Constant power dissipation
o Poor noise margin
• However these circuits are used under limited circumstances such as reduced input capacitance and smaller area.

b) Derive the CMOS inverter DC characteristics graphically from p device and n device characteristics and show all
operating regions.

CMOS inverter
CMOS inverter shown in above fig. Table below outlines various regions of operation for the n- and p-transistors. In this table,
Vtn is the threshold voltage of the n-channel device, and Vtp is the threshold voltage of the p-channel device. Note that Vtp is
negative. The equations are given both in terms of Vgs/Vds and Vin/Vout. As the source of the nMOS transistor is grounded,
Vgsn = Vin and Vdsn = Vout. As the source of the pMOS transistor is tied to VDD, Vgsp =Vin – VDD and Vdsp =Vout – VDD.

• The objective is to find the variation in output voltage (Vout) as a function of the input voltage (Vin). This may be
done graphically, for simplicity, we assume Vtp = –Vtn and that the pMOS transistor is 2–3 times as wide as the
nMOS transistor so βn = βp.
• The plot shows Idsn and Idsp in terms of Vdsn and Vdsp for various values of Vgsn and Vgsp using drain current
equation.
• Fig 1.10(b) shows the same plot of Idsn and |Idsp| now in terms of Vout for various values of Vin. The possible
operating points of the inverter, marked with dots, are the values of Vout where Idsn = |Idsp| for same Vin.
• These operating points are plotted on Vout vs. Vin axes in Fig. (c) to show the inverter DC transfer characteristics.
• The supply current IDD = Idsn = |Idsp| is also plotted against Vin in Fig (d) showing that both transistors are
momentarily ON as Vin passes through voltages between GND and VDD, resulting in a pulse of current drawn from
the power supply.
• The operation of the CMOS inverter can be divided into five regions indicated on Fig 1.10(c). The state of each
transistor in each region and state of output is shown in Table 2.
o In region A, the nMOS transistor is OFF so the pMOS transistor pulls the output to VDD.
o In region B, the nMOS transistor starts to turn ON, pulling the output down.
o In region C, both transistors are in saturation.
o In region D, the pMOS transistor is partially ON
In region E, pMOS is completely OFF, leaving the nMOS transistor to pull the output down to GND.
 Table 2. Summary of CMOS Inverter Operation

Fig:Graphical Derivation of CMOS Inverter DC Characteristics

Fig. CMOS inverter DC Characteristics

OR

2 a) Explain the nMOS enhancement mode transistor operation for different values of Vgs and Vds .
When gate-to-source voltage, Vgs is less than threshold voltage and if source is grounded, then the junctions between
the body and the source or drain are zero-biased or reverse-biased and no current flows. We say the transistor is OFF,
and this mode of operation is called cutoff. This is shown in below fig
 Fig (a)
When a higher positive potential exceeding a critical threshold voltage Vt is applied, the holes are repelled further and
some free electrons in the body are attracted to the region beneath the gate. This results a layer of electrons in the p-
type body is called the inversion layer.

Fig(b)

When the gate voltage is greater than the threshold voltage, an inversion region of electrons (majority carriers) called the
channel connects the source and drain, creating a conductive path and turning the transistor ON as shown in Fig (b). The
number of carriers and the conductivity increases with the gate voltage. The potential difference between drain and
source is Vds= Vgs - Vgd. If Vds = 0 (i.e., Vgs =Vgd), there is no electric field tending to push current from drain to source.

Fig(c)

When a small positive potential Vds is applied to the drain, current Ids flows through the channel from drain to source.
This mode of operation is termed linear, resistive, triode, nonsaturated, or unsaturated mode as shown in Fig(c).

If Vds becomes sufficiently large that Vds >Vgs-Vt, the channel is no longer inverted near the drain and becomes pinched
off Fig (d). However, conduction is still brought about by the drift of electrons under the influence of the positive drain
voltage. Above this drain voltage the current Ids is controlled only by the gate voltage and ceases to be influenced by the
drain. This mode is called saturation.

b) Explain the fabrication steps of CMOS p-well process with neat diagram and write the mask sequence.

• There are a number of methods for CMOS fabrication, which includes p-well, n-well, twin tub and silicon-on-insulator
(SOI) processes.
• The p-well process is widely used and the n-well process as it is an retrofit to existing nMOS technology.
 Fig. CMOS p-well process steps

Fig. CMOS p-well inverter showing VDD and VSS substrate connections
• The p-well structure has an n-type substrate in which p-type devices can be formed with the help of masking and
diffusion. In order to accommodate n-type devices, deep p-well is diffused into the n-type substrate. This is
shown in Fig 1.
The summary of processing steps are:
▪ Mask: defines the areas in which the deep p-well diffusion has to take place.
▪ Mask 2: defines the thin oxide region (where the thick oxide is to be removed or stripped and thin oxide
grown)
▪ Mask 3: patterning the polysilicon layer which is deposited after thin oxide.
 ▪ Mask 4: A p+ mask is used (to be in effect “AND” with mask 2) to define areas where p-diffusion is to take
place.
▪ Mask 5: –ve form of mask 4 (p+ mask) is used which defines areas where n-diffusion is to take place.
▪ Mask 6: Contact cuts are defined using this mask.
▪ Mask 7: The metal layer pattern is defined by this mask.
▪ Mask 8: An overall passivation (over glass) is now applied and it also defines openings for accessing pads.

c) What are the advantages of BiCMOS process over CMOS technology.

BiCMOS technology CMOS process
1. Improved speed over CMOS Low Speed
2. Low power dissipation High power dissipation
3. Better analog capability Low analog capability
4. High Latch up immunity Low Latch up immunity

Module 2

3 a) Explain λ based design rules with neat diagram.

λ based Design rules are set of guidelines which specify minimum dimension and spacing allowed in layout drawing. Design
rules also acts a communication link between circuit designers and process engineers during manufacturing phase.
Design rules for wires and separations (nMOS and CMOS)

Design rules for Transistors (nMOS, pMOS and CMOS)

Design rules for Contact cuts (nMOS and CMOS)

b) Draw the circuit and stick diagram for nMOS and CMOS implementation of Boolean expression. Y =(A+B)’.

OR
4 a) Calculate the capacitance in □Cg for the given metal layer shown in the Fig Q4(a), if feature size=5µm and relative
value of metal to substrate =0.075.
b) Define sheet resistance Rs and standard unit of capacitance (□Cg). Calculate the on resistance of 4:1 nMOS inverter with
Rs=10kΩ/□, Zpu=8λ/2λ, Zpd=2λ/2λ. Also estimate the total power dissipated if VDD=5V.

Sheet resistance Rs can be defined as resistance of the channel whose length and width are equal.
𝐿
𝑅𝐷𝑆 = 𝑅𝑠
𝑊
𝜌
Where 𝑅𝑠 = is a constant and it is called sheet resistance.
𝑡
Area capacitance is defined as capacitance per unit area at the gate of transistor and denoted by 𝐶𝐴 .
∈0 ∈𝑟
𝐶𝐴 =
𝐷
∈0 = permittivity of free space = 8.854x 10−12 F/m.
∈𝑟 = relative permittivity of a given material
𝐷 = thickness of sio2 constant for a given technology.
 Module 3
5 a) Find the scaling factors for:
i) Saturation current:

Co is scaled by β, μ and 2 are constants, W and L is scaled by 1/α, Vgs and Vt both voltages are scaled by 1/ β.
Thus Idss is scaled by β*(1/ β)2 = 1/β
ii) Current density:
𝐼𝑑𝑠𝑠
J= 𝐴
A is the cross sectional area of channel in ‘on’ state and is scaled by 1/α2 and Idss is scaled by 1/β.
Thus J is scaled by (1/β)/(1/α2) = α2/β
iii) Power dissipation/unit area:
Pa is defined as scaled by

iv) Maximum operating frequency:

fo = W/L *(μ Co VDD)/Cg
or fo is inversely proportional to Td
Thus fo is scaled as 1/( β/α2) = α2/ β
b) Design a 4 bit ALU to implement addition, subtraction, EX-OR, EX-NOR, OR and AND operations.
• An ALU must be able to add and subtract two binary numbers, perform logical operations such as AND, OR
and Equality (EX-OR) functions.
• Subtraction can be easily implemented using the adder element. Suppose we need find A – B, then
▪ Compliment B and add 1 to it to get B’
▪ Add this to A i.e., A+B’
▪ This gives subtraction using adder
• Here compliment for subtraction can be served from ‘logical compliment’ (negate)
• In order to keep architecture as simple as possible it would be better if all the logical operations can be
performed on the adder.
• Considering the possibility
We have the sum and new carry equations as
Sum Sk = Hk C’k-1 + Hk’ Ck-1
New carry Ck = Ak Bk + Hk Ck-1
Where Hk = A’k Bk + Ak B’k

➢ If in Sk , if Ck-1 is held at logic 0 then the expression would be

➢ Sk = Hk .1 + Hk’ 0
➢ Sk = Hk = A’k Bk + Ak B’k
➢ This represents the EX-OR function/operation
➢ If in Sk , if Ck-1 is held at logic 1 then the expression would be
➢ Sk = Hk .0 + Hk’. 1
 ➢ Sk = H’k = A’k B’k + Ak Bk
➢ This represents the EX-NOR function/operation
➢ If in Ck , if Ck-1 is held at logic 0 then the expression would be
➢ Ck = Ak Bk + Hk 0
➢ Ck = Ak Bk
➢ This represents the AND function/operation
➢ If in Ck , if Ck-1 is held at logic 1 then the expression would be
➢ Ck = Ak Bk + Hk . 1 = Ak Bk + Hk
➢ Ck = Ak Bk + A’k Bk + Ak B’k
➢ Ck = Bk + Ak B’k
➢ Ck = Bk + Ak
➢ This represents the OR function/operation
• Thus with suitable switching of carry line between adder element will give ALU logical functions.

One such arrangement for both arithmetic and logical function is shown in figure.

OR
6 a) With a neat diagram, explain 4x4 barrel shifter.
• A general purpose n-bit shifter should be capable of shifting n incoming data up to n-1 place either in a right or
left direction.
• Shifting should take place in ‘end-around’ basis i.e., any bit shifted out at one end of a data word will be shifted in
at the other end of the word. Thus the problem of right shift or left shift can be easily eased.
• It can be analyzed that for a 4-bit word, that a 1-bit shift right is equivalent to a 3-bit shift left and a 2-bit shift
right is equivalent to a 2-bit left etc. Hence, the design of either shift right or left can be done. Here the design is
of shift right by 0, 1, 2, or 3 places.
• The shifter must have:
 • input from a four line parallel data bus
• Four output lines for the shifted data
• The input data can be transferred to output lines using shift from 0, 1, 2 to 3 bits
• While designing the strategy should be decided. The chosen strategy here is data flow direction is horizontal and
control signal flow direction is vertical.
• To meet the criteria a 4 × 4 crossbar switch is used. The MOS switch implementation of 4 × 4 crossbar switch is
shown in the Fig below.

• To drive each cross bar switch - 16 control signals SC00 to SC15 are provided to each transistor switch.
• Arrangement is general and can be expanded to accommodate n-bit inputs/outputs.
• In this arrangement any input can be connected to any or all the outputs.
• If all switches are closed all inputs are connected to all outputs and it forms a short circuit.
• As it needs 16 control signal it increases the complexity and to reduce the complexity, the switch gates are
coupled in groups (in this case it is grouped into 4)
• Here 4 groups of 4 is formed which corresponds to shift 0, shift 1, shift 2 and shift 3 bits. This arrangement is
called ‘barrel shifter’. (In this only 4 control signals is needed)

• The inter bus switches have their gate inputs connected in a staircase fashion in groups of four and there are now
four shift control inputs which must be mutually exclusive in the active state.
• CMOS transmission gates may be used in place of the simple pass transistor switches if appropriate. Barrel shifter
connects the input lines representing a word to a group of output lines with the required shift determined by its
control inputs (sh0, sh1, sh2, sh3). Control inputs also determine the direction of the shift. If input word has n –
bits and shifts from 0 to n-1 bit positions are to be implemented.

SH0 SH1 SH2 SH3 SH4

O0 O1 O2 O3 O0
O1 O2 O3 O2 O1
O2 O3 O0 O1 O2
 O3 O0 O1 O0 O3

Block diagram of barrel shifter and shifting of data is shown in the table.

b) Describe Manchester Carry-chain.

• It is a fast adder circuit, it is a carry propagate adder in which the delay taken by the carry to reach the last stage
of output is reduced.
• As seen in the previous concept of passing the carry the transmission gate, the path can be precharged by the
clock
• Then the path can be gated by the n-type pass transistor.
• When clock is 0, output will be charged to logic high due to pMOS. When clock is 1 pMOS will be off. If Pk is high,
then the carry will be propagate.
• If Pk is 0, then Ck-1 will not be propagated.
• Depending on inputs at Gk , (Ak = Bk =1) carry will be generated or (Ak = Bk =0) no carry generation.
• Even though Manchester carry cells are faster while cascading delay is observed. Cascading is done by connecting
pass transistor in series.
• As n pass transistor is cascaded the delay also increases as square of n. thus in order to reduce delay buffers are
included at after every 4 chain as shown in the block diagram

Fig. Cascading of Manchester carry adder

 Module 4

7 a) Discuss the architectural issues related to subsystem.

The following are the guidelines/architectural issues that needs to be considered while designing of the
system.
1. Define the requirements carefully and properly.
2. Partition the overall architecture into appropriate subsystems.
3. Communication paths should be carefully selected in order to develop sensible interrelationships between the
subsystems.
4. Draw the floor plan of how the system is to map onto the silicon.
5. Aim for regular structures so that design is largely a matter of replication.
6. Draw suitable stick or symbolic diagrams of the leaf-cells of the subsystem.
7. Convert each cell into layout.
8. Carry out design rule check carefully and thoroughly.
9. Simulate the performance of each cell/subsystem.
b) Explain Pseudo nMOS logic for NAND gate and Inverter.
In nMOS circuit if the pull-up network with depletion mode transistor is replaced by pMOS transistor with
its gate connected to Vss. This structure is called as pseudo- nMOS logic.
This logic helps in reducing the number of transistors seen in the CMOS logic seen for pull-up network.
Fig. shows 3 input NAND logic using pseudo-nMOS logic.
As the pMOS is connected to VSS it can be either in saturation or active region and the status of nMOS at
pull-doun network depend on the state of input.
When all the inputs are zero, pMOS will be on and the output is pulled up to VDD and with other data pMOS acts
as a current source (saturation). The output is now the product of the resistance of the pull-down network
and current of the pull-up network.

In order to obtain required ratio, the arrangement considered is pseudo-nMOS inverter being driven by
another pseudo-inverter.
For analysis taking the condition Vin = VDD/2, in this condition nMOS device is operating in
saturation (0 < Vgsn – Vtn < Vdsn) and pMOS is operating in linear
/resistive region (0 < Vdsp < Vgsp – Vtp).
Equating the currents of nMOS and pMOS and suitable arrangement, we obtain the equation as
 We obtain

OR

8 a) Explain Parity generator with basic block diagram and stick diagram.
The parity generating technique is one of the most widely used error detection techniques for the data
transmission. In digital systems, when binary data is transmitted and processed, data may be subjected to
noise. Hence, parity bit is added to the word containing data in order to make number of 1s either even or odd.
In even parity bit scheme, the parity bit is ‘0’ if there are even number of 1s in the data stream and the parity bit is ‘1’ if
there are odd number of 1s in the data stream.
In odd parity bit scheme, the parity bit is ‘1’ if there are even number of 1s in the data stream and the parity bit is
‘0’ if there are odd number of 1s in the data stream. Let us discuss both even and odd parity generators.
In VLSI a circuit to be designed to indicate parity of a binary number is shown in the fig for (n+1) bit input.

Since the no. of bits is undefined, a general solution on cascadeable bit-wise and a regular structure is shown in
Fig. A standard or basic one-bit cell from which an n-bit parity generator may be formed. The standard/ basic
cell is shown in the Fig
The parity information is passed from one cell to next and the parity information is modified or retained
depending on the input lines Ai and A’i
 If Ai = 1, parity output Pi will change to P’i-1 (i.e., if Ai [input] =1 and Pi-1 [previous parity] =1, the output parity
Pi will change to 0)
If Ai = 0, output parity Pi will remain in the same state of Pi-1 (i.e., if Ai [input] =0 and
Pi-1 [previous parity] =1, the output parity Pi will remain as 1)
Suitable arrangement for such cell is implemented using the expression
Pi = P’i-1 Ai + Pi-1 A’i
The same can be implemented using nMOS and CMOS technology. The parity generator symbol and stick
diagram for nMOS technology is shown below.

Fig. Symbol for Pi

Fig. nMOS stick diagram for parity generator

b) Explain FPGA architectures.
FPGA consists of three major elements.
Combinational Logic
Interconnect
I/O pins
The combinational logic is divided into small units which is known as logic elements(LE) or combinational
logic blocks(CLB).
LE or CLB usually forms the functions of several logic gates.
Interconnections between these logic elements are made using programmable interconnects.
This interconnects are logically organized into channels or other units.
FPGA offers several interconnects depending on the distance between CLB’s that are to be connected: clock
signals are provided with their own interconnection networks.
I/O pins are referred as I/O blocks.These are generally programmable for inputs or outputs and often provides other
features such as low power or high speed connection.
FPGA Interconnect:
The FPGA designer should rely on pre-designed wiring, unlike custom VLSI designer cannot design wires as needed.
The interconnection system of FPGA is one of the most complex aspect because wiring is global property of
logic design.
Connection between logic elements requires complex paths since LE’s are arranged in two dimensional structure as
shown in below figure.

Wires are typically organized in wiring channels or routing channels which runs horizontally and vertically
throughout the chip.
Each channel contains several wires designer or program chooses which wire will carry signal in each channel.
Connection must be made between wires to carry signal from one point to another.
Ex: Net in figure starts from output of LE in upper-right-hand corner travels down vertical channel 5 until it
reaches horizontal channel 2, then moves down vertical channel 3 to horizontal channel 3, then it uses vertical
channel 1 to reach the input of LE at Lower-left-corner.
FPGA channel must provide wires of variety of lengths for designer to make all the required connection between
logic elements.
Since LE’s are organized in regular array we can arrange wires going from one LE to another. Figure below shows
connections of varying length as measured in unit LE’s: top signal of length 1 goes to next LE, the second signal goes to
second LE and so on. This organization is Known as segment wiring structure.
 All FPGA’s need to be programmed or configured.
There are three major circuit technologies for configuring an FPGA: SRAM, Antifuse and flash.

Module 5
9 a) Explain 3 transistor dynamic RAM cell.

• In this cell arrangement it uses a single transistor for storing data and 2 transistors for each RD and WR access
switch.
• It has a pull-up network with either CMOS or nMOS technology and RD/WR circuit as pull-down network.
• The binary data is stored at gate capacitance of transistor in the form of charge; RD and WR are the control lines.
• T1 with T2 is used for writing the data and T3 with T2 is used for reading the data. At point I data is written and
read.
• Here T2 is the storage transistor and T1 & T3 are pass transistors which acts as access switches for control lines
RD and WR and also for read and write operations.

Write Operation
• WR and RD signals are mutually exclusive i.e., compliment to each other.
✓ When WR = 1, RD will be 0
✓ Because of WR = 1, T1 is ON but T3 and T2 are OFF.
✓ If data bit on bus is 1, as T1 pass transistor is ON it will pass the signal (V DD – Vth) towards T2. The
capacitor is charged to this potential at I
✓ If data bit is 0, as T1 is ON it will pass the signal and charge stored at I is 0.
✓ After the data is stored at I or capacitor WR signal is made to 0
Read Operation
• For this RD = 1, WR = 0
✓ As WR = 0, T1 is OFF and T3 is ON as RD = 1
✓ T2 will be ON/OFF depending on the voltage/charge stored at I (gate capacitance of T2)
✓ If logic 1 is stored at I, then T2 will be ON. Thus T3 and T2 is ON and path for discharge and the
bus is pulled down to ground.
 ✓ If logic 0 is stored at I, the T2 is OFF and charge does not any path for discharge and retains logic
at logic1
Note: The compliment of stored bit is read on the data bus
• In DRAM sensing amplifiers will be connected and as the output begins to decrease from 1 to 0 and this
makes the sensing amplifier output as logic 1. If the output does not change then sensing amplifier will
make the output as logic 0.
Static Power:
• Static power dissipation is nil since current flows only when i )RD signal is high and ii)logic 1 is stored
• Thus actual dissipation associated with each stored bit depends on the bus pull-up and the duration RD and
on switching frequency
Area:
• In 4mm× 4mm, silicon chip area data storage can be >4.8kbits.
Volatility:
• Cell is dynamic and will hold data only for as long as sufficient charge remains on gate capacitance of T2

b) Write a note on testability and testing.

The keys to designing circuits that are testable are controllability and observability. Controllability is the ability to set (to
1) and reset (to 0) every node internal to the circuit. Observability is the ability to observe, either directly or indirectly,
the state of any node in the circuit. Good observability and controllability reduce the cost of manufacturing testing
because they allow high fault coverage with relatively few test vectors.
There are three main approaches to what is commonly called as Design for Testability (DFT). These may be categorized
as follows:
▪ Ad hoc testing
▪ Scan-based approaches
▪ Built-in self-test (BIST)
Ad hoc Testing:
Ad hoc test techniques, as their name suggests, are collections of ideas aimed at reducing the combinational explosion of
testing. They are only useful for small designs where scan, ATPG, and BIST are not available.
Some of the common techniques for ad hoc testing are:
✓ Partitioning large sequential circuits
✓ Adding test points
✓ Adding multiplexers
✓ Providing for easy state reset
Some of the examples are: multiplexers can be used to provide alternative signal paths during testing. In CMOS,
transmission gate multiplexers provide low area and delay overhead. Use of the bus in a bus-oriented system for test
purposes. Here each register is made loadable from the bus and capable of being driven onto the bus. Here, the internal
logic values that exist on a data bus are enabled onto the bus for testing purposes.

Any design should always have a method of resetting the internal state of the chip within a single cycle or at most a few
cycles. Apart from making testing easier, this also makes simulation faster as a few cycles are required to initialize the
chip. In general Ad hoc testing techniques represent a bag of tricks.
OR

10 a) Explain the scan design techniques.

• The scan-design strategy for testing has evolved to provide observability and controllability at each register.
 • In designs with scan, the registers operate in one of two modes.
• In normal mode: they behave as expected
• In scan mode: they are connected to form a giant shift register called a scan chain spanning the whole chip.
• By applying N clock pulses in scan mode, all N bits of state in the system can be shifted out and new N bits of
state can be shifted in. Thus scan mode gives easy observability and controllability of every register in the system.
• Modern scan is based on the use of scan registers, as shown in Fig. The scan register is a D flip-flop preceded by a
multiplexer. When the SCAN signal is deasserted (made to 0), the register behaves as a conventional register,
storing data on the D input. When SCAN is asserted (made to 1), the data is loaded from the SI pin, which is
connected in shift register fashion to the previous register Q output in the scan chain.
• To load the scan chain, SCAN is asserted and 8 CLK pulses are given to load the first two ranks of 4-bit registers
with data. Then SCAN is deasserted and CLK is asserted for one cycle to operate the circuit normally with
predefined inputs. SCAN is then reasserted and CLK asserted eight times to read the stored data out. At the same
time, the new register contents can be shifted in for the next test.
• . Testing proceeds in this manner of serially clocking the data through the scan register to the right point in the
circuit, running a single system clock cycle and serially clocking the data out for observation. In this scheme, every
input to the combinational block can be controlled and every output can be observed.

• Test generation for this type of test architecture can be highly automated.
The prime disadvantage is the area and delay impact of the extra multiplexer in the scan register.
Parallel Scan:

Serial scan chains can become quite long, and the loading and unloading can dominate testing time. A simple
method/solution is to split the chains into smaller segments. This can be done on a module-by-module basis or
completed automatically to some specified scan length. This method is called ‘Random Access Scan’.
 Fig shows a two-by-two register section. Each register receives a column (column<m>) and row (row<n>) access signal
along with a row data line (data<n>). A global write signal (write) is connected to all registers. By asserting the row and
column access signals in conjunction with the write signal, any register can be read or written.

b) Demonstrate write operation & read operation for four transistor dynamic and six transistor static CMOS memory cell.
▪ The cells here include both n-type and p-type transistors and are intended for CMOS systems.
▪ Both the dynamic and static elements uses 2 bus per bit arrangement so that the bit is available in both
normal and compliment form on bit and bit’ bus
▪ Prior to reading and writing operation of the data, the buses are pre-charged to VDD or logic 1.

4 Transistor Dynamic memory cell:

Fig. four transistor dynamic RAM with sense amplifier

Write operation:
 • Before writing onto memory the bit and bit’ line is pre-charged to logic 1 using pMOS transistor T5 and T6
in coincidence with clock signal ϕ1
• Next appropriate column is selected in coincidence with the clock signal ϕ2.
• Depending on the data on the bus either bit or bit’ is discharged.
• At the same clock signal ϕ2 the row select line is activated, turning on transistors T3 and T4.
• Thus value on bit and bit’ are written via T3 and T4 stored at T2 and T1 as gate capacitances C g2 and Cg1
respectively.
• The way in which T2 and T1 are connected always gives the complimentary states when row select line is
activated. When row line is deactivated the data stored will remain until the gate capacitance can hold
the value.
• For refreshing sense amplifier is provided which will permanently hold the data.
Read operation:
• Before reading again bit and bit’ lines are pre-charged to VDD using T5 and T6 transistors.
Suppose in the memory element if logic 1 is stored i.e., at gate of T2 and at gate of T4 logic 1 is stored.
• When column and row lines are selected i.e., T3 and T4 will be in ON state.
• As logic 1 is available at T2, T2 will be in ON state and T1 will be in OFF state. Thus T3 = ON, T1 = OFF, T4 =
ON, T2 = ON. With this condition bit’ which was pre-charged to VDD has now a path to discharge to VSS.
Hence bit’ = 0 and bit = 1 as shown in the Fig.
• When sense amplifier senses this voltage variation on bit’ line and outputs the data on bus line. The bit =
1 and bit’ = 0, which represents the data in the memory.
• The sense amplifier formed from the arrangement of T1, T2, T3 and T4, which forms a flip flop circuit.
• If the “sense” de-active/ inactive, then the bit line state is reflected in the gate capacitances of T1 and T3
and this is w.r.t VDD. This will cause one of the transistor to turn ON and other to turn OFF.
• When sense = enabled, current flows from VDD through ON transistor and helps to maintain the state of
the bit line.
• Sense amplifier performs 2 function
1. Rewriting the data after reading i.e., refreshing the memory cell so that it holds the data without
signal degradation
2. It predetermines the state of the data lines.
 Fig. six transistor static RAM cell with sense amplifier

• Figure shows 6 T SRAM with the adaption of dynamic cell and modifying it to form a static memory cell.
• It includes 2 additional transistor per store bit thus it is called 6 transistor. The transistor T5 and T6 acts as the
access switch for memory element which is formed by connecting two inverters back to back (i.e., output of one
is connected as the input of the other)

Similar to 4T Dynamic RAM the information is stored in memory cell. The memory cell is connected in such a way that it
gives the complimentary states when row select line is activated. When row line is deactivated the data stored will
remain in the memory cell.