MDU5593S: Dual Asymmetric N-Channel Trench MOSFET 30V
MDU5593S: Dual Asymmetric N-Channel Trench MOSFET 30V
MDU5593S: Dual Asymmetric N-Channel Trench MOSFET 30V
MDU5593S
Dual Asymmetric N-channel Trench MOSFET 30V
S2
5 S2
6 S2
7 G2
8
S1/D2
1 D1 3
2 D1 2
3 D1 1
4
G1
Thermal Characteristics
Characteristics Symbol FET1 FET2 Unit
(1)
Thermal Resistance, Junction-to-Ambient RθJA 57 50 o
C/W
Thermal Resistance, Junction-to-Case RθJC 3.5 2.8
Note :
1. Surface mounted FR-4 board by JEDEC (jesd51-7). Continuous current at TC=25℃ is silicon limited.
2. EAS is tested at starting Tj = 25℃, L = 0.5mH, IAS = 15.5A, VDD = 27V, VGS = 10V. And 100% UIL Test at L = 0.1mH, IAS = 18.0A.
30 7
3.5V
20 6
VGS = 10V
10 5
3.0V
0 4
0.0 0.2 0.4 0.6 0.8 1.0 10 20 30 40 50
1.8 20
※ Notes :
※ Notes :
1. VGS = 10 V
1.6 ID = 13A
2. ID = 13 A
Drain-Source On-Resistance
Drain-Source On-Resistance
16
RDS(ON), (Normalized)
1.4
RDS(ON) [mΩ ],
1.2
12
1.0 TJ = 25
℃
8
0.8
0.6
-50 -25 0 25 50 75 100 125 150 4
3 4 5 6 7 8 9 10
o
TJ, Junction Temperature [ C] VGS, Gate to Source Volatge [V]
Fig.3 On-Resistance Variation with Fig.4 On-Resistance Variation with
Temperature Gate to Source Voltage
Area
25
※ Notes :
※ Notes : VGS = 0V
VDS = 5V
IDR, Reverse Drain Current [A]
20 1
10
ID, Drain Current [A]
15
TJ=25 ℃
TJ=25 ℃
10 10
0
-1
0 10
1 2 3 4 5 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
1200
Capacitance [F]
6
800
Coss ※ Notes ;
4 1. VGS = 0 V
2. f = 1 MHz
400
2
Crss
0 0
0 5 10 15 20 0 10 20 30
QG, Total Gate Charge [nC] VDS, Drain-Source Voltage [V]
2
10
60
50
10 ms
ID, Drain Current [A]
1
ID, Drain Current [A]
10
Operation in This Area
40
is Limited by R DS(on) 100 ms
Limited by Package
30
1s
10 s
0 DC
10 20
Single Pulse 10
TJ=Max Rated
TA=25℃
-1
10 0
10
-1
10
0
10
1
10
2 25 50 75 100 125 150
Fig.9 Maximum Safe Operating Area Fig.10 Maximum Drain Current vs. Case
Temperature
1
10
, Normalized Thermal Response
D=0.5
0
10 0.2
0.1
0.05
※ Notes :
-1 0.02 Duty Factor, D=t 1/t2
10
PEAK TJ = PDM * Zθ JA* Rθ JA(t) + TA
0.01
-2 single pulse
10
JA
Zθ
-3
10
-4 -3 -2 -1 0 1 2 3
10 10 10 10 10 10 10 10
t1, Rectangular Pulse Duration [sec]
Note :
1. Surface mounted FR-4 board by JEDEC (jesd51-7). Continuous current at TC=25℃ is silicon limited.
2. EAS is tested at starting Tj = 25℃, L = 0.5mH, IAS = 15.5A, VDD = 27V, VGS = 10V. And 100% UIL Test at L = 0.1mH, IAS = 18.0A.
4.0
3.5V
30
3.5
20
3.0V VGS = 10V
3.0
10
2.5
0 2.0
0.0 0.2 0.4 0.6 0.8 1.0 10 20 30 40 50
1.8 20
※ Notes : ※ Notes :
18
1. VGS = 10 V ID = 21A
1.6 2. ID = 21 A
Drain-Source On-Resistance
16
Drain-Source On-Resistance
RDS(ON), (Normalized)
1.4 14
RDS(ON) [mΩ ],
12
1.2
10
8
1.0
6
TJ = 25 ℃
0.8 4
2
0.6
-50 -25 0 25 50 75 100 125 150 0
2 3 4 5 6 7 8 9 10
o
TJ, Junction Temperature [ C] VGS, Gate to Source Volatge [V]
20
IDR, Reverse Drain Current [A]
1
10
ID, Drain Current [A]
15
TJ=25 ℃
TJ=25 ℃
10
0
10
0
-1
1 2 3 4 10
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VGS, Gate-Source Voltage [V]
VSD, Source-Drain voltage [V]
2000 Ciss
Capacitance [F]
6
Coss
4
1000
※ Notes ;
1. VGS = 0 V
2. f = 1 MHz
2
Crss
0
0 0 10 20 30
0 10 20 30
2
10 100
10 ms 80
ID, Drain Current [A]
1
10
Operation in This Area
100 ms
60
is Limited by R DS(on)
1s
10 s
DC 40
0
10
Limited by Package
20
Single Pulse
TJ=Max Rated
TA=25 ℃
-1
10 0
-2 -1 0 1 2
10 10 10 10 10 25 50 75 100 125 150
Fig.9 Maximum Safe Operating Area Fig.10 Maximum Drain Current vs. Case
Temperature
1
10
, Normalized Thermal Response
D=0.5
0
10
0.2
0.1
0.05 ※ Notes :
-1
0.02 Duty Factor, D=t1/t2
10
PEAK TJ = PDM * Zθ JA* Rθ JA(t) + TA
0.01
-2
10
JA
Zθ
single pulse
-3
10
-4 -3 -2 -1 0 1 2 3
10 10 10 10 10 10 10 10
t1, Rectangular Pulse Duration [sec]
DISCLAIMER:
The Products are not designed for use in hostile environments, including, without limitation, aircraft, nuclear power
generation, medical appliances, and devices or systems in which malfunction of any Product can reasonably be
expected to result in a personal injury. Seller’s customers using or selling Seller’s products for use in such
applications do so at their own risk and agree to fully defend and indemnify Seller.
MagnaChip reserves the right to change the specifications and circuitry without notice at any time. MagnaChip does not consider responsibility
for use of any circuitry other than circuitry entirely included in a MagnaChip product. is a registered trademark of MagnaChip
Semiconductor Ltd.