VERILOG HDL
Chapter 5
Syntax and Semantics
Trương Phong Tuyên
Lexical Conventions
• The basic lexical conventions used by
Verilog HDL are similar to those in the C
programming language.
• Verilog HDL is a case-sensitive language.
• All keywords are in lowercase.
2
Lexical Conventions
• White Space
White space can contain the characters for blanks, tabs,
newlines, and form feeds. These characters are ignored
except when they serve to separate other tokens.
However, blanks and tabs are significant in strings.
White space characters are:
• Blank spaces
• Tabs
• Carriage returns
• New-line
• Form-feeds
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Lexical Conventions
• Functional Equivalent Code
4
Lexical Conventions
• Comments
There are two forms to
introduce comments.
• Single line comments
begin with the token //
and end with a carriage
return
• Multi line comments
begin with the token /*
and end with the token */
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Lexical Conventions
• Case Sensitivity
Verilog HDL is case sensitive
Lower case letters are unique from upper case letters
All Verilog keywords are lower case
Examples
Never use Verilog keywords as unique names, even if the
case is different.
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Lexical Conventions
• Identifiers
Identifiers are names used to give an object, such as a
register or a function or a module, a name so that it can be
referenced from other places in a description.
• Identifiers must begin with an alphabetic character or the underscore
character (a-z, A-Z, _)
• Identifiers may contain alphabetic characters, numeric characters, the
underscore, and the dollar sign (a-z, A-Z, 0-9, _, $ )
• Identifiers can be up to 1024 characters long.
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Lexical Conventions
• Escaped Identifiers
Verilog HDL allows any character to be used in an
identifier by escaping the identifier. Escaped identifiers
provide a means of including any of the printable
ASCII characters in an identifier (the decimal values
33 through 126, or 21 through 7E in hexadecimal).
Escaped identifiers begin with the back slash ( \ )
Entire identifier is escaped by the back slash.
Escaped identifier is terminated by white space (Characters
such as commas, parentheses, and semicolons become part
of the escaped identifier unless preceded by a white space)
Terminate escaped identifiers with white space, otherwise
characters that should follow the identifier are considered as
part of it.
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Lexical Conventions
• Examples of escape
identifiers
Verilog does not allow to
identifier to start with a
numeric character. So if you
really want to use a identifier
to start with a numeric value
then use a escape character
as shown below.
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Numbers in Verilog
• You can specify constant numbers in decimal,
hexadecimal, octal, or binary format. Negative
numbers are represented in 2's complement form.
When used in a number, the question mark? character
is the Verilog alternative for the z character. The
underscore character (_) is legal anywhere in a
number except as the first character, where it is
ignored.
• Examples:
8’b 1001 0001
8’b 1101_00zz 8’b 1101_00??
8’h A9
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Numbers in Verilog
• Integer Numbers
Verilog HDL allows integer numbers to be specified
as sized or unsized numbers (unsized size is 32bits)
In a radix of binary, octal, decimal, or hexadecimal
Radix and hex digits (a,b,c,d,e,f) are case
insensitive
Spaces are allowed between the size, radix and
value
Syntax
<size>’<radix><value>;
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Numbers in Verilog
• Integer Numbers (cont.)
Verilog expands <value> filling the specified <size> by working from right-
to-left
When <size> is smaller than <value>, then leftmost bits of <value> are
truncated
When <size> is larger than <value>, then leftmost bits are filled, based on
the value of the leftmost bit in <value>.
• Leftmost '0' or '1' are filled with '0'
• Leftmost 'Z' are filled with 'Z'
• Leftmost 'X' are filled with 'X'
Note: X stands for unknown and Z stands for high impedance, 1 for logic
high or 1 and 0 for logic low or 0
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Numbers in Verilog
• Example of Integer Numbers
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Numbers in Verilog
• Real Numbers
Verilog supports real constants and variables.
Verilog converts real numbers to integers by rounding.
Real Numbers can not contain ‘Z’ and ‘X’.
Real numbers may be specified in either decimal or scientific
notation.
Syntax
< value >.< value >
< mantissa >E< exponent >
Real numbers are rounded off to the nearest integer when
assigning to an integer.
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Numbers in Verilog
• Signed and Unsigned Numbers
Verilog supports both types of numbers, but with certain
restrictions. Like in C language we don't have int and unint
types to say if a number is signed integer or unsigned
integer.
Any number that does not have negative sign prefix is a
positive number. Another indirect way would be “unsigned".
Negative numbers can be specified by putting a minus sign
before the size for a constant number, thus they become
signed numbers. Verilog internally represents negative
numbers in 2's complement format. An optional signed
specifier can be added for signed arithmetic (Ver. 2001).
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Numbers in Verilog
• Example of Real Numbers
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Numbers in Verilog
• Example of Real
Numbers (cont.)
The example file
shows how Verilog
treats signed and
unsigned numbers.
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Numbers in Verilog
• Example of Real Numbers (cont.)
Verilog 1995 Vs. Verilog 2001
• The only way to declare a signed value in Verilog 1995
was to declare it as an integer.
• Verilog 2001 provides the ‘s construct for declaring and
specifying a sized value as signed. For example, 2
represented as a 3-bit signed hex value would be
specified as 3 ’sh2. The value -4 represented as a 3-bit
signed hex value would be specified as -3’ sh4.
Examples
• input signed [7:0] data_in;
• reg signed [7:0] data = 8'shF0;
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Modules
• Modules are the building
blocks of Verilog designs.
• You create the design
hierarchy by instantiating
modules in other modules.
• You instance a module when
you use that module in
another, higher-level
module.
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Modules
• Ports
Ports allow communication between a module and
its environment.
All but the top-level modules in a hierarchy have
ports.
Ports can be associated by order or by name.
You declare ports to be input, output or inout.
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Modules
• Ports (cont.)
The port declaration syntax is :
input [range_val:range_var] list_of_identifiers;
output [range_val:range_var] list_of_identifiers;
inout [range_val:range_var] list_of_identifiers;
Example
Note: As a good coding practice, there should be
only one port identifier per line.
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Modules
• Ports (cont.)
A complete example in Verilog
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Modules
• Ports (cont.) - Modules connected by port order (implicit)
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Modules
• Ports (cont.) - Modules connected by name (explicit)
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Modules
• Instantiating a module
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Modules
• Port Connection Rules
Inputs: internally must always be of type net, externally the
inputs can be connected to a variable of type reg or net.
Outputs: internally can be of type net or reg, externally the
outputs must be connected to a variable of type net.
Inouts: internally or externally must always be type net, can
only be connected to a variable net type.
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Modules
• Port Connection Rules (cont.)
Width matching: It is legal to connect internal and
external ports of different sizes. But beware,
synthesis tools could report problems.
Unconnected ports: unconnected ports are allowed
by using a “,”.
The net data types are used to connect structure.
A net data type is required if a signal can be driven
a structural connection.
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Modules
• Implicit Unconnected Port
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Modules
• Explicit Unconnected Port
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Hierarchical Identifiers
• Hierarchical path names are based on the top module
identifier followed by module instant identifiers,
separated by periods.
• This is useful basically when we want to see the
signal inside a lower module, or want to force a value
inside an internal module. The example below shows
how to monitor the value of an internal module signal.
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Hierarchical Identifiers
• adder_hier
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Data Types
• Verilog language has two primary data types:
Nets - represent structural connections between
components.
Registers - represent variables used to store data.
• Every signal has a data type associated with it:
Explicitly declared with a declaration in your Verilog code.
Implicitly declared with no declaration when used to
connect structural building blocks in your code. Implicit
declaration is always a net type “wire” and is one bit wide.
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Data Types
• Types of Nets
Each net type has a functionality that is used to model
different types of hardware (such as PMOS, NMOS, CMOS,
etc.)
Note: Of all net types, wire is the one which is most widely used.
33
Data Types
• Example - wor
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Data Types
• Example - wand
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Data Types
• Example - tri
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Data Types
• Example - trireg
37
Data Types
• Register Data Types
Registers store the last value assigned to them until another
assignment statement changes their value.
Registers represent data storage constructs.
You can create regs arrays called memories.
Register data types are used as variables in procedural
blocks.
A register data type is required if a signal is assigned a
value within a procedural block
Procedural blocks begin with keyword initial and always.
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Data Types
• Register Data Types (cont.)
Note : Of all register types, reg is the one which is
most widely used.
39
Data Types
• Strings
A string is a sequence of characters enclosed by double
quotes and all contained on a single line. Strings used as
operands in expressions and assignments are treated as a
sequence of eight-bit ASCII values, with one eight-bit ASCII
value representing one character.
To declare a variable to store a string, declare a register
large enough to hold the maximum number of characters the
variable will hold. Note that no extra bits are required to
hold a termination character; Verilog does not store a
string termination character.
Strings can be manipulated using the standard operators.
40
Data Types
• Strings (cont.)
When a variable is larger than required to hold a
value being assigned, Verilog pads the contents on
the left with zeros after the assignment. This is
consistent with the padding that occurs during
assignment of non-string values.
Certain characters can be used in strings only
when preceded by an introductory character called
an escape character.
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Data Types
• Strings (cont.)
The following table lists these characters in the
right-hand column together with the escape
sequence that represents the character in the left-
hand column.
Special characters in strings
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Data Types
• A sample string
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The End
