11 Memory Hierarchy

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The Memory Hierarchy

15-213: Introduction to Computer Systems
11th Lecture, Oct. 6, 2015
Instructors:
Randal E. Bryant and David. R. O’Hallaron
Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 1

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Today
 Storage technologies and trends
 Locality of reference
 Caching in the memory hierarchy

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Random-Access Memory (RAM)

 Key features
▪ RAM is traditionally packaged as a chip.
▪ Basic storage unit is normally a cell (one bit per cell).
▪ Multiple RAM chips form a memory.
 RAM comes in two varieties:

▪ SRAM (Static RAM)
▪ DRAM (Dynamic RAM)

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SRAM vs DRAM Summary
Trans. Access Needs Needs

per bit time refresh? EDC? Cost Applications
SRAM 4 or 6 1X No Maybe 100x Cache memories
DRAM 1 10X Yes Yes 1X Main memories,

frame buffers

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Nonvolatile Memories
 DRAM and SRAM are volatile memories
▪ Lose information if powered off.
 Nonvolatile memories retain value even if powered off
▪ Read-only memory (ROM): programmed during production
▪ Programmable ROM (PROM): can be programmed once
▪ Eraseable PROM (EPROM): can be bulk erased (UV, X-Ray)
▪ Electrically eraseable PROM (EEPROM): electronic erase capability
▪ Flash memory: EEPROMs. with partial (block-level) erase capability
▪ Wears out after about 100,000 erasings
 Uses for Nonvolatile Memories
▪ Firmware programs stored in a ROM (BIOS, controllers for disks,
network cards, graphics accelerators, security subsystems,…)
▪ Solid state disks (replace rotating disks in thumb drives, smart
phones, mp3 players, tablets, laptops,…)
▪ Disk caches
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Traditional Bus Structure Connecting

CPU and Memory
 A bus is a collection of parallel wires that carry address,
data, and control signals.
 Buses are typically shared by multiple devices.
CPU chip
Register file
ALU
System bus Memory bus
I/O Main
Bus interface
bridge memory

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Memory Read Transaction (1)

 CPU places address A on the memory bus.
Register file Load operation: movq A, %rax
ALU
%rax
Main memory
I/O bridge 0
A
Bus interface x A

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 Main memory reads A from the memory bus, retrieves
word x, and places it on the bus.
Register file
Load operation: movq A, %rax
ALU
%rax
Main memory
I/O bridge x 0
Bus interface x A

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 CPU read word x from the bus and copies it into register
%rax.
Register file Load operation: movq A, %rax
ALU
%rax x
Main memory
I/O bridge 0
Bus interface x A

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Memory Write Transaction (1)

 CPU places address A on bus. Main memory reads it and
waits for the corresponding data word to arrive.
Register file Store operation: movq %rax, A
ALU
%rax y
Main memory
I/O bridge 0
A
Bus interface A

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 CPU places data word y on the bus.
Register file Store operation: movq %rax, A
ALU
%rax y
Main memory
I/O bridge 0
y
Bus interface A

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 Main memory reads data word y from the bus and stores
it at address A.
Register file
Store operation: movq %rax, A
ALU
%rax y
main memory
I/O bridge 0
Bus interface y A

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What’s Inside A Disk Drive?

Spindle
Arm Platters
Actuator
Electronics
(including a
processor
SCSI and memory!)
connector
Image courtesy of Seagate Technology
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Disk Geometry
 Disks consist of platters, each with two surfaces.
 Each surface consists of concentric rings called tracks.
 Each track consists of sectors separated by gaps.
Tracks
Surface
Track k Gaps
Spindle
Sectors
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Disk Geometry (Muliple-Platter View)

 Aligned tracks form a cylinder.
Cylinder k
Surface 0
Platter 0
Surface 1
Surface 2
Platter 1
Surface 3
Surface 4
Platter 2
Surface 5
Spindle

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Disk Capacity
 Capacity: maximum number of bits that can be stored.
▪ Vendors express capacity in units of gigabytes (GB), where
1 GB = 109 Bytes.
 Capacity is determined by these technology factors:
▪ Recording density (bits/in): number of bits that can be squeezed
into a 1 inch segment of a track.
▪ Track density (tracks/in): number of tracks that can be squeezed
into a 1 inch radial segment.
▪ Areal density (bits/in2): product of recording and track density.

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Recording zones
 Modern disks partition tracks
into disjoint subsets called
recording zones
…
▪ Each track in a zone has the same
number of sectors, determined
by the circumference of
innermost track. Spindle
▪ Each zone has a different number
of sectors/track, outer zones
have more sectors/track than
inner zones.
▪ So we use average number of
sectors/track when computing
capacity.

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Computing Disk Capacity

Capacity = (# bytes/sector) x (avg. # sectors/track) x
(# tracks/surface) x (# surfaces/platter) x
(# platters/disk)
Example:
▪ 512 bytes/sector
▪ 300 sectors/track (on average)
▪ 20,000 tracks/surface
▪ 2 surfaces/platter
▪ 5 platters/disk
Capacity = 512 x 300 x 20000 x 2 x 5

= 30,720,000,000
= 30.72 GB

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Disk Operation (Single-Platter View)
The disk surface

The read/write head
spins at a fixed
is attached to the end
rotational rate
of the arm and flies over
the disk surface on
a thin cushion of air.
spindle
spindle
spindle
spindle
By moving radially, the arm can

position the read/write head over
any track.

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Disk Operation (Multi-Platter View)

Read/write heads
move in unison
from cylinder to cylinder
Arm
Spindle

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Disk Structure - top view of single platter
Surface organized into tracks
Tracks divided into sectors

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Disk Access
Head in position above a track

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Disk Access
Rotation is counter-clockwise

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Disk Access – Read
About to read blue sector

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After BLUE read
After reading blue sector

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After BLUE read
Red request scheduled next

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Disk Access – Seek
After BLUE read Seek for RED
Seek to red’s track

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Disk Access – Rotational Latency
After BLUE read Seek for RED Rotational latency
Wait for red sector to rotate around

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After BLUE read Seek for RED Rotational latency After RED read
Complete read of red

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Disk Access – Service Time Components
After BLUE read Seek for RED Rotational latency After RED read
Data transfer Seek Rotational Data transfer

latency

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Disk Access Time

 Average time to access some target sector approximated by :
▪ Taccess = Tavg seek + Tavg rotation + Tavg transfer
 Seek time (Tavg seek)
▪ Time to position heads over cylinder containing target sector.
▪ Typical Tavg seek is 3—9 ms
 Rotational latency (Tavg rotation)
▪ Time waiting for first bit of target sector to pass under r/w head.
▪ Tavg rotation = 1/2 x 1/RPMs x 60 sec/1 min
▪ Typical Tavg rotation = 7200 RPMs
 Transfer time (Tavg transfer)
▪ Time to read the bits in the target sector.
▪ Tavg transfer = 1/RPM x 1/(avg # sectors/track) x 60 secs/1 min.

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Disk Access Time Example

 Given:
▪ Rotational rate = 7,200 RPM
▪ Average seek time = 9 ms.
▪ Avg # sectors/track = 400.
 Derived:
▪ Tavg rotation = 1/2 x (60 secs/7200 RPM) x 1000 ms/sec = 4 ms.
▪ Tavg transfer = 60/7200 RPM x 1/400 secs/track x 1000 ms/sec = 0.02 ms
▪ Taccess = 9 ms + 4 ms + 0.02 ms
 Important points:
▪ Access time dominated by seek time and rotational latency.
▪ First bit in a sector is the most expensive, the rest are free.
▪ SRAM access time is about 4 ns/doubleword, DRAM about 60 ns
▪ Disk is about 40,000 times slower than SRAM,
▪ 2,500 times slower then DRAM.
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Logical Disk Blocks

 Modern disks present a simpler abstract view of the
complex sector geometry:
▪ The set of available sectors is modeled as a sequence of b-sized
logical blocks (0, 1, 2, ...)
 Mapping between logical blocks and actual (physical)
sectors
▪ Maintained by hardware/firmware device called disk controller.
▪ Converts requests for logical blocks into (surface,track,sector)
triples.
 Allows controller to set aside spare cylinders for each
zone.
▪ Accounts for the difference in “formatted capacity” and “maximum
capacity”.

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I/O Bus
CPU chip
Register file
ALU
System bus Memory bus
I/O Main
Bus interface
bridge memory
I/O bus Expansion slots for

other devices such
USB Graphics Disk as network adapters.
controller adapter controller
Mouse Keyboard Monitor

Disk
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Reading a Disk Sector (1)

CPU chip
Register file
CPU initiates a disk read by writing a
command, logical block number, and
ALU destination memory address to a port
(address) associated with disk controller.
Main
Bus interface
memory
I/O bus
USB Graphics Disk

mouse keyboard Monitor

Disk
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CPU chip
Register file Disk controller reads the sector and
performs a direct memory access
ALU
(DMA) transfer into main memory.
Main
Bus interface
memory
I/O bus
USB Graphics Disk


Disk
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CPU chip
When the DMA transfer completes,
Register file
the disk controller notifies the CPU
ALU with an interrupt (i.e., asserts a
special “interrupt” pin on the CPU)
Main
Bus interface
memory
I/O bus
USB Graphics Disk


Disk
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Solid State Disks (SSDs)

I/O bus
Requests to read and

write logical disk blocks
Solid State Disk (SSD)
Flash
translation layer
Flash memory
Block 0 Block B-1
Page 0 Page 1 … Page P-1 … Page 0 Page 1 … Page P-1
 Pages: 512KB to 4KB, Blocks: 32 to 128 pages

 Data read/written in units of pages.
 Page can be written only after its block has been erased
 A block wears out after about 100,000 repeated writes.
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SSD Performance Characteristics
Sequential read tput 550 MB/s Sequential write tput 470 MB/s
Random read tput 365 MB/s Random write tput 303 MB/s
Avg seq read time 50 us Avg seq write time 60 us
 Sequential access faster than random access

▪ Common theme in the memory hierarchy
 Random writes are somewhat slower
▪ Erasing a block takes a long time (~1 ms)
▪ Modifying a block page requires all other pages to be copied to
new block
▪ In earlier SSDs, the read/write gap was much larger.
Source: Intel SSD 730 product specification.

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SSD Tradeoffs vs Rotating Disks

 Advantages
▪ No moving parts → faster, less power, more rugged
 Disadvantages
▪ Have the potential to wear out
Mitigated by “wear leveling logic” in flash translation layer
▪
▪ E.g. Intel SSD 730 guarantees 128 petabyte (128 x 1015 bytes) of
writes before they wear out
▪ In 2015, about 30 times more expensive per byte
 Applications
▪ MP3 players, smart phones, laptops
▪ Beginning to appear in desktops and servers

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The CPU-Memory Gap

The gap between DRAM, disk, and CPU speeds.
100,000,000.0
10,000,000.0 Disk
1,000,000.0
100,000.0
SSD
10,000.0 Disk seek time

Time (ns)
SSD access time

1,000.0 DRAM access time
SRAM access time
100.0 DRAM
CPU cycle time
10.0 Effective CPU cycle time
1.0
0.1
CPU
0.0
1985 1990 1995 2000 2003 2005 2010 2015
Year

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Locality to the Rescue!
The key to bridging this CPU-Memory gap is a fundamental

property of computer programs known as locality

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Today

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Locality
 Principle of Locality: Programs tend to use data and
instructions with addresses near or equal to those they
have used recently
 Temporal locality:
▪ Recently referenced items are likely
to be referenced again in the near future
 Spatial locality:
▪ Items with nearby addresses tend
to be referenced close together in time

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Locality Example
sum = 0;
for (i = 0; i < n; i++)
sum += a[i];
return sum;
 Data references
▪ Reference array elements in succession
(stride-1 reference pattern). Spatial locality
▪ Reference variable sum each iteration. Temporal locality
 Instruction references
▪ Reference instructions in sequence. Spatial locality
▪ Cycle through loop repeatedly. Temporal locality

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Qualitative Estimates of Locality

 Claim: Being able to look at code and get a qualitative
sense of its locality is a key skill for a professional
programmer.
 Question: Does this function have good locality with

respect to array a?
int sum_array_rows(int a[M][N])

{
int i, j, sum = 0;
for (i = 0; i < M; i++)

for (j = 0; j < N; j++)
sum += a[i][j];
return sum;
}
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Locality Example
 Question: Does this function have good locality with
respect to array a?
int sum_array_cols(int a[M][N])

{
int i, j, sum = 0;
for (j = 0; j < N; j++)

for (i = 0; i < M; i++)
sum += a[i][j];
return sum;
}

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Locality Example
 Question: Can you permute the loops so that the function
scans the 3-d array a with a stride-1 reference pattern
(and thus has good spatial locality)?
int sum_array_3d(int a[M][N][N])

{
int i, j, k, sum = 0;
for (i = 0; i < M; i++)

for (j = 0; j < N; j++)
for (k = 0; k < N; k++)
sum += a[k][i][j];
return sum;
}

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Memory Hierarchies
 Some fundamental and enduring properties of hardware
and software:
▪ Fast storage technologies cost more per byte, have less capacity,
and require more power (heat!).
▪ The gap between CPU and main memory speed is widening.
▪ Well-written programs tend to exhibit good locality.
 These fundamental properties complement each other

beautifully.
 They suggest an approach for organizing memory and

storage systems known as a memory hierarchy.

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Today

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Example Memory
Hierarchy L0:
Regs CPU registers hold words
Smaller, retrieved from the L1 cache.
faster, L1: L1 cache
and (SRAM) L1 cache holds cache lines
costlier retrieved from the L2 cache.
L2: L2 cache
(per byte)
(SRAM)
storage L2 cache holds cache lines
devices retrieved from L3 cache
L3: L3 cache
(SRAM)
L3 cache holds cache lines
retrieved from main memory.
Larger,
slower, L4: Main memory
and (DRAM) Main memory holds
cheaper disk blocks retrieved
(per byte) from local disks.
storage L5: Local secondary storage
devices (local disks)
Local disks hold files
retrieved from disks
on remote servers
L6: Remote secondary storage
(e.g., Web servers)
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Caches
 Cache: A smaller, faster storage device that acts as a staging
area for a subset of the data in a larger, slower device.
 Fundamental idea of a memory hierarchy:
▪ For each k, the faster, smaller device at level k serves as a cache for the
larger, slower device at level k+1.
 Why do memory hierarchies work?
▪ Because of locality, programs tend to access the data at level k more
often than they access the data at level k+1.
▪ Thus, the storage at level k+1 can be slower, and thus larger and
cheaper per bit.
 Big Idea: The memory hierarchy creates a large pool of
storage that costs as much as the cheap storage near the
bottom, but that serves data to programs at the rate of the
fast storage near the top.
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General Cache Concepts
Smaller, faster, more expensive

Cache 8
4 9 14
10 3 memory caches a subset of
the blocks
Data is copied in block-sized

10
4 transfer units
Larger, slower, cheaper memory

Memory 0 1 2 3 viewed as partitioned into “blocks”
4 5 6 7
8 9 10 11
12 13 14 15

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General Cache Concepts: Hit

Request: 14 Data in block b is needed
Block b is in cache:
Cache 8 9 14 3
Hit!
Memory 0 1 2 3
4 5 6 7
8 9 10 11
12 13 14 15

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General Cache Concepts: Miss

Request: 12 Data in block b is needed
Block b is not in cache:

Cache 8 9
12 14 3
Miss!
Block b is fetched from

12 Request: 12
memory
Block b is stored in cache

Memory 0 1 2 3 • Placement policy:
4 5 6 7 determines where b goes
• Replacement policy:
8 9 10 11
determines which block
12 13 14 15 gets evicted (victim)

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General Caching Concepts:

Types of Cache Misses
 Cold (compulsory) miss
▪ Cold misses occur because the cache is empty.
 Conflict miss
▪ Most caches limit blocks at level k+1 to a small subset (sometimes a
singleton) of the block positions at level k.
▪ E.g. Block i at level k+1 must be placed in block (i mod 4) at level k.
▪ Conflict misses occur when the level k cache is large enough, but multiple
data objects all map to the same level k block.
▪ E.g. Referencing blocks 0, 8, 0, 8, 0, 8, ... would miss every time.
 Capacity miss
▪ Occurs when the set of active cache blocks (working set) is larger than
the cache.

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Examples of Caching in the Mem. Hierarchy

Cache Type What is Cached? Where is it Cached? Latency (cycles) Managed By
Registers 4-8 bytes words CPU core 0 Compiler

TLB Address translations On-Chip TLB 0 Hardware
MMU
L1 cache 64-byte blocks On-Chip L1 4 Hardware
L2 cache 64-byte blocks On-Chip L2 10 Hardware
Virtual Memory 4-KB pages Main memory 100 Hardware + OS
Buffer cache Parts of files Main memory 100 OS
Disk cache Disk sectors Disk controller 100,000 Disk firmware
Network buffer Parts of files Local disk 10,000,000 NFS client
cache
Browser cache Web pages Local disk 10,000,000 Web browser
Web cache Web pages Remote server disks 1,000,000,000 Web proxy
server
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Summary
 The speed gap between CPU, memory and mass storage
continues to widen.
 Well-written programs exhibit a property called locality.
 Memory hierarchies based on caching close the gap by

exploiting locality.

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Supplemental slides

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Conventional DRAM Organization

 d x w DRAM:
▪ dw total bits organized as d supercells of size w bits
16 x 8 DRAM chip
cols
0 1 2 3
2 bits 0
/
addr
1
rows
Memory supercell
2
controller (2,1)
(to/from CPU)
3
8 bits
/
data
Internal row buffer

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Reading DRAM Supercell (2,1)

Step 1(a): Row access strobe (RAS) selects row 2.
Step 1(b): Row 2 copied from DRAM array to row buffer.
16 x 8 DRAM chip
Cols
0 1 2 3
RAS = 2
2
/ 0
addr
1
Rows
Memory
controller 2
8 3
/
data
Internal row buffer

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Reading DRAM Supercell (2,1)

Step 2(a): Column access strobe (CAS) selects column 1.
Step 2(b): Supercell (2,1) copied from buffer to data lines, and eventually
back to the CPU.
16 x 8 DRAM chip
Cols
0 1 2 3
CAS = 1
2
/ 0
addr
To CPU 1
Rows
Memory
controller 2
supercell 3
8
(2,1) /
data
supercell
Internal row buffer
(2,1)
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Memory Modules
addr (row = i, col = j)
: supercell (i,j)
DRAM 0
64 MB
memory module
DRAM 7
consisting of
eight 8Mx8 DRAMs
bits bits bits bits bits bits bits bits

56-63 48-55 40-47 32-39 24-31 16-23 8-15 0-7
63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0
Memory
controller
64-bit word main memory address A
64-bit word

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Enhanced DRAMs
 Basic DRAM cell has not changed since its invention in 1966.
▪ Commercialized by Intel in 1970.
 DRAM cores with better interface logic and faster I/O :
▪ Synchronous DRAM (SDRAM)
▪ Uses a conventional clock signal instead of asynchronous control
▪ Allows reuse of the row addresses (e.g., RAS, CAS, CAS, CAS)
▪ Double data-rate synchronous DRAM (DDR SDRAM)

▪ Double edge clocking sends two bits per cycle per pin
▪ Different types distinguished by size of small prefetch buffer:
– DDR (2 bits), DDR2 (4 bits), DDR3 (8 bits)
▪ By 2010, standard for most server and desktop systems
▪ Intel Core i7 supports only DDR3 SDRAM

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Storage Trends
SRAM
Metric 1985 1990 1995 2000 2005 2010 2015 2015:1985
$/MB 2,900 320 256 100 75 60 320 116

access (ns) 150 35 15 3 2 1.5 200 115
DRAM
Metric 1985 1990 1995 2000 2005 2010 2015 2015:1985
$/MB 880 100 30 1 0.1 0.06 0.02 44,000

access (ns) 200 100 70 60 50 40 20 10
typical size (MB) 0.256 4 16 64 2,000 8,000 16.000 62,500
Disk
Metric 1985 1990 1995 2000 2005 2010 2015 2015:1985
$/GB 100,000 8,000 300 10 5 0.3 0.03 3,333,333

access (ms) 75 28 10 8 5 3 3 25
typical size (GB) 0.01 0.16 1 20 160 1,500 3,000 300,000
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CPU Clock Rates Inflection point in computer history

when designers hit the “Power Wall”
1985 1990 1995 2003 2005 2010 2015 2015:1985
CPU 80286 80386 Pentium P-4 Core 2 Core i7(n) Core i7(h)
Clock
rate (MHz) 6 20 150 3,300 2,000 2,500 3,000 500
Cycle
time (ns) 166 50 6 0.30 0.50 0.4 0.33 500
Cores 1 1 1 1 2 4 4 4
Effective
cycle 166 50 6 0.30 0.25 0.10 0.08 2,075
time (ns)
(n) Nehalem processor

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition (h) Haswell processor 66

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Carnegie Mellon

The Memory Hierarchy

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 1

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 2

Random-Access Memory (RAM)

 RAM comes in two varieties:

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 3

SRAM vs DRAM Summary

Trans. Access Needs Needs

SRAM 4 or 6 1X No Maybe 100x Cache memories

DRAM 1 10X Yes Yes 1X Main memories,

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 4

Traditional Bus Structure Connecting

System bus Memory bus

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 6

Memory Read Transaction (1)

Register file Load operation: movq A, %rax

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 7

Memory Read Transaction (2)

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 8

Memory Read Transaction (3)

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 9

Memory Write Transaction (1)

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 10

Memory Write Transaction (2)

Register file Store operation: movq %rax, A

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 11

Memory Write Transaction (3)

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 12

What’s Inside A Disk Drive?

Disk Geometry (Muliple-Platter View)

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 15

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 16

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 17

Computing Disk Capacity

Capacity = 512 x 300 x 20000 x 2 x 5

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 18

Disk Operation (Single-Platter View)

The disk surface

By moving radially, the arm can

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 19

Disk Operation (Multi-Platter View)

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 20

Disk Structure - top view of single platter

Surface organized into tracks

Tracks divided into sectors

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 21

Head in position above a track

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 22

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 23

Disk Access – Read

About to read blue sector

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 24

Disk Access – Read

After BLUE read

After reading blue sector

Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 25

Disk Access – Read

After BLUE read