Memory: It Is A Storage Device Used To Hold The Input and Data
Memory: It Is A Storage Device Used To Hold The Input and Data
Memory: It Is A Storage Device Used To Hold The Input and Data
CPU chip
register file
ALU
I/O main
bus interface
bridge memory
Memory Read Transaction (1)
ALU
B
main memory
I/O bridge 0
bus interface x M
Memory Read Transaction (2)
• Main memory reads M from the memory bus, retrieves word
x, and places it on the bus.
register file
Load operation: mov B, M
ALU
B
main memory
I/O bridge x 0
bus interface x M
Memory Read Transaction (3)
• CPU read word x from the bus and copies it into register
%eax.
register file
Load operation: mov B, M
ALU
B x
main memory
I/O bridge 0
bus interface x M
Memory Write Transaction (1)
• CPU places address M on bus. Main memory reads it and
waits for the corresponding data word to arrive.
register file Store operation: mov M, B
ALU
B y
main memory
I/O bridge 0
M
bus interface M
Memory Write Transaction (2)
ALU
B y
main memory
I/O bridge 0
y
bus interface M
Memory Write Transaction (3)
• Main memory read data word y from the bus and stores it at
address A.
register file Store operation: mov M, B
ALU
B y
main memory
I/O bridge 0
bus interface y M
CPU chip
Reading a Disk Sector (1)
CPU initiates a disk read by writing a
register file
command, logical block number, and
• ALU
destination memory address to a port
(address) associated with disk controller.
main
bus interface
memory
I/O bus
main
bus interface
memory
I/O bus
main
bus interface
memory
I/O bus
• Modern disks partition tracks into disjoint subsets called recording zones
– Each track in a zone has the same number of sectors, determined by the
circumference of innermost track.
– Each zone has a different number of sectors/track
Computing Disk Capacity
• Capacity = (# bytes/sector) x (avg. # sectors/track) x
• (# tracks/surface) x (# surfaces/platter) x
• (# platters/disk)
• Example:
– 512 bytes/sector
– 300 sectors/track (on average)
– 20,000 tracks/surface
– 2 surfaces/platter
– 5 platters/disk
• Organization
Module characteristics
• Capacity (Number of DRAM Devices)
• ECC vs non-ECC Modules that have error correcting code are labeled as ECC. Modules without error
correcting code are labeled non-ECC.
• Number of DRAM Ranks (also known as rows or sides) Any given module can have 1, 2, or 4 ranks,
but only 1 rank of a module can be active at any moment in time. When a module has two or more ranks, the
memory controller must periodically switch between them by performing close and open operations.
• Timings latency, clock cycle time, row cycle time, refresh row cycle time, row active time
• Buffering
• Packaging
• Power consumption
Caching in a Memory Hierarchy
Level k: 48 9 14
10 3
0 1 2 3
Level k+1: 4 5 6 7
8 9 10 11
12 13 14 15
General Caching Concepts
• Program needs object d, which is stored in
Request
14
12 some block b.
12
14
0 1 2 3
• Cache hit
Level 4*
12 9 14 3 – Program finds b in the cache at level k. E.g.,
k: block 14.
• Cache miss
12
4* Request
12 – b is not at level k, so level k cache must fetch
it from level k+1. E.g., block 12.
– If level k cache is full, then some current block
0 1 2 3
must be replaced (evicted). Which one is the
“victim”?
Level 4
4* 5 6 7
k+1: 8 9 10 11
12 13 14 15
General Caching Concepts
• Types of cache misses:
– Cold (compulsory) miss
• Cold misses occur because the cache is empty.
– Conflict miss
• Conflict misses occur when the level k cache is large enough,
but multiple data objects all map to the same level k block.
• E.g. Referencing blocks 0, 8, 0, 8, 0, 8, ... would miss every
time.
– Capacity miss
• Occurs when the set of active cache blocks (working set) is
larger than the cache.