19-0283; Rev 4; 5/98

KIT
ATION
EVALU B L E
AVAILA

Low-Cost, 2-Channel, ±14-Bit Serial ADCs

_______________General Description ____________________________Features

MAX110/MAX111
The MAX110/MAX111 analog-to-digital converters ♦ Single +5V Supply (MAX111)
(ADCs) use an internal auto-calibration technique to ♦ Two Differential Input Channels
achieve 14-bit resolution plus overrange, with no exter- ♦ 14-Bit Resolution Plus Sign and Overrange
nal components. Operating supply current is only
♦ 0.03% Linearity (MAX110)
550µA (MAX110) and reduces to 4µA in power-down 0.05% Linearity (MAX111)
mode, making these ADCs ideal for high-resolution bat-
tery-powered or remote-sensing applications. A fast ♦ Low Power Consumption:
550µA (MAX110)
serial interface simplifies signal routing and opto-isola- 640µA (MAX111)
tion, saves microcontroller pins, and offers compatibility 4µA Shutdown Current
with SPI™, QSPI™, and Microwire™. The MAX110
♦ Up to 50 Conversions/sec
operates with ±5V supplies, and converts differential
analog signals in the -3V to +3V range. The MAX111 ♦ 50Hz/60Hz Rejection
operates with a single +5V supply and converts differ- ♦ Auto-Calibration Mode
ential analog signals in the ±1.5V range, or single- ♦ No External Components Required
ended signals in the 0V to +1.5V range. ♦ 16-Pin DIP/SO, 20-Pin SSOP
Internal calibration allows for both offset and gain-error
correction under microprocessor (µP) control. Both ______________Ordering Information
devices are available in space-saving 16-pin DIP and
PART TEMP. RANGE PIN-PACKAGE INL(%)
SO packages, as well as an even smaller 20-pin SSOP
package. MAX110ACPE 0°C to +70°C 16 Plastic DIP ±0.03
MAX110BCPE 0°C to +70°C 16 Plastic DIP ±0.05
________________________Applications MAX110ACWE 0°C to +70°C 16 Wide SO ±0.03
Process Control MAX110BCWE 0°C to +70°C 16 Wide SO ±0.05
Weigh Scales MAX110ACAP 0°C to +70°C 20 SSOP ±0.03
Panel Meters MAX110BCAP 0°C to +70°C 20 SSOP ±0.05
MAX110BC/D 0°C to +70°C Dice* ±0.05
Data-Acquisition Systems
Ordering Information continued at end of data sheet.
Temperature Measurement * Contact factory for dice specifications.

__________Typical Operating Circuit _________________Pin Configurations

+5V TOP VIEW

VDD IN1+ 1 16 IN1-

IN1+ RCSEL
REF- 2 15 IN2+

REF+ 3 MAX110 14 IN2-

IN1- MAX110 MAX111
IN2+
MAX111 VDD 4 13 VSS (AGND)

IN2- RCSEL 5 12 GND

REF+
XCLK 6 11 DIN
REF-
CS SCLK 7 10 DOUT
SCLK BUSY 8 9 CS
FROM µC
DIN
VSS
(AGND) DOUT DIP/SO
( ) ARE FOR MAX111
( ) ARE FOR MAX111 -5V (0V)
Pin Configurations continued at end of data sheet.
™ SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.

________________________________________________________________ Maxim Integrated Products 1

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
 Low-Cost, 2-Channel, ±14-Bit Serial ADCs
MAX110/MAX111

ABSOLUTE MAXIMUM RATINGS

VDD to GND ...........................................................................+6V 16-Pin Wide SO (derate 9.52mW/°C above +70°C) ......762mW
VSS to GND (MAX110)..............................................+0.3V to -6V 20-Pin SSOP (derate 8.00mW/°C above +70°C) ...........640mW
AGND to DGND.....................................................-0.3V to +0.3V 16-Pin CERDIP (derate 10.00mW/°C above +70°C)......800mW
VIN1+, VIN1- ......................................(VDD + 0.3V) to (VSS - 0.3V) Operating Temperature Ranges
VIN2+, VIN2- ......................................(VDD + 0.3V) to (VSS - 0.3V) MAX11_ _C_ _......................................................0°C to +70°C
VREF+, VREF- ....................................(VDD + 0.3V) to (VSS - 0.3V) MAX11_ _E_ _ ...................................................-40°C to +85°C
Digital Inputs and Outputs .........................(VDD + 0.3V) to -0.3V MAX11_BMJE .................................................-55°C to +125°C
Continuous Power Dissipation Storage Temperature Range .............................-65°C to +160°C
16-Pin Plastic DIP (derate 10.53mW/°C above +70°C).....842mW Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS—MAX110
(VDD = 5V ±5%, VSS = -5V ±5%, fXCLK = 1MHz, ÷ 2 mode (DV2 = 1), 81,920 CLK cycles/conv, VREF+ = 1.5V, VREF- = -1.5V,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ACCURACY (Note 1)
14 + POL
Resolution RES (Note 2) Bits
+ OFL
Differential Nonlinearity DNL (Notes 3, 4) ±2 LSB
No-Missing-Codes 13 + POL
(Note 3) Bits
Resolution + OFL
-VREF ≤ VIN ≤ VREF ±0.03 ±0.06
MAX110AC/E
-0.83 x VREF ≤ VIN ≤ 0.83 x VREF ±0.015 ±0.03
Relative Accuracy -VREF ≤ VIN ≤ VREF ±0.04
INL MAX110BC/E %FSR
(Notes 3, 5–7) -0.83 x VREF ≤ VIN ≤ 0.83 x VREF ±0.018
-VREF ≤ VIN ≤ VREF ±0.1
MAX110BM
-0.83 x VREF ≤ VIN ≤ 0.83 x VREF ±0.05
Offset Error VIN+ = VIN- = 0V ±4 mV
Offset Error After offset null 0.003
µV/°C
Temperature Drift Uncalibrated 0.02
Common-Mode Rejection
CMRR -2.5V ≤ (VIN+ = VIN-) ≤ 2.5V 6 ppm/V
Ratio
After gain calibration (Note 5) ±0.1
Full-Scale Error %
Uncalibrated -8 0
Full-Scale Error
8 ppm/°C
Temperature Drift
VSS = -5V, VDD = 4.75V to 5.25V 15
Power-Supply Rejection ppm
VDD = 5V, VSS = -4.75V to -5.25V 30
ANALOG INPUTS
Differential Input Voltage
VIN (Note 6) -VREF +VREF V
Range
Absolute Input Voltage VIN+, VSS + VDD -
V
Range VIN- 2.25 2.25
Input Bias Current IIN+, IIN- 500 nA
Input Capacitance (Note 3) 10 pF

2 _______________________________________________________________________________________
 Low-Cost, 2-Channel, ±14-Bit Serial ADCs
ELECTRICAL CHARACTERISTICS—MAX110 (continued)

MAX110/MAX111
(VDD = 5V ±5%, VSS = -5V ±5%, fXCLK = 1MHz, ÷ 2 mode (DV2 = 1), 81,920 CLK cycles/conv, VREF+ = 1.5V, VREF- = -1.5V,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

REFERENCE INPUTS
Differential Reference
VREF 0 3.0 V
Input Voltage Range
Absolute Reference Input VREF+, VSS + VDD -
V
Voltage Range VREF- 2.25 2.25
IREF+,
Reference Input Current VREF+ = 2.5V, VREF- = 0V 500 nA
IREF-
Reference Input
(Note 3) 10 pF
Capacitance
CONVERSION TIME
Synchronous Conversion 10,240 clock-cycles/conversion 20.48
tCONV ms
Time (Note 7) 102,400 clock-cycles/conversion 204.80
Oversampling Clock
fOSC (Note 8) 0.25 1.25 MHz
Frequency
DIGITAL INPUTS (CS, SCLK, DIN, and XCLK when RCSEL = 0V)
Input High Voltage VIH 2.4 V
Input Low Voltage VIL 0.8 V
Input Capacitance (Note 3) 10 pF
Input Leakage Current ILKG Digital inputs at 0V or 5V ±1 µA
DIGITAL OUTPUTS (DOUT, BUSY, and XCLK when RCSEL = VDD)
DOUT, BUSY, ISINK = 1.6mA 0.4
Output Low Voltage VOL V
XCLK, ISINK = 200µA 0.4

DOUT, BUSY, VDD = 4.75V, ISOURCE = 1.0mA VDD - 0.5

Output High Voltage VOH V
XCLK, VDD = 4.75V, ISOURCE = 200µA VDD - 0.5
Leakage Current ILKG VOUT = 5V or 0V ±10 µA
Output Capacitance (Note 3) 10 pF
POWER REQUIREMENTS (all digital inputs at 0V or 5V)
Positive Supply Voltage VDD Performance guaranteed by supply rejection test 4.75 5.25 V
Negative Supply Voltage VSS Performance guaranteed by supply rejection test -4.75 -5.25 V
fXCLK = 500kHz,
550 950
continuous-conversion mode
VDD = 5.25V,
Positive Supply Current IDD XCLK unloaded, µA
VSS = -5.25V
continuous-conversion mode, RC 780
oscillator operational (Note 9)
VDD = 5.25V, fXCLK = 500kHz,
Negative Supply Current ISS 320 650 µA
VSS = -5.25V continuous-conversion mode
IDD 4 10
Power-Down Current VDD = 5.25V, VSS = -5.25V, VXCLK = 0V, PD = 1 µA
ISS 0.05 2

_______________________________________________________________________________________ 3
 Low-Cost, 2-Channel, ±14-Bit Serial ADCs
ELECTRICAL CHARACTERISTICS—MAX111
MAX110/MAX111

(VDD = 5V ±5%, fXCLK = 1MHz, ÷ 2 mode (DV2 = 1), 81,920 CLK cycles/conv, VREF+ = 1.5V, VREF- = 0V, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

ACCURACY (Note 1)
14 + POL
Resolution RES (Note 2) Bits
+ OFL
Differential Nonlinearity DNL (Notes 3, 4) ±2 LSB
No-Missing-Codes 13 + POL
(Note 3) Bits
Resolution + OFL
-VREF ≤ VIN ≤ VREF ±0.05 ±0.10
MAX111AC/E
-0.667 x VREF ≤ VIN ≤ 0.667 x VREF ±0.03 ±0.05
Relative Accuracy, -VREF ≤ VIN ≤ VREF ±0.18
Differential Input INL MAX111BC/E %FSR
(Notes 3, 5–7) -0.667 x VREF ≤ VIN ≤ 0.667 x VREF ±0.10
-VREF ≤ VIN ≤ VREF ±0.25
MAX111BM
-0.667 x VREF ≤ VIN ≤ 0.667 x VREF ±0.20
0V ≤ VIN ≤ VREF ±0.1
MAX111AC/E
VIN ≤ 0.667 x VREF ±0.06
Relative Accuracy, 0V ≤ VIN ≤ VREF ±0.18
Single-Ended Input INL MAX111BC/E %FSR
(IN- = GND) VIN ≤ 0.667 x VREF ±0.10
0V ≤ VIN ≤ VREF ±0.25
MAX111BM
VIN ≤ 0.667 x VREF ±0.15
Offset Error VIN+ = VIN- = 0V ±4 mV
Common-Mode Rejection
CMRR 10mV ≤ (VIN+ = VIN-) ≤ 2.0V 6 ppm/V
Ratio
After gain calibration (Note 5) ±0.2
Full-Scale Error %
Uncalibrated -8 0
Full-Scale Error
8 ppm/°C
Temperature Drift

Power-Supply Rejection VDD = 4.75V to 5.25V 15 ppm

ANALOG INPUTS
Differential Input Voltage
VIN (Note 6) -VREF +VREF V
Range
Absolute Input Voltage VIN+,
0 VDD - 3.2 V
Range VIN-
Input Bias Current IIN+, IIN- 500 nA
Input Capacitance (Note 3) 10 pF

4 _______________________________________________________________________________________
 Low-Cost, 2-Channel, ±14-Bit Serial ADCs
ELECTRICAL CHARACTERISTICS—MAX111 (continued)

MAX110/MAX111
(VDD = 5V ±5%, fXCLK = 1MHz, ÷ 2 mode (DV2 = 1), 81,920 CLK cycles/conv, VREF+ = 1.5V, VREF- = 0V, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REFERENCE INPUTS
Differential Reference
VREF 0 1.5 V
Input Voltage Range
Absolute Reference Input VREF+,
0 VDD - 3.2 V
Voltage Range VREF-
IREF+,
Reference Input Current VREF+ = 1.5V, VREF- = 0V 500 nA
IREF-
Reference Input
(Note 3) 10 pF
Capacitance
CONVERSION TIME
Synchronous Conversion 10,240 clock-cycles/conversion 20.48
tCONV ms
Time (Note 7) 102,400 clock-cycles/conversion 204.80
Oversampling Clock
fOSC (Note 8) 0.25 1.25 MHz
Frequency
DIGITAL INPUTS (CS, SCLK, DIN, and XCLK when RCSEL = 0V)
Input High Voltage VIH 2.4 V
Input Low Voltage VIL 0.8 V
Input Capacitance (Note 3) 10 pF
Input Leakage Current ILKG Digital inputs at 0V or 5V ±1 µA
DIGITAL OUTPUTS (DOUT, BUSY, and XCLK when RCSEL = VDD)
DOUT, BUSY, ISINK = 1.6mA 0.4
Output Low Voltage VOL V
XCLK, ISINK = 200µA 0.4

DOUT, BUSY, VDD = 4.75V, ISOURCE = 1.0mA VDD - 0.5

Output High Voltage VOH V
XCLK, VDD = 4.75V, ISOURCE = 200µA VDD - 0.5
Leakage Current ILKG VOUT = 5V or 0V ±1 µA
Output Capacitance (Note 3) 10 pF
POWER REQUIREMENTS (all digital inputs at 0V or 5V)
Positive Supply Voltage VDD Performance guaranteed by supply rejection test 4.75 5.25 V
fXCLK = 500kHz,
640 1200
continuous-conversion mode
Supply Current IDD VDD = 5.25V XCLK unloaded, µA
continuous-conversion mode, RC 960
oscillator operational (Note 9)
Power-Down Current IDD VDD = 5.25V, VXCLK = 0V, PD = 1 4 10 µA

_______________________________________________________________________________________ 5
 Low-Cost, 2-Channel, ±14-Bit Serial ADCs
MAX110/MAX111

Note 1: These specifications apply after auto-null and gain calibration. Performance at power-supply tolerance limits is guaranteed
by power-supply rejection tests. Tests are performed at VDD = 5V and VSS = -5V (MAX110).
Note 2: 32,768 LSBs cover an input voltage range of ±VREF (15 bits). An additional bit (OFL) is set for VIN > VREF.
Note 3: Guaranteed by design. Not subject to production testing.
Note 4: DNL is less than ±2 counts (LSBs) out of 215 counts (±14 bits). The major source of DNL is noise, and this can be further
improved by averaging.
Note 5: See 3-Step Calibration section in text.
Note 6: VREF = (VREF+ - VREF-), VIN = (VIN1+ - VIN1-) or (VIN2+ - VIN2-). The voltage is interpreted as negative when the voltage at
the negative input terminal exceeds the voltage at the positive input terminal.
Note 7: Conversion time is set by control bits CONV1–CONV4.
Note 8: Tested at clock frequency of 1MHz with the divide-by-2 mode (i.e. oversampling clock of 500kHz). See Typical Operating
Characteristics section for the effect of other clock frequencies. Also read the Clock Frequency section.
Note 9: This current depends strongly on CXCLK (see Applications Information section).

TIMING CHARACTERISTICS (see Figure 6)

(VDD = 5V, VSS = -5V (MAX110), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

TA = +25°C 60
CS to SCLK Setup Time
tCSS MAX11_ _C/E 80 ns
(Note 10)
MAX11_ BM 100
CS to SCLK Hold Time
tCSH 0 ns
(Note 10)
TA = +25°C 60
DIN to SCLK Setup Time
tDS MAX11_ _C/E 80 ns
(Note 10)
MAX11_ BM 100
DIN to SCLK Hold Time
tDH 0 ns
(Note 10)
TA = +25°C 100
SCLK, XCLK Pulse Width
tCK MAX11_ _C/E 120 ns
(Note 10)
MAX11_ BM 160
TA = +25°C 0 35 80
Data Access Time
tDA CLOAD = 50pF MAX11_ _C/E 0 100 ns
(Note 10)
MAX11_ BM 0 120
TA = +25°C 0 60 100
SCLK to DOUT Valid
tDO CLOAD = 50pF MAX11_ _C/E 0 120 ns
Delay (Note 10)
MAX11_ BM 0 140
Bus Relinquish Time TA = +25°C 35 80
tDH ns
(Note 10) MAX11_ _C/E/M 120
TA = +25°C 2.0
RC Oscillator Frequency MAX11_ _C/E 1.3 2.8 MHz
MAX11_ BM 1.1 3.0
Note 10: Timing specifications are sample tested at +25°C to ensure compliance. All input control signals are specified
with tr = tf = 5ns (10% to 90% of +5V) and timed from a +1.6V voltage level.

6 _______________________________________________________________________________________
 ,
 ,

Low-Cost, 2-Channel, ±14-Bit Serial ADCs
__________________________________________Typical Operating Characteristics

MAX110/MAX111
(MAX110, VDD = 5V, VSS = -5V, VREF+ = 1.5V, VREF- = -1.5V, differential input (VIN+ = -VIN-), fXCLK = 1MHz, ÷ 2 mode (DV2 = 1),
81,920 clocks/conv, TA = +25°C, unless otherwise noted.)

MAX110 RELATIVE ACCURACY MAX110 RELATIVE ACCURACY

(-0.83 VREF < VIN < 0.83 VREF) (-VREF < VIN < VREF)
0.10 0.10

MAX110 toc01
MAX110 toc02
-40°C ≤ TA ≤ +85°C -40°C ≤ TA ≤ +85°C
RANGE OF INL VALUES RANGE OF INL VALUES

RELATIVE ACCURANCY (%FSR)

RELATIVE ACCURANCY (%FSR)

(200 PIECE SAMPLE SIZE) (200 PIECE SAMPLE SIZE)

0.05 0.05

0 0

-0.05 -0.05

-0.10 -0.10
-4 -2 0 2 4 -4 -2 0 2 4
VIN (V) VIN (V)

MAX110 RELATIVE ACCURACY vs. MAX110 RELATIVE ACCURACY

OVERSAMPLING FREQUENCY (fOSC) vs. TEMPERATURE
0.07 0.10
MAX110-TOC03

MAX110-TOC04
VDD = 4.75V
0.06 VSS = -4.75V
RELATIVE ACCURACY (%FSR)

RELATIVE ACCURACY (%FSR)

TA = +85°C 0.08
0.05

0.04 ÷1 MODE 0.06

0.03
÷2 MODE 0.04
0.02
0.02
0.01
÷ 4 MODE
0 0
0 0.25 0.50 0.75 1.00 1.25 -50 -25 0 25 50 75 100
fOSC (MHz) TEMPERATURE (°C)

MAX110 POWER DISSIPATION vs.

OVERSAMPLING FREQUENCY (fOSC)
8
MAX110-TOC05

VDD = 5.25V
VIN = 0V
7
POWER DISSIPATION (mW)

TA = -40°C

6 ÷ 4 MODE

4 ÷ 2 MODE
÷ 1 MODE
3

2
0 0.25 0.50 0.75 1.00 1.25
fOSC (MHz)

_______________________________________________________________________________________ 7
 Low-Cost, 2-Channel, ±14-Bit Serial ADCs
____________________________Typical Operating Characteristics (continued)
MAX110/MAX111

(MAX111, VDD = 5V, VREF+ = 1.5V, VREF- = 0V, differential input (VIN+ = -VIN-), fXCLK = 1MHz, ÷ 2 mode (DV2 = 1),
81,920 clocks/conv, TA = +25°C, unless otherwise noted.)

MAX111 RELATIVE ACCURACY MAX111 RELATIVE ACCURACY

(-0.667VREF < VIN < 0.667VREF) (-VREF < VIN < VREF)
0.10 0.10

MAX110-TOC7
MAX110-TOC6

RELATIVE ACCURACY (%FSR)

RELATIVE ACCURACY (%FSR)

0.05 0.05

0 0

-0.05 -0.05

-0.10 -0.10
-2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0
VIN (V) VIN (V)

MAX111 RELATIVE ACCURACY vs. MAX111 RELATIVE ACCURACY

OVERSAMPLING FREQUENCY (fOSC) vs. TEMPERATURE
0.14 0.10
MAX110-TOC08

MAX110-TOC09
VDD = 4.75V
0.12 TA = +85°C
RELATIVE ACCURACY (%FSR)

RELATIVE ACCURACY (%FSR)

0.08
0.1

0.08 ÷ 1 MODE 0.06

0.06
0.04
0.04 ÷2 MODE
÷4 MODE 0.02
0.02

0 0
0 0.25 0.50 0.75 1.00 -50 -25 0 25 50 75 100
fOSC (MHz) TEMPERATURE (°C)

MAX111 POWER DISSIPATION vs.

OVERSAMPLING FREQUENCY (fOSC)
7
MAX110-TOC10

VDD = 5.25V
6 VIN = 0V
POWER DISSIPATION (mW)

TA = -40°C
5
÷ 4 MODE
4

3
÷ 1 MODE
2 ÷ 2 MODE

0
0 0.25 0.50 0.75 1.00 1.25
fOSC (MHz)

8 _______________________________________________________________________________________
 Low-Cost, 2-Channel, ±14-Bit Serial ADCs

MAX110/MAX111
______________________________________________________________Pin Description
PIN
NAME FUNCTION
DIP/SO SSOP
1 1 IN1+ Channel 1 Positive Analog Input
2 2 REF- Negative Reference Input
3 3 REF+ Positive Reference Input
4 6 VDD Positive Power-Supply Input—connect to +5V
RC Select Input. Connect to GND to select external clock mode. Connect to VDD to
5 7 RCSEL select RC OSC mode. XCLK must be connected to VDD or GND through a resistor
(1MΩ or less) when RC OSC mode is selected.
Clock Input / RC Oscillator Output. TTL/CMOS-compatible oversampling clock input
when RCSEL = GND. Connects to the internal RC oscillator when RCSEL = VDD. XCLK
6 8 XCLK
must be connected to VDD or GND through a resistor (1MΩ or less) when RC OSC
mode is selected.
7 9 SCLK Serial Clock Input. TTL/CMOS-compatible clock input for serial-interface data I/O.
8 10 BUSY Busy Output. Goes low at conversion start, and returns high at end of conversion.
Chip-Select Input. Pull this input low to perform a control-word-write/data-read opera-
9 11 CS tion. A conversion begins when CS returns high, provided NO-OP is a 1. See the sec-
tion Using the MAX110/MAX111 with SPI, QSPI, and Microwire Serial Interfaces.
10 12 DOUT Serial Data Output. High-impedance when CS is high.
11 13 DIN Serial Data Input. See Control Register section.
12 16 GND Digital Ground
VSS MAX110 Negative Power-Supply Input—connect to -5V
13 17
AGND MAX111 Analog Ground
14 18 IN2- Channel 2 Negative Analog Input
15 19 IN2+ Channel 2 Positive Analog Input
16 20 IN1- Channel 1 Negative Analog Input
— 4, 5, 14, 15 N.C. No Connect—there is no internal connection to this pin

_______________Detailed Description to the ADC. The up/down counter clocks data in from
the comparator at the oversampling clock rate and
The MAX110/MAX111 ADC converts low-frequency
averages the pulse-width-modulated (PWM) square
analog signals to a 16-bit serial digital output (14 data
wave to produce the conversion result. A 16-bit static
bits, a sign bit, and an overrange bit) using a first-order
shift register stores the result at the end of the conver-
sigma-delta loop (Figure 1). The differential input volt-
sion. Figure 2 shows the ADC waveforms for a differen-
age is internally connected to a precision voltage-to-
tial analog input equal to 1/2 (V REF+ - V REF- ). The
current converter. The resulting current is integrated
resulting comparator and 1-bit DAC outputs are high
and applied to a comparator. The comparator output
for seven cycles and low for three cycles of the over-
then drives an up/down counter and a 1-bit DAC. When
sampling clock.
the DAC output is fed back to the integrator input, the
sigma-delta loop is completed. Since the analog input signal is integrated over many
clock cycles, much of the signal and quantization noise
During a conversion, the comparator output is a VREF-
is attenuated. The more clock cycles allowed during
to VREF+ square wave; its duty cycle is proportional to
each conversion, the greater the noise attenuation (see
the magnitude of the differential input voltage applied
Programming Conversion Time).

_______________________________________________________________________________________ 9
 Low-Cost, 2-Channel, ±14-Bit Serial ADCs
MAX110/MAX111

DIN SCLK CS

IN1+ DITHER
GENERATOR
IN1-
IN+ INTEGRATOR
IN2+ INPUT Gm Σ ∫ SERIAL
IN2- MUX IN- UP/DOWN DOUT
SHIFT
- COUNTER REGISTER
REF+
REF- 16 16

CONTROL
REGISTER
16 16
Gm
TIMER + CONTROL BUSY
LOGIC + CLOCK GENERATOR RCSEL
OSC
DIVIDER
NETWORK,
DIVIDE BY XCLK
MAX110 1, 2, OR 4
MAX111
RC
OSCILLATOR

Figure 1. Functional Diagram

Oversampling Clock
XCLK internally connects to a clock-frequency divider VREF+
network, whose output is the ADC oversampling clock, DC LEVEL AT 1/2 VREF
fOSC. This allows the selected clock source (internal RC DIFFERENTIAL
oscillator or external clock applied to XCLK) to be ANALOG
INPUT
divided by one, two, or four (see Clock Divider-Ratio
Control Bits). VREF-

Figure 3 shows the two methods for providing the over- VREF+
sampling clock to the MAX110/MAX111. In external-
clock mode (Figure 3a), the internal RC oscillator is OUTPUT FROM
1-BIT DAC
disabled and XCLK accepts a TTL/CMOS-level clock to
provide the oversampling clock to the ADC.
VREF-
Select external-clock mode (Figure 3a) by connecting
RCSEL to GND and a TTL/CMOS-compatible clock to OVERSAMPLING
XCLK (see Selecting the Oversampling Clock CLOCK
Frequency).
In RC-oscillator mode (Figure 3b), the internal RC oscil-
lator is active and its output is connected to XCLK MAX110
MAX111
(Figure 1). Select RC-oscillator mode by connecting
RCSEL to VDD. This enables the internal oscillator and Figure 2. ADC Waveforms During a Conversion
connects it to XCLK for use by the ADC and external
system components. Minimize the capacitive loading on
XCLK when using the internal RC oscillator.

10 ______________________________________________________________________________________
 Low-Cost, 2-Channel, ±14-Bit Serial ADCs

MAX110/MAX111
+5V
+5V

VDD
VDD
RCSEL
RCSEL

MAX110 MAX110
MAX111 +5V
MAX111
GND
GND
TTL/CMOS
1MΩ
XCLK
XCLK
VSS (AGND)
VSS (AGND)

-5V (0V)
-5V (0V)
( ) ARE FOR MAX111.
( ) ARE FOR MAX111.

Figure 3a. Connection for External-Clock Mode Figure 3b. Connection for Internal RC-Oscillator Mode—XCLK
connects to the internal RC oscillator. Note, the pull-up resistor
is not necessary if the internal oscillator is never shut down.

ADC Operation properly if the reference voltage remains within the rec-
The output data from the MAX110/MAX111 is arranged ommended voltage range (see Reference Inputs). If the
in twos-complement format (Figures 4, 5). The sign bit reference voltage exceeds the recommended input
(POL) is shifted out first, followed by the overrange bit range, the overrange bit may not operate properly.
(OR), and the 14 data bits (MSB first) (see Figure 6).
The MAX110 operates from ±5V power supplies and Digital Interface—Starting a Conversion
converts low-frequency analog signals in the ±3V Data is transferred into and out of the serial I/O shift
range when using the maximum reference voltage of register by pulling CS low and applying a serial clock
VREF = 3V (VREF = VREF+ - VREF-). Within the ±3V input at SCLK. This fully static shift register allows SCLK to
range, greater accuracy is obtained within ±2.5V (see range from DC to 2MHz. Output data from the ADC is
Electrical Characteristics for details). Note that a nega- clocked out on SCLK’s falling edge and should be read
tive input voltage is defined as VIN- > VIN+. For the on SCLK’s rising edge. Input data to the ADC at DIN is
MAX110, the absolute voltage at any analog input pin clocked in on SCLK’s rising edge. A new conversion
must remain within the (VSS + 2.25V) to (VDD - 2.25V) begins when CS returns high, provided the MSB in the
range. input control word (NO-OP) is a 1 (see Using the
MAX110/MAX111 with Microwire, SPI, and QSPI Serial
The MAX111 operates from a single +5V supply and Interfaces). Figure 6 shows the detailed serial-interface
converts low-frequency differential analog signals in the timing diagram.
±1.5V range when using the maximum reference volt-
age of V REF = 1.5V. As indicated in the Electrical CS must remain high during the conversion (while
Characteristics, greater accuracy is achieved within the BUSY remains low). Bringing CS low during the conver-
±1.2V range. The absolute voltage at any analog input sion causes the ADC to stop converting, and may
pin for the MAX111 must remain within 0V to VDD - 3.2V. result in erroneous output data.
When VIN- > VIN+ the input is interpreted as negative. Using the MAX110/MAX111 with SPI, QSPI, and
The overrange bit (OFL) is provided to sense when the Microwire Serial Interfaces
input voltage level has exceeded the reference voltage Figure 7 shows the most common serial-interface con-
level. The converter does not “saturate” until the input nections. The MAX110/MAX111 are compatible with
voltage is typically 20% larger. The linearity is not guar- SPI, QSPI (CPHA = 0, CPOL = 0), and Microwire serial-
anteed in this range. Note that the overrange bit works interface standards.

______________________________________________________________________________________ 11
 Low-Cost, 2-Channel, ±14-Bit Serial ADCs
MAX110/MAX111

OUTPUT
CODE +OVERFLOW
TRANSITION
POL OFL D13...D0
+OVERFLOW 0 1 00 . . .000
0 0 11 . . .111
0 0 11 . . .110
0 0 11 . . .101
0 0 11 . . .100

0 0 00 . . .001
0 0 00 . . .001
0 0 00 . . .000
1 1 11 . . .111
1 1 11 . . .110
-OVERFLOW
TRANSITION
1 1 00 . . .011
1 1 00 . . .010
1 1 00 . . .001
1 1 00 . . .000
-OVERFLOW 1 0 11 . . .111
- VREF VREF -1LSB
INPUT VOLTAGE (LSBs)

Figure 4. Differential Transfer Function

OUTPUT
CODE OVERFLOW
TRANSITION
POL OFL D13...D0
+OVERFLOW 0 1 00 . . .000
0 0 11 . . .111
0 0 11 . . .110
0 0 11 . . .101
0 0 11 . . .100

0 0 00 . . .011
0 0 00 . . .010
0 0 00 . . .001
0 0 00 . . .000
1 1 11 . . .111
0 1 2 3 VREF -1LSB
INPUT VOLTAGE (LSBs)

Figure 5. Unipolar Transfer Function

12 ______________________________________________________________________________________
 Low-Cost, 2-Channel, ±14-Bit Serial ADCs

MAX110/MAX111
CS
tCSH tCK

tCSS
SCLK
tCK
tDH
tDS

DIN MSB LSB

tDO
tDA tDH

DOUT POL OFL MSB DO

BUSY

END OF START OF
CONVERSION CONVERSION

Figure 6. Detailed Serial-Interface Timing

The ADC serial interface operates with just SCLK, DIN,

and DOUT (allow sufficient time for the conversion to
+5V I/O CS complete between read/write operations). Achieve con-
SCK SCLK MAX110 tinuous operation by connecting BUSY to an uncommit-
µP
MISO DOUT MAX111 ted µP I/O or interrupt, to signal the processor when the
MOSI DIN conversion results are ready. Figures 8a and 8b show
SS MASKABLE BUSY the timing for SPI/Microwire and QSPI operation.
INTERRUPT
The fully static 16-bit I/O register allows infinite time
a. SPI/QSPI
between the two 8-bit read/write operations necessary
to obtain the full 16 bits of data with SPI and Microwire.
I/O CS
CS must remain low during the entire two-byte transfer
SK SCLK MAX110 (Figure 8a). QSPI allows a full 16-bit data transfer
µP (Figure 8b).
SI DOUT MAX111
SO DIN
MASKABLE BUSY Interfacing to the 80C32 Microcontroller Family
INTERRUPT or I/O Figure 7c shows the general 80C32 connection to the
MAX110/MAX111 using Port 1. For a more detailed dis-
b. MICROWIRE cussion, see the MAX110 evaluation kit manual.
I/O Shift Register
P1.0 CS Serial data transfer is accomplished with a 16-bit fully
P1.1 SCLK MAX110 static shift register. The 16-bit control word shifted into
µP
P1.2 DIN MAX111 this register during a data-transfer operation controls
P1.3 DOUT
the ADC’s various functions. The MSB (NO-OP)
P1.4 BUSY
enables/disables transfer of the control word within the
ADC. A logic 1 causes the remaining 15 bits in the con-
c. 80C51/80C32 trol word to be transferred from the I/O register into the
control register when CS goes high, updating the
Figure 7. Common Serial-Interface Connections ADC’s configuration and starting a new conversion. If

______________________________________________________________________________________ 13
 Low-Cost, 2-Channel, ±14-Bit Serial ADCs
MAX110/MAX111

1ST BYTE READ/WRITE 2ND BYTE READ/WRITE MAX110

MAX111

BUSY

CS

SCLK

DOUT POL OFL D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DIN NO OP NU NU CONV4 CONV3 CONV2 CONV1 DV4 DV2 NU NU CHS CAL NUL PDX PD

Figure 8a. SPI/Microwire-Interface Timing

MAX110
MAX111
BUSY

CS

SCLK

DOUT POL OFL D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DIN NO OP NU NU CONV4 CONV3 CONV2 CONV1 DV4 DV2 NU NU CHS CAL NUL PDX PD

Figure 8b. QSPI Serial-Interface Timing

14 ______________________________________________________________________________________
 Low-Cost, 2-Channel, ±14-Bit Serial ADCs

MAX110/MAX111
Table 1. Input Control-Word Bit Map
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NO-OP NU NU CONV4 CONV3 CONV2 CONV1 DV4 DV2 NU NU CHS CAL NUL PDX PD

↑
First bit clocked in.
BIT NAME DESCRIPTION
If this bit is a logic high, the remaining 15 LSBs are transferred to the control register and a
new conversion begins when CS returns high. If this bit is set low, the control word is not
15 NO-OP
passed to the control register, the ADC configuration remains unchanged, and no new con-
version begins when CS returns high.
5, 6, 13, 14 NU Used for test purposes only. Set these bits low.
9–12 CONV1–CONV4 Conversion Time Control Bits. See Table 4.
7, 8 DV2, DV4 XCLK to Oversampling Cock Ratio Control Bits. See Table 5.
Input Channel Select. A logic high selects channel 2 (IN2+ and IN2-), while a logic low
4 CHS
selects channel 1 (IN1+ and IN1-). See Tables 2 and 3.
3 CAL Gain-Calibration Bit. A logic high selects gain-calibration mode. See Table 3.
2 NUL Internal Offset-Null Bit. A logic high selects offset-null mode. See Table 3.
1 PDX Oscillator Power-Down. Set this bit high to power down the RC oscillator.
0 PD Analog Power-Down. Set this bit high to power down the analog section.

NO-OP is a zero, the control word is not transferred to When PDX is set high, the internal RC oscillator stops
the control register, the ADC’s configuration remains shortly after CS returns high. If the next control word
unchanged, and no new conversion is initiated. This written to the device has NO-OP = 1 instructing the
allows specific ADCs in a “daisy chain” arrangement to ADC to convert, BUSY will go low, but because the RC
be reconfigured while leaving the remaining ADCs oscillator is stopped, BUSY will remain low and will not
unchanged. Table 1 lists the various ADC control word allow a new conversion to begin. To avoid this situation,
functions. write a “dummy” control word with NO-OP = 0 and any
Output data is shifted out of DOUT at the same time the combination of bits 14-0 in the control word following
input control word for the next conversion is shifted in the control word with PDX = 0. With NO-OP = 0, bits 14-
(Figure 8). 0 are ignored and the internal state machine resets.
Next, perform a normal 3-step calibration (see Table 3).
On power-up, all internal registers reset to zero. Note that XCLK must be connected to V DD or GND
Therefore, when writing the first control word to the through a resistor (suggested value is 1MΩ) when the
ADC, the data simultaneously shifted out will be zeros. RC oscillator mode is selected (RCSEL = VDD). This
The first conversion begins when CS goes high (NO-OP resistor is not necessary if the external oscillator mode
= 1). The results are placed in the 16-bit I/O register for is used, or if the internal oscillator is not shut down.
access on the next data-transfer operation.
Selecting the Analog Inputs
Power-Down Mode Bit 4 (CHS) controls which of the two differential inputs
Bits 0 and 1 control the ADC’s power-down mode. If bit connect to the internal ADC inputs (see the Functional
0 (PD) is a logic high, power is removed from all analog Diagram). A logic high selects IN2+ and IN2- while a
circuitry except the RC oscillator. A logic high at bit 1 logic low selects IN1+ and IN1-. Table 2 shows the
(PDX) removes power from the RC oscillator. If both bits allowable input multiplexer configurations.
PD and PDX are a logic high, or if PD is high and
RCSEL is low, the supply currents reduce to 4µA. If an
external XCLK clock continues to run in power-down
mode, the supply current will depend on the clock rate.

______________________________________________________________________________________ 15
 Low-Cost, 2-Channel, ±14-Bit Serial ADCs
MAX110/MAX111

Table 2. Allowable Input Multiplexer Configurations

CAL NUL CHS NO-OP ADC IN+ ADC IN- DESCRIPTION

0 0 0 1 IN1+ IN1- Channel 1 connected to ADC inputs. Conversion begins when CS returns high.

0 0 1 1 IN2+ IN2- Channel 2 connected to ADC inputs. Conversion begins when CS returns high.

IN1- connected to the ADC inputs; offset-null mode selected. Autonull conversion
0 1 0 1 IN1- IN1-
begins when CS returns high, and the results are stored in the null register.
IN2- connected to the ADC inputs; offset-null mode selected. Autonull conversion
0 1 1 1 IN2- IN2-
begins when CS returns high, and the results are stored in the null register.
REF- connected to the ADC inputs; offset-null mode selected. Autonull conversion
1 1 X 1 REF- REF-
begins when CS returns high, and the results are stored in the null register.

REF+ and REF- connected to the ADC inputs; gain-calibration mode

1 0 X 1 REF+ REF- selected. Autocal conversion begins when CS returns high, and the results are
stored in the 16-bit I/O register.

Input control word is not transferred to the control register. ADC

No No
X X X 0 configuration remains unchanged and no new conversion starts when CS
Change Change
returns high.

X = Don't Care

Table 3. Procedure to Calibrate the ADC

CONTROL WORD
STEP DESCRIPTION Not CONV1- DV2 & Not
NO-OP CHS CAL NUL PDX PD
Used CONV4 DV4 Used
Sets the new conversion speed (if required)
and performs an offset correction conversion
with the internal ADC inputs shorted to REF-. New
1 1 00 XX 00 X 1 1 0 0
The result is stored in the null register. Data
(This step also selects the speed/resolution
for the ADC.)

Performs a gain-calibration conversion with

No
2 the null register contents as the starting value. 1 00 XX 00 X 1 0 0 0
Change
The result is stored in the calibration register.

Performs an offset-null conversion with the

internal ADC inputs shorted to the selected 0
No
3 input channel's negative input (IN1- or IN2-). 1 00 XX 00 or 0 1 0 0
Change
The next operation performs the first signal 1
conversion with the new setup.

X = Don't Care

16 ______________________________________________________________________________________
 Low-Cost, 2-Channel, ±14-Bit Serial ADCs
3-Step Calibration Automatic gain calibration is not allowed in the

MAX110/MAX111
The data sheet electrical specifications apply to the 102,400 cycles per conversion mode (see
device after optional calibration of gain error and offset. Programming Conversion Time). In this mode, calibra-
Uncalibrated, the gain error is typically 2%. tion can be achieved by connecting the reference volt-
Table 3 describes the three steps required to calibrate age to one input channel and performing a normal
the ADC completely. conversion. Subsequent conversion results can be cor-
rected by software. Do not issue a NO-OP command
Once the ADC is calibrated to the selected channel, set directly following the gain calibration, as the cali-
CAL = 0 and NUL = 0 and leave CHS unchanged in the bration data will be lost.
next control word to perform a signal conversion on the
selected analog input channel. Programming Conversion Time
Calibrate the ADC after the following operations: The MAX110/MAX111 are specified for 12 bits of accu-
racy and up to ±14 bits of resolution. The ADC’s resolu-
— when power is first applied tion depends on the number of clock cycles allowed
— if the reference common-mode voltage changes during each conversion. Control-register bits 9–12
— if the common-mode voltage of the selected input (CONV1–CONV4) determine the conversion time by
channel varies significantly. The CMRR of the analog controlling the nominal number of oversampling clock
inputs is 0.25LSB/V. cycles required for each conversion (OSCC/CONV).
Table 4 lists the available conversion times and result-
— after changing channels (if the common-mode volt- ing resolutions.
ages of the two channels are different)
To program a new conversion time, perform a 3-step
— after changing conversion speed/resolution. calibration with the appropriate CONV1–CONV4 data
— after significant changes in temperature. The offset used in Table 3. The ADC is now calibrated at the new
drift with temperature is typically 0.003µV/°C. conversion speed/resolution.

Table 4. Available Conversion Times

CLOCK CYCLES NOMINAL CONVERSION TIME CONVERSION

CONV4 CONV3 CONV2 CONV1 PER RCSEL = GND, DV2 = DV4 = 0, XCLK = 500kHz RESOLUTION
CONVERSION (ms) (Bits)

1 0 0 1 10,240 20.48 12 + POL

0 0 1 1 20,480 40.96 13 + POL
0 1 1 0 81,920 163.84 14 + POL
0 0 0 0 102,400* 204.80 14 + POL

* Gain-calibration mode is not available with 102,400 clock cycles/conversion selected.

Table 5. Clock Divider-Ratio Control

DV2 DV4 DESCRIPTION

0 0 XCLK or internal RC oscillator connects directly to the ADC; fOSC = fXCLK.

0 1 XCLK or internal RC oscillator is divided by 4 and connects to the ADC; fOSC = fXCLK ÷ 4.

1 0 XCLK or internal RC oscillator is divided by 2 and connects to the ADC; fOSC = fXCLK ÷ 2.

1 1 Not allowed

Clock duty cycles of 50% ±10% are recommended.

______________________________________________________________________________________ 17
 Low-Cost, 2-Channel, ±14-Bit Serial ADCs
MAX110/MAX111

-10

-20

GAIN (dB)
-30

-40

-50

-60
CONVERSION TIME 0.1 1 2 3 4 5 6 7 8 9 10
LINE CYCLE PERIOD

SIGNAL FREQUENCY IN Hz 1 10 20 30 40 50 60 70 80 90100

FOR 100ms CONVERSION
TIME (see Table 6)

Figure 9. MAX110/MAX111 Noise Rejection Follows SIN(X) / X Function

Selecting the Oversampling clock frequency can be used for best performance.
Clock Frequency Over the extended and military temperature ranges, the
ratio of 2 or 4 gives the best performance. See the
Choose the oversampling frequency, fOSC, carefully to
Typical Operating Characteristics to observe the effect
achieve the best relative-accuracy performance from the
of the clock divider on the converter’s linearity.
MAX110/MAX111 (see Typical Operating Characteristics).
Clock Divider-Ratio Control Bits 50Hz/60Hz Line Frequency Rejection
Bits 7 and 8 (DV2 and DV4) program the clock- High rejection of 50Hz or 60Hz is obtained by using an
frequency divider network. The divider network sets the oversampling clock frequency and a clock-cycles/con-
frequency ratio between f XCLK (the frequency of the version setting so the conversion time equals an inte-
external TTL/CMOS clock or internal RC oscillator) and gral number of line cycles, as in the following equation:
fOSC (the oversampling frequency used by the ADC). fOSC = fLINE x m / n
An oversampling clock frequency between 450kHz and where fOSC is the oversampling clock frequency, fLINE
700kHz is optimum for the converter. Best perfor- = 50Hz or 60Hz, m is the number of clock cycles per
mance over the extended temperature range is conversion (see Table 4), and n is the number of line
obtained by choosing 1MHz or 1.024MHz with the cycles averaged every conversion.
divide-by-2 option (DV2 = 1) (see the section Effect
of Dither on INL). To determine the converter’s accura- This noise rejection is inherent in integrating and
cy at other clock frequencies, see the Typical sigma-delta ADCs, and follows a SIN(X) / X function
Operating Characteristics and Table 5. (Figure 9). Notches in this function represent extremely
high rejection, and correspond to frequencies with an
Effect of Dither on Relative Accuracy integral number of cycles in the MAX110/MAX111’s
First-order sigma-delta converters require dither for selected conversion time.
randomizing any systematic tone being generated in The shortest conversion time resulting in maximum
the modulator. The frequency of the dither source plays simultaneous rejection of both 60Hz and 50Hz line fre-
an important role in linearizing the modulator. The ratio quencies is 100ms. When using the MAX111, use a
of the dither generator’s frequency to that of the modu- 200ms conversion time for maximum 60Hz and 50Hz
lator’s oversampling clock can be changed by setting rejection and optimum performance. For either device,
the DV2/DV4 bits. The XCLK clock is directly used by select the appropriate oversampling clock frequency
the dither generator while the DV2/DV4 bits reduce the and either an 81,240 or 102,400 clock cycles per con-
oversampling clock by a ratio of 2 or 4. Over the com- version (CCPC) ratio. Table 6 suggests the possible
mercial temperature range, any ratio (i.e., 1, 2, or 4) configurations.
between the dither frequency and the oversampling

18 ______________________________________________________________________________________
 Low-Cost, 2-Channel, ±14-Bit Serial ADCs

MAX110/MAX111
POWER POWER
SUPPLIES SUPPLIES

+5V -5V GND +5V GND

4.7µF 4.7µF *R = 10Ω 4.7µF

*R = 10Ω

0.1µF 0.1µF 0.1µF

VDD GND VSS +5V DGND VDD GND AGND +5V DGND

DIGITAL DIGITAL
MAX110 CIRCUITRY MAX111 CIRCUITRY

*OPTIONAL *OPTIONAL

Figure 10a. MAX110 Power-Supply Grounding Connections Figure 10b. MAX111 Power-Supply Grounding Connections

A 100ms conversion time cannot be achieved with either If you wish to use a configuration other than those sug-
10,240 CCPC or 20,480 CCPC modes because fOSC gested in Table 6, you can accomplish similar 50Hz
would be below the minimum 250kHz requirement. and 60Hz line-frequency rejection off-chip by averag-
When the gain calibration is performed, the conversion ing several conversions.
times change approximately 1% to compensate for the __________Applications Information
modulator’s gain error. This slightly degrades the line-
frequency rejection, because the corrected conversion Layout, Grounding, Bypassing
time is no longer an exact multiple of the line frequency. For minimal noise, bypass each supply to GND with a
Typically, the rejection of 50Hz/60Hz from the converter 0.1µF capacitor. A ground plane should also be placed
is 55dB; i.e., if there is 100mV injection at the reference under the analog circuitry. To minimize the coupling
or the analog input pin, it will cause an uncertainty of effects of stray capacitance, keep digital lines as far
±0.006%. If the system has large 50Hz/60Hz noise, the from analog components and lines as possible. Figure
use of internal auto gain calibration is not recommend- 10 shows the suggested power-supply and ground-
ed. Instead, gain calibration should be done off-chip, plane connections.
using numerical computation methods.

Table 6. Suggested XCLK Frequencies to Achieve Maximum Rejection of Both 50Hz/60Hz Line
Frequencies
MAX110 (tCONVERT = 100ms) MAX111 (tCONVERT = 200ms)

81,240 CCPC 102,400 CCPC 81,240 CCPC 102,400 CCPC

DIVIDER DIVIDER
RATIO RELATIVE RELATIVE RATIO RELATIVE RELATIVE
fXCLK fXCLK fXCLK fXCLK
ACCURACY ACCURACY ACCURACY ACCURACY
(MHz) (MHz) (MHz) (MHz)
(%) (%) (%) (%)
1:1 0.8124 0.025 1.024 0.065 1:1 0.4062 0.030 0.512 0.030
2:1 1.6248 0.018 2.048 0.045 2:1 0.8124 0.025 1.024 0.025
4:1 3.2496 0.016 4.096 0.030 4:1 1.6248 0.022 2.048 0.023
CCPC = Clock Cycles per Conversion

______________________________________________________________________________________ 19
 Low-Cost, 2-Channel, ±14-Bit Serial ADCs
MAX110/MAX111

+5V

0.1µF
+5V

VDD
22k

1/2 MAX492 REF+

30mV +5V
FULL-SCALE 10k
1k
MAX111
REF-
1µF
1k
+5V 121k
49.9k
IN1+ CS
2k
49.9k 1k IN1- DIN

1µF DOUT
121k +5V
SCLK
AGND GND

1/2 MAX492

Figure 11. Weigh Scale Application

Capacitive Loading Effects of XCLK in Weigh Scale Application

Internal RC-Oscillator Mode The fully differential analog signal and reference inputs
When using the internal RC oscillator, capacitive load- make the MAX111 easy to interface to transducers with
ing effects on the XCLK pin must be minimized. Stray differential outputs, such as the load cell in Figure 11.
capacitance causes the VDD power consumption to Because the ADC input is differential, the load cell only
increase by an amount p = 1⁄2CV2f, where C = stray requires differential gain, eliminating the need for the
capacitance, V is the supply voltage, and f is the fre- difference amplifier (differential to single-ended con-
quency of the internal RC oscillator. verter) of the standard three op-amp instrumentation-
amplifier realization.
External Reference
The reference inputs to the ADC are high impedance, The 30mV full-scale bridge output is amplified to 2V
allowing both an external voltage reference and ratio- full-scale and applied to the MAX111 channel-one
metric applications without loading effects. The fully dif- input. The reference voltage to the ADC is created by a
ferential analog signal and reference inputs are voltage divider connected to the +5V rail. The same 5V
advantageous for performing ratiometric conversions provides excitation for the bridge; therefore, as the
(Figures 11 and 12). For example, when measuring excitation voltage varies, the reference voltage to the
load cells, the bridge excitation and the ADC reference ADC also varies, providing an ADC output that does
input both share the same voltage source. As the exci- not depend on the supply voltage.
tation changes with temperature or voltage, the output The two 121kΩ resistors connected to the +5V supplies
of the load cell will change. But since the differential shift the common-mode voltage from 2.5V (5V/2) to
reference voltage also changes, the conversion results 1.5V to ensure linearity. Match these two resistors to
remain constant, all else remaining equal. avoid introducing differential offset, or trim the resistor
mismatch with a potentiometer. In practice, the scale is
“zeroed” or “tared” by storing the average of several
conversions in a memory location while the scale is

20 ______________________________________________________________________________________
 Low-Cost, 2-Channel, ±14-Bit Serial ADCs

MAX110/MAX111
+5V
1/4 MAX479
VDD
IN2+
IN2-
10k 10k

MAX110
1/4 MAX479
1k
+5V
1µF
VIN
243k
TEMP

IN1+ CS
K-TYPE MAX874
OUT 1k
IN1- DIN
243k
DOUT
10k REF+
1k SCLK
REF-
VSS
1µF
1/4 MAX479
-5V
1M

Figure 12. Thermocouple Circuit with Software Compensation

unloaded, and subtracting this value from actual weight where α is the Seebeck constant for the type of thermo-
measurements. The lowpass filtering action of the couple, T1 is the temperature being measured, and
MAX111’s sigma-delta converter helps minimize noise. TREF is the temperature of the junction block. Although
The resolution of the weigh scale can be further one method to obtain TREF is to force the junction block
increased by averaging several conversions. to a known temperature (0°C), a more popular
approach is to measure TREF directly using a thermistor
Thermocouple Circuit with Software or PN junction voltage.
Compensation
A thermocouple is created by the junction of dissimilar The circuit in Figure 12 shows a k-type thermocouple
metals, and generates a voltage proportional to temper- going through a 54dB gain stage to channel 1 of the
ature (Seebeck voltage), making it useful for tempera- MAX110. A MAX874 voltage reference provides both
ture-measurement instruments. When a thermocouple the 3V reference voltage and reference junction tem-
probe is connected to a measurement instrument, other perature information to the MAX110. Armed with the
thermoelectric potentials are created between the alloys temperature information provided by the MAX874, the
of the probe and the copper connectors of the instru- thermocouple voltage created at the junction block can
ment. These potentials introduce a temperature-depen- be subtracted out in software. The TEMP output of the
dent error that must be subtracted from the temperature MAX874 is nominally 690mV at room temperature, and
measurement to obtain an accurate result. According to increases with temperature at about 2.3mV/°C. Place
the law of intermediate metals, the junction of the ther- the MAX874 as close as possible to the terminal block,
mocouple-probe alloys with the copper of the instrument and ensure good thermal contact between them. This
junction block can be treated as another thermocouple circuit employs a common k-type thermocouple and,
of the same type. The voltage measured by the instru- with the component values shown, can indicate tem-
ment can be expressed as: peratures in the range of -150°C to +125°C.
V = α(T1 - TREF)

______________________________________________________________________________________ 21
 Low-Cost, 2-Channel, ±14-Bit Serial ADCs
MAX110/MAX111

_Ordering Information (continued) __________________Chip Topography

PART TEMP. RANGE PIN-PACKAGE INL(%) REF+ REF- IN1+ IN1- IN2+ IN2-
MAX110AEPE -40°C to +85°C 16 Plastic DIP ±0.03
MAX110BEPE -40°C to +85°C 16 Plastic DIP ±0.05
MAX110AEWE -40°C to +85°C 16 Wide SO ±0.03
MAX110BEWE -40°C to +85°C 16 Wide SO ±0.05
MAX110AEAP -40°C to +85°C 20 SSOP ±0.03
MAX110BEAP -40°C to +85°C 20 SSOP ±0.05
V SS
MAX110BMJE -55°C to +125°C 16 CERDIP** ±0.05 (AGND)
MAX111ACPE 0°C to +70°C 16 Plastic DIP ±0.03 V SS
(AGND)
MAX111BCPE 0°C to +70°C 16 Plastic DIP ±0.05 GND
MAX111ACWE 0°C to +70°C 16 Wide SO ±0.03 V DD
MAX111BCWE 0°C to +70°C 16 Wide SO ±0.05 V DD GND

MAX111ACAP 0°C to +70°C 20 SSOP ±0.03 RCSEL

MAX111BCAP 0°C to +70°C 20 SSOP ±0.05
0.168"
MAX111BC/D 0°C to +70°C Dice* ±0.05 (4.27mm)
MAX111AEPE -40°C to +85°C 16 Plastic DIP ±0.03
MAX111BEPE -40°C to +85°C 16 Plastic DIP ±0.05
MAX111AEWE -40°C to +85°C 16 Wide SO ±0.03
MAX111BEWE -40°C to +85°C 16 Wide SO ±0.05
MAX111AEAP -40°C to +85°C 20 SSOP ±0.03
MAX111BEAP -40°C to +85°C 20 SSOP ±0.05
MAX111BMJE -55°C to +125°C 16 CERDIP** ±0.05
XCLK SCLK BUSY CS DOUT DIN
* Contact factory for dice specifications.
** Contact factory for availability. 0.121"
(3.07mm)

____Pin Configurations (continued) ( ) ARE FOR MAX111

TRANSISTOR COUNT: 5849

TOP VIEW
SUBSTRATE CONNECTED TO VDD

IN1+ 1 20 IN1-

REF- 2 19 IN2+

REF+ 3 MAX110 18 IN2-

MAX111
N.C. 4 17 VSS (AGND)

N.C. 5 16 GND

VDD 6 15 N.C.

RCSEL 7 14 N.C.

XCLK 8 13 DIN

SCLK 9 12 DOUT

BUSY 10 11 CS

SSOP
( ) ARE FOR MAX111

22 ______________________________________________________________________________________
 Low-Cost, 2-Channel, ±14-Bit Serial ADCs

MAX110/MAX111
_______________________________________________________Package Information

PDIPN.EPS
SOICW.EPS

______________________________________________________________________________________ 23
 Low-Cost, 2-Channel, ±14-Bit Serial ADCs
MAX110/MAX111

___________________________________________Package Information (continued)

SSOP.EPS
CDIPS.EPS

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.