Digitally Adjustable LCD Bias Supply: Evaluation Kit Manual Follows Data Sheet
Digitally Adjustable LCD Bias Supply: Evaluation Kit Manual Follows Data Sheet
Digitally Adjustable LCD Bias Supply: Evaluation Kit Manual Follows Data Sheet
NUAL
KIT MA
ATION HEET
EVALU A T A S
WS D
FOLLO
MAX749
The MAX749 generates negative LCD-bias contrast ♦ +2.0V to +6.0V Input Voltage Range
voltages from 2V to 6V inputs. Full-scale output voltage
can be scaled to -100V or greater, and is digitally ♦ Flexible Control of Output Voltage:
adjustable in 64 equal steps by an internal digital-to- Digital Control
analog converter (DAC). Only seven small surface- Potentiometer Adjustment
mount components are required to build a complete PWM Control
supply. The output voltage can also be adjusted using
♦ Output Voltage Range Set by One Resistor
a PWM signal or a potentiometer.
A unique current-limited control scheme reduces supply ♦ Low, 60µA Max Quiescent Current
current and maximizes efficiency, while a high switching ♦ 15µA Max Shutdown Mode
frequency (up to 500kHz) minimizes the size of external
components. Quiescent current is only 60µA max and is ♦ Small Size – 8-Pin SO and Plastic DIP Packages
reduced to under 15µA in shutdown mode. While shut
down, the MAX749 retains the voltage set point, simpli-
fying software control. The MAX749 drives either an
external P-channel MOSFET or a PNP transistor.
RSENSE
0.1µF 1 8
V+ CS
V+ 1 8 CS
2 ADJ 7
DIGITAL MAX749 DHI 2 7
ADJUST ADJ DHI
3 6 -VOUT MAX749
ON/OFF CTRL DLOW CTRL 3 6 DLOW
4 5
FB GND FB 4 5 GND
RFB DIP/SO
CCOMP
TIMING CHARACTERISTICS
TA = +25°C TA = TMIN to TMAX
PARAMETER SYMBOL CONDITIONS UNITS
MIN TYP MAX MIN MAX
V+ = 2V 125 300 400
Minimum Reset Pulse Width tR ns
V+ = 5V 25 85 100
Minimum Reset Setup tRS Not tested 0 0 ns
Minimum Reset Hold tRH Not tested 0 0 ns
V+ = 2V 15 85 100
Minimum ADJ High Pulse Width tSH ns
V+ = 5V 10 85 100
V+ = 2V 170 400 500
Minimum ADJ Low Pulse Width tSL ns
V+ = 5V 60 150 200
V+ = 2V 70 200 250
Minimum ADJ Low to CTRL Low tSD ns
V+ = 5V 20 85 100
2 ______________________________________________________________________________________
Digitally Adjustable LCD Bias Supply
__________________________________________Typical Operating Characteristics
MAX749
(TA = +25°C, L = 47µH, unless otherwise noted.)
MAX749TOC2-B
MAX749TOC2-C
-24V
78
-12V -12V
80 -12V 76 80
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
-24V -5V
74 -5V
-5V
-24V
75 72 75
V+ = 5V
V+ = 3V 70 V+ = 3V RSENSE = 0.25Ω
RBASE = 470Ω RBASE = 160Ω TRANSISTOR: SMD10P05L
70 RSENSE = 0.25Ω 68 RSENSE = 0.25Ω 70
TRANSISTOR: ZTX750 TRANSISTOR = ZTX750
66
65 64 65
0 10 20 30 40 50 60 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 35 40 45 50
OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) OUTPUT CURRENT (mA)
MAX749-TOC1-B
MAX749-TOC1-A
-20mA
-5mA
-20mA
80 80
-40mA
EFFICIENCY (%)
EFFICIENCY (%)
-40mA
-5mA
75 75
V+ = 3V V+ = 5V
70 RBASE = 470Ω 70
RSENSE = 0.25Ω
RSENSE = 0.25Ω
TRANSISTOR : SMD10P05L
TRANSISTOR : ZTX750
65 65
-24 -22 -20 -18 -16 -14 -12 -10 -8 -6 -4 -24 -22 -20 -18 -16 -14 -12 -10 -8 -6 -4
OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V)
LOAD CURRENT vs. INPUT VOLTAGE LOAD CURRENT vs. INPUT VOLTAGE
400 500
MAX749-TOC3-B
MAX749-TOC3-A
350 450
RBASE = 470Ω -5V RBASE = 160Ω
400
300 RSENSE = 0.25Ω RSENSE = 0.25Ω -5V
LOAD CURRENT (mA)
LOAD CURRENT (mA)
0 0
2 3 4 5 6 2 3 4 5 6
INPUT VOLTAGE (V) INPUT VOLTAGE (V)
_______________________________________________________________________________________ 3
Digitally Adjustable LCD Bias Supply
____________________________Typical Operating Characteristics (continued)
MAX749
OUTPUT 100mVAC/div
OUTPUT 100mVAC/div
VOLTAGE
VOLTAGE
1 V/div
LOAD INPUT
CURRENT 10mA/div VOLTAGE
0mA
VOUT = -15V
TRANSISTOR = ZTX750
0V
50µs/div 50ms/div
VOUT = -15V VOUT = -15V
TRANSISTOR = ZTX750 ILOAD = 5mA
TRANSISTOR = ZTX750
______________________________________________________________Pin Description
PIN NAME FUNCTION
+2V to +6V Input Voltage to power the MAX749 and external circuitry. When using an external
1 V+
P-channel MOSFET, V+ must exceed the MOSFET’s gate threshold voltage.
Logic Input. When CTRL is high, a rising edge on ADJ increments an internal counter. When CTRL is
2 ADJ low, the counter is reset to mid-scale when ADJ is high. When ADJ is low, the counter does not
change (regardless of activity on CTRL) as long as V+ is applied.
Logic Input. When CTRL and ADJ are low, the MAX749 is shut down, but the counter is not reset.
3 CTRL When CTRL is low, the counter is reset to mid-scale when ADJ is high. The device is always on when
CTRL is high.
Feedback Input for output full-scale voltage selection. -VOUT(MAX) = (RFB) x (20µA) where RFB is
4 FB
connected from FB to -VOUT. The device is in regulation when VFB = 0V.
5 GND Ground
Output Driver Low. Connect to DHI when using an external P-channel MOSFET. When using an
6 DLOW external PNP transistor, connect a resistor RBASE from DLOW to the base of the PNP to set the maxi-
mum base-drive current.
Output Driver High. Connect to the gate of the external P-channel transistor, or to the base of the
7 DHI
external PNP transistor.
Current-Sense Input. The external transistor is turned off when current through the sense resistor,
8 CS
RSENSE, brings CS below V+ by 140mV (typ).
4 ______________________________________________________________________________________
Digitally Adjustable LCD Bias Supply
MAX749
+2V TO +6V
0.1µF 22µF
INPUT
6.2V
V+
RESET 6-BIT 6.66µA TO 20µA RSENSE
POWER-ON 6-BIT
RESET COUNTER CURRENT-OUTPUT
DAC
CTRL REF
RFB VOUT
FB (NEGATIVE)
MAX749 GND
22µF
30V
CCOMP
_______________Detailed Description turns off, current flows from the output through the diode
and the coil, driving the output negative. Feedback con-
The MAX749 is a negative-output inverting power con-
trol adjusts the external transistor’s timing to provide a
troller that can drive an external PNP transistor or P-
regulated negative output voltage.
channel MOSFET. An external resistor and an internal
DAC control the output voltage (Figure 1). The MAX749’s unique control scheme combines the
ultra-low supply current of pulse-skipping, pulse-fre-
The MAX749 is designed to operate from 2V to 6V inputs,
quency modulation (PFM) converters with the high full-
ideal for operation from low-voltage batteries. In systems
load efficiency characteristic of pulse-width modulation
with higher-voltage batteries, such as notebook comput-
(PWM) converters. This control scheme allows the
ers, the MAX749 may also be operated from the regulat-
device to achieve high efficiency over a wide range of
ed +5V supply. A high-efficiency +5V regulator, such as
loads. The current-sense function and high operating
the MAX782, is an ideal source for the MAX749. In this
frequency allow the use of tiny external components.
example, the MAX749 efficiency (80%) is compounded
with the MAX782 efficiency (95%): 80% x 95% = 76%, Switching control is accomplished through the combi-
which is still high. nation of a current limit in the switch plus on- and off-
time limits (Figure 2).
Operating Principle Once turned on, the transistor stays on until either:
The MAX749 and the external components shown in the
Typical Operating Circuit form a flyback converter. - the maximum on-time one-shot turns it off
When the external transistor is on, current flows through (8µs later), or
the current-sense resistor, the transistor, and the coil. - the switch current reaches its limit (as determined
Energy is stored in the core of the coil during this phase, by the current-sense resistor and the current
and the diode does not conduct. When the transistor comparator).
_______________________________________________________________________________________ 5
Digitally Adjustable LCD Bias Supply
MAX749
+2V TO +6V
INPUT
0.1µF
22µF
V+
140mV
RSENSE
Q TRIG CURRENT
COMPARATOR
MINIMUM
OFF-TIME
ONE-SHOT
FLIP-FLOP
DHI Q1
S Q
ZTX750
R
DLOW
MAXIMUM RBASE
ON-TIME D1
470Ω L1 1N5819
ONE-SHOT
VOLTAGE 47µH
TRIG COMPARATOR
Q
RFB VOUT
FB (NEGATIVE)
6-BIT
REF CURRENT-OUTPUT 22µF
MAX749 DAC 30V
GND CCOMP
Once turned off, a one-shot holds the switch off for a ments the DAC output. When incremented beyond full
minimum of 1µs, and the switch either stays off (if the scale, the counter rolls over and sets the DAC to the
output is in regulation), or turns on again (if the output minimum value. In this way, a single pulse applied to
is out of regulation). ADJ increases the DAC set point by one step, and 63
With light loads, the transistor switches for one or more pulses decrease the set point by one step.
cycles and then turns off, much like a traditional PFM Table 1 is the logic table for the CTRL and ADJ inputs,
converter. With heavy loads, the transistor stays on until which control the internal DAC and counter. Figures 3-7
the switch current reaches the current limit; it then show various timing specifications and different ways of
shuts off for 1µs, and immediately turns on again until incrementing and resetting the DAC, and of placing it in
the next time the switch current reaches its limit. This the low-power standby mode. As long as the timing
cycle repeats until the output is in regulation. specifications for ADJ and CTRL are observed, any
sequence of operations can be implemented.
Output Voltage Control
The output voltage is set using a single external resistor Table 1. Input Truth Table
and the internal current-output DAC (Figure 1). The full-
scale output voltage is set by selecting the feedback ADJ CTRL RESULT
resistor, RFB. The output voltage is controlled from 33% Low Low Shut down
to 100% of the full-scale output by an internal 64-step Reset counter to mid-range. The
DAC/counter. High Low
device is not shut down.
On power-up or after a reset, the counter sets the DAC X High On
output to mid-range. Each rising edge of ADJ incre-
High Increment the counter
6 ______________________________________________________________________________________
Digitally Adjustable LCD Bias Supply
In Figure 3, the MAX749 is reset when it is taken out of
MAX749
shutdown, which sets the output at mid-scale. Figure 4
ADJ
shows how to increment the counter. Figure 5 illustrates
CTRL a reset without shutting the device down.
Figure 7 provides an example of a sequence of opera-
tR tSD tions: Starting from shutdown, the device is turned on,
incremented, reset to mid-scale without being shut
ON down, incremented again, and finally shut down.
SHUTDOWN RESET SHUTDOWN
Shutdown Mode
Figure 3. Shutdown-Reset-On-Shutdown Sequence of Operation. When CTRL and ADJ are both low, the MAX749 is shut
The device is not shut down during reset. down (Table 1): The internal reference and biasing cir-
cuitry turn off, the output voltage drops to zero, and the
supply current drops to 15µA. The MAX749 retains its
DAC setting, simplifying software control.
CTRL
CTRL
tRH
tR
SHUTDOWN RESET ON SHUTDOWN ON SHUTDOWN
Figure 6. Reset Sequence with Shutdown Figure 7. Control Sequence Example (see Output Voltage
Control section)
_______________________________________________________________________________________ 7
Digitally Adjustable LCD Bias Supply
Current-Sense Resistor
MAX749
+4.5V to +6V The current-sense resistor limits the peak switch cur-
INPUT 0.1µF 22µF rent to 140mV/RSENSE, where RSENSE is the value of the
RSENSE
current-sense resistor, and 140mV is the typical cur-
V+
rent-sense comparator threshold (see V+ to CS Voltage
CS in the Electrical Characteristics).
MAX749 DHI Q1
To maximize efficiency and reduce the size and cost of
SMD10P05L the external components, minimize the peak current.
However, since the output current is a function of the peak
CTRL DLOW current (Figures 9a-9e), the limit should not be set too low.
L1
No calculations are required to choose the proper cur-
D1 rent-sense resistor; simply follow this two-step procedure:
47µH
ADJ 1N5819
1. Determine:
VOUT - the minimum input voltage, VIN(MIN),
R1 R2 (NEGATIVE)
- the maximum output voltage, VOUT(MAX), and
GND - the maximum output current, IOUT(MAX).
22µF For example, assume that the output voltage must be
30V adjustable to -24V (VOUT(MAX) = -24V) at up to 30mA
CCOMP
VOUT(MIN) = -R1(13.33µA) (IOUT(MAX) = 30mA). The supply voltage ranges from
VOUT(MAX) = -(R1+R2)(13.33µA) 4.75V to 6V (VIN(MIN) = 4.75V).
2. In Figures 9a-9e, locate the graph drawn for the
Figure 8. Using a Potentiometer to Adjust the Output Voltage
appropriate output voltage (which is either the
desired output voltage or, if that is not shown, the
graph for the nearest voltage more negative than the
counter rolls over and sets the DAC to -V OUT(MIN) , desired output). On this graph find the curve for the
where -VOUT(MIN) = RFB x 6.66µA. In other words, a sin- highest RSENSE (the lowest current limit) with an out-
gle rising edge of ADJ increments the DAC output by put current that is adequate at the lowest input
one, and 63 rising edges of ADJ decrement the DAC voltage.
output by one.
In this example, select the -24V output graph, Figure 9d.
Potentiometer Adjustment We then want a curve where IOUT is ≥30mA with a 4.75V
It is also possible to adjust the output voltage using a input. The 0.3Ω RSENSE graph shows 25mA of output cur-
potentiometer instead of the internal DAC (Figure 8). On rent with a 4.75V input, so we look next at the 0.25Ω
power-up (V+ applied), the internal current source is set RSENSE graph. It shows IOUT = 30mA for VIN = 4.75V and
to mid-scale, or 13.33µA. Choose R1 and R2 with the fol- VOUT = -24V. Therefore select RSENSE = 0.25Ω. This pro-
lowing equations: vides a current limit in the range 440mA to 720mA.
R1 = -VOUT(MIN)/13.33µA Alternatively, a 0.2Ω sense resistor can be used. This
gives a current limit in the range 550mA to 900mA, but
R2 = -VOUT(MAX)/13.33µA - R1. enables over 40mA to be generated at -24V with input
Where the potentiometer can be varied from 0 (producing voltages down to 4.5V. A 0.2Ω resistor may be easier to
VOUT(MIN)) to R2Ω (producing VOUT(MAX)). Notice that ADJ obtain than an 0.25Ω resistor.
is connected to ground, allowing the device to be shut The theoretical design curves shown in Figures 9a-9e
down. assume the minimum (worst-case) value for the current-
PWM Adjustment limit comparator threshold. Having selected the cur-
A positive pulse-width modulated (PWM) logic signal rent-sense resistor, the maximum current limit is given
(e.g., from a microcontroller) can control the MAX749’s by 180mV/RSENSE. Use the maximum current-limit fig-
output voltage. Use the PWM signal to pull up the FB ure when choosing the transistor, coil, and diode.
pin through a suitable resistor. An RC network on the IRC (see Table 2) makes surface-mount resistors with pre-
PWM output would also be required. In this configura- ferred values including: 0.1Ω, 0.2Ω, 0.3Ω, 0.5Ω, and 1.0Ω.
tion, the longer the PWM signal remains high, the more
negative the MAX749’s output will be driven.
8 ______________________________________________________________________________________
Digitally Adjustable LCD Bias Supply
Choosing an Inductor
MAX749
Practical inductor values range from 22µH to 100µH, 0.2
100
and 47µH is normally a good choice. Inductors with a
MAX749-Fig 11
ferrite core or equivalent are recommended. The induc- L = 47µH
tor’s saturation current rating – the current at which the 80
0.25
core begins to saturate and the inductance falls to 80%
RSENSE (Ω)
or 90% of its nominal value – should ideally equal the 60
0.3
current limit (see Current-Sense Resistor section).
However, because the current is limited by the 40
MAX749, the inductor can safely be driven into satura- 0.5
tion with only a slight impact on efficiency. 20
For highest efficiency, use a coil with low resistance, 1.0
preferably under 300mΩ. To minimize radiated noise, 0
use a toroid, pot-core, or shielded inductor. 2 3 4 5 6
INPUT VOLTAGE (V)
Figure 9c. Maximum Output Current vs. Input Voltage,
VOUT = -15V
250 0.2 60
MAX749-Fig 9
0.2
MAXIMUM OUTPUT CURRENT (mA)
MAX749-Fig 12
200 L = 47µH 0.25 L = 47µH
0.3 40 0.25
RSENSE (Ω)
RSENSE (Ω)
150
30 0.3
100
0.5
20
0.5
50
1.0 10
1.0
0 0
2 3 4 5 6 2 3 4 5 6
INPUT VOLTAGE (V) INPUT VOLTAGE (V)
Figure 9a. Maximum Output Current vs. Input Voltage, Figure 9d. Maximum Output Current vs. Input Voltage,
VOUT = -5V VOUT = -24V
140 25 0.2
MAX749-Fig 13
0.2
MAXIMUM OUTPUT CURRENT (mA)
VOUT = -12V
MAX-749-Fig10
15
RSENSE (Ω)
80 0.3
60
10
0.5
40
0.5
5
20 1.0 1.0
0 0
2 3 4 5 6 2 3 4 5 6
INPUT VOLTAGE (V) INPUT VOLTAGE (V)
Figure 9b. Maximum Output Current vs. Input Voltage, Figure 9e. Maximum Output Current vs. Input Voltage,
VOUT = -12V VOUT = -48V
_______________________________________________________________________________________ 9
Digitally Adjustable LCD Bias Supply
The Sumida CD54-470N (47µH, 720mA, 370mΩ) is suit- Table 2. Component Suppliers
MAX749
10 _____________________________________________________________________________________
Digitally Adjustable LCD Bias Supply
Capacitors Compensation Capacitor
MAX749
Output Filter Capacitor The high value of the feedback resistor makes the feed-
A 22µF, 30V surface-mount (SMT) tantalum output filter back loop susceptible to phase lag if parasitic capaci-
capacitor typically maintains 100mVp-p output ripple tance is present at the FB pin. To compensate for this, it
when generating -24V at 40mA from a 5V input. Smaller may be necessary to connect a capacitor, CCOMP, in
capacitors, down to 10µF, may be used for light loads parallel with R FB . Although C COMP is normally not
in applications that can tolerate higher output ripple. required, the value of CCOMP depends upon the value
Surface-mount capacitors are generally preferred of RFB and on the individual circuit layout—typical val-
because they lack the inductance and resistance of the ues range from 0pF to 220pF.
leads of their through-hole equivalents. PC Layout and Grounding
Input Bypass Capacitor Due to high current levels and fast switching wave-
A 22µF tantalum capacitor in parallel with a 0.1µF forms, proper PC board layout is essential. In particular,
ceramic normally provides sufficient bypassing. Mount keep all leads short, especially the lead connected to
the 0.1µF capacitor very close to the IC. Larger the FB pin and those connecting Q1, L1, and D1
capacitors may be needed if the incoming supply has together. Mount the RFB resistor very close to the IC.
high impedance. Less bypass capacitance is accept- Use a star ground configuration: Connect the ground
able if the circuit is run off a low-impedance supply. lead of the input bypass capacitor, the output capaci-
Begin prototyping with a large bypass capacitor; when tor, and the inductor at a common point next to the
the circuit is working, reduce the bypass to the smallest GND pin of the MAX749. Additionally, connect the posi-
value that gives good results. Although bench power tive lead of the input bypass capacitor as close as pos-
supplies have low impedance at DC, they often have sible to the V+ pin of the IC.
high impedance at the frequencies used by switching
DC-DC converters.
The effective series resistance (ESR) of both the
bypass and filter capacitors affects efficiency. Best per-
formance is obtained by doubling up on the filter
capacitors or using low-ESR types. ___________________Chip Topography
The smallest low-ESR SMT capacitors currently avail-
able are Sprague 595D series, which are about half the 0.070"
size of competing products. Sanyo OS-CON organic (0.1178mm)
semiconductor through-hole capacitors also exhibit low V+ V+ CS
ESR, and are especially useful when operation below
0°C is required. Table 2 lists the phone numbers of
these and other manufacturers.
ADJ
CTRL
DHI 0.808"
(0.2032mm)
DLOW
FB GND
______________________________________________________________________________________ 11
Digitally Adjustable LCD Bias Supply
_______________________________________________________Package Information
MAX749
INCHES MILLIMETERS
E DIM
MIN MAX MIN MAX
E1 A – 0.200 – 5.08
D
A1 0.015 – 0.38 –
A3 A2 0.125 0.175 3.18 4.45
A3 0.055 0.080 1.40 2.03
A A2
B 0.016 0.022 0.41 0.56
B1 0.045 0.065 1.14 1.65
C 0.008 0.012 0.20 0.30
L A1 D1 0.005 0.080 0.13 2.03
0° - 15°
E 0.300 0.325 7.62 8.26
C E1 0.240 0.310 6.10 7.87
e e 0.100 – 2.54 –
B1 eA
B eA 0.300 – 7.62 –
eB eB – 0.400 – 10.16
L 0.115 0.150 2.92 3.81
D1
INCHES MILLIMETERS
Plastic DIP PKG. DIM PINS
MIN MAX MIN MAX
PLASTIC P D 8 0.348 0.390 8.84 9.91
P D 14 0.735 0.765 18.67 19.43
DUAL-IN-LINE
P D 16 0.745 0.765 18.92 19.43
PACKAGE P D 18 0.885 0.915 22.48 23.24
(0.300 in.) P D 20 1.015 1.045 25.78 26.54
N D 24 1.14 1.265 28.96 32.13
21-0043A
INCHES MILLIMETERS
DIM
MIN MAX MIN MAX
A 0.053 0.069 1.35 1.75
D A1 0.004 0.010 0.10 0.25
B 0.014 0.019 0.35 0.49
0°-8° C 0.007 0.010 0.19 0.25
A
E 0.150 0.157 3.80 4.00
0.101mm
0.004in.
e 0.050 1.27
e H 0.228 0.244 5.80 6.20
B A1 C L L 0.016 0.050 0.40 1.27
INCHES MILLIMETERS
Narrow SO DIM PINS
MIN MAX MIN MAX
E H
SMALL-OUTLINE D 8 0.189 0.197 4.80 5.00
D 14 0.337 0.344 8.55 8.75
PACKAGE
D 16 0.386 0.394 9.80 10.00
(0.150 in.) 21-0041A
12 ______________________________________________________________________________________