CSO Lecture Notes Unit-1

Shri Vaishnav Vidyapeeth Vishwavidyalaya, Indore (MP)
Think Excellence. Live Excellence.
Shri Vaishnav Institute of Information Technology

Department of Information Technology
Lecture Notes
COMPUTER SYSTEM ORGANIZATION

(BTIT205)
Subject Teacher
Er. Gaurav Shrivastava

B.E. (CSE), M.E. (IT)
Asst. Professor (IT Department)
IT- First Year Coordinator
SVITT-SVVV, Indore
Syllabus
Unit-I: Computer Basics and CPU : Von Newman model, various subsystems, CPU, Memory, I/O,
System Bus, CPU and Memory registers, Program Counter, Accumulator, Instruction register, Micro
operations, Register Transfer Language, Instruction Fetch, decode and execution, data movement and
manipulation, Instruction formats and addressing modes of basic computer. 8085 microprocessor
organization
Unit-II Control Unit Organization: Hardwired control unit, Micro and nano programmed control unit,
Control Memory, Address Sequencing, Micro Instruction formats, Micro program sequencer,
Microprogramming, Arithmetic and Logic Unit: Arithmetic Processor, Addition, subtraction,
multiplication and division, Floating point and decimal arithmetic and arithmetic units, design of
arithmetic unit.
Unit-III Input Output Organization: Modes of data transfer – program controlled, interrupt driven and
direct memory access, Interrupt structures, I/O Interface, Asynchronous Data Transfer, I/O processor,
8085 I/O structure, 8085 instruction set and basic programming. Data Transfer – Serial / parallel,
synchronous/asynchronous, simplex,/half duplex and full duplex.
Unit-IV Memory organization: Memory Maps, Memory Hierarchy, Cache Memory - Organization and
mappings. Associative Memory, Virtual Memory, Memory Management Hardware.
Unit-V Multiprocessors: Pipeline and Vector processing, Instruction and arithmetic pipelines, Vector
and array processors, Interconnection structure and inter-processor communication.
References:
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Prepared by: - Er. Gaurav Shrivastava, Asst. Professor (I.T. Dept.) SVIIT-SVVV, Indore
Unit-I:
Computer Basics and CPU
1. Computer Types
A computer can be defined as a fast electronic calculating machine that accepts the (data)
digitized input information process it as per the list of internally stored instructions and
produces the resulting information.
List of instructions are called programs & internal storage is called computer memory.
The different types of computers are

1. Personal computers: - This is the most common type found in homes, schools,
Business offices etc., It is the most common type of desk top computers with processing
and storage units along with various input and output devices.
2. Note book computers: - These are compact and portable versions of PC
3. Work stations: - These have high resolution input/output (I/O) graphics capability,
but with same dimensions as that of desktop computer. These are used in engineering
applications of interactive design work.
4. Enterprise / Mainframe systems: - These are used for business data processing in
medium to large corporations that require much more computing power and storage
capacity than work stations. Internet associated with servers has become a dominant
worldwide source of all types of information.
5. Super computers: - These are used for large scale numerical calculations required in
the applications like weather forecasting etc.
2. Functional unit of Computers

A computer consists of five functionally independent main parts input, memory,
arithmetic logic unit (ALU), and output and control unit.
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Fig : Functional units of computer

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Input device accepts the coded information as source program i.e. high level language.
This is either stored in the memory or immediately used by the processor to
perform the desired operations. The program stored in the memory determines the
processing steps. Basically the computer converts one source program to an object
program. I.e. into machine language
Finally the results are sent to the outside world through output device. All of these
actions are coordinated by the control unit.
2.1 Input unit: -

The source program/high level languages program/coded information/simply data is fed
to a computer through input devices keyboard is a most common type. Whenever a key is
pressed, one corresponding word or number is translated into its equivalent binary code
over a cable & fed either to memory or processor.
Joysticks, trackballs, mouse, scanners etc. are other input devices.
2.2 Memory unit: -

Its function into store programs and data. It is basically to two types
I. Primary memory
II. Secondary memory
I. Primary memory: - Is the one exclusively associated with the processor and operates
at the electronics speeds programs must be stored in this memory while they are being
executed. The memory contains a large number of semiconductors storage cells. Each
capable of storing one bit of information. These are processed in a group of fixed site
called word.
To provide easy access to a word in memory, a distinct address is associated with each
word location. Addresses are numbers that identify memory location.
Number of bits in each word is called word length of the computer. Programs must reside
in the memory during execution. Instructions and data can be written into the memory or
read out under the control of processor.
Memory in which any location can be reached in a short and fixed amount of time after
specifying its address is called random-access memory (RAM).
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The time required to access one word in called memory access time. Memory which is
only readable by the user and contents of which can‟t be altered is called read only
memory (ROM) it contains operating system.
Caches are the small fast RAM units, which are coupled with the processor and are aften
contained on the same IC chip to achieve high performance. Although primary storage is
essential it tends to be expensive.
II. Secondary memory: - Is used where large amounts of data & programs have to be
stored, particularly information that is accessed infrequently.
Examples: - Magnetic disks & tapes, optical disks (ie CD-ROM‟s), floppies etc.,
2.3 Arithmetic logic unit (ALU):-

Most of the computer operators are executed in ALU of the processor like addition,
subtraction, division, multiplication, etc. the operands are brought into the ALU from
memory and stored in high speed storage elements called register. Then according to the
instructions the operation is performed in the required sequence.
The control and the ALU are many times faster than other devices connected to a
computer system. This enables a single processor to control a number of external devices
such as key boards, displays, magnetic and optical disks, sensors and other mechanical
controllers.
2.4 Output unit:-

These actually are the counterparts of input unit. Its basic function is to send the
processed results to the outside world.
Examples: - Printer, speakers, monitor etc.
2.5 Control unit:-

It effectively is the nerve centre that sends signals to other units and senses their states.
The actual timing signals that govern the transfer of data between input unit, processor,
memory and output unit are generated by the control unit.
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3. The von Neumann Computer Model
 Von Neumann computer systems contain three main building blocks:
o the central processing unit (CPU),
o memory,
o Input/output devices (I/O).
 These three components are connected together using the system bus.
 The most prominent items within the CPU are the registers: they can be
manipulated directly by a computer program.
Components of the Von Neumann Model
1. Memory: Storage of information (data/program)

2. Processing Unit: Computation/Processing of Information
3. Input: Means of getting information into the computer. e.g. keyboard, mouse
4. Output: Means of getting information out of the computer. e.g. printer, monitor
5. Control Unit: Makes sure that all the other parts perform their tasks correctly and
at the correct time.
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4. System Bus
The system bus connects the CPU with the main memory and, in some systems, with the
level 2 (L2) cache. Other buses, such as the IO buses, branch off from the system bus to
provide a communication channel between the CPU and the other peripherals.
The system bus combines the functions of the three main buses, which are as follows:
 The control bus carries the control, timing and coordination signals to manage the
various functions across the system.
 The address bus is used to specify memory locations for the data being transferred.
 The data bus, which is a bidirectional path, carries the actual data between the
processor, the memory and the peripherals.
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5. CPU and Memory Registers,
CPU Register:
A processor register (CPU register) is one of a small set of data holding places that are
part of the computer processor.
A register may hold an instruction, a storage address, or any kind of data (such as a bit
sequence or individual characters). Some instructions specify registers as part of the
instruction. For example, an instruction may specify that the contents of two defined
registers be added together and then placed in a specified register. A register must be
large enough to hold an instruction - for example, in a 64-bit computer; a register must be
64 bits in length. In some computer designs, there are smaller registers - for example,
half-registers - for shorter instructions. Depending on the processor design and language
rules, registers may be numbered or have arbitrary names.
Memory Registers:
Register are used to quickly accept, store, and transfer data and instructions that are being
used immediately by the CPU, there are various types of Registers those are used for
various purpose. Among of the some Mostly used Registers named as AC
or Accumulator, Data Register or DR, the AR or Address Register, program
counter (PC), Memory Data Register (MDR) ,Index register, Memory Buffer Register.
These Registers are used for performing the various Operations. While we are working
on the System then these Registers are used by the CPU for Performing the Operations.
When We Gives Some Input to the System then the Input will be Stored into the
Registers and When the System will gives us the Results after Processing then the Result
will also be from the Registers.
So that they are used by the CPU for Processing the Data which is given by the User.
Registers Perform:-
1) Fetch: The Fetch Operation is used for taking the instructions those are given by the
user and the Instructions those are stored into the Main Memory will be fetch by using
Registers.
2) Decode: The Decode Operation is used for interpreting the Instructions means the
Instructions are decoded means the CPU will find out which Operation is to be
performed on the Instructions.
3) Execute: The Execute Operation is performed by the CPU. And Results those are
produced by the CPU are then Stored into the Memory and after that they are displayed
on the user Screen.
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Types of Registers are as Followings
 Memory Address Register (MAR)
This register holds the memory addresses of data and instructions. This register is used to
access data and instructions from memory during the execution phase of an
instruction. Suppose CPU wants to store some data in the memory or to read the data
from the memory. It places the address of the-required memory location in the MAR.
 Program Counter
The program counter (PC), commonly called the instruction pointer (IP) in Intel x86
microprocessors, and sometimes called the instruction address register, or just part of the
instruction sequencer in some computers, is a processor register
It is a 16 bit special function register in the 8085 microprocessor. It keeps track of
the next memory address of the instruction that is to be executed once the execution of
the current instruction is completed. In other words, it holds the address of the memory
location of the next instruction when the current instruction is executed by the
microprocessor.
 Accumulator Register
This Register is used for storing the Results those are produced by the System. When the
CPU will generate Some Results after the Processing then all the Results will be Stored
into the AC Register.
 Memory Data Register (MDR)
MDR is the register of a computer's control unit that contains the data to be stored in the
computer storage (e.g. RAM), or the data after a fetch from the computer storage. It
acts like a buffer and holds anything that is copied from the memory ready for the
processor to use it. MDR hold the information before it goes to the decoder.
MDR which contains the data to be written into or readout of the addressed location. For
example, to retrieve the contents of cell 123, we would load the value 123 (in binary, of
course) into the MAR and perform a fetch operation. When the operation is done, a copy
of the contents of cell 123 would be in the MDR. To store the value 98 into cell 4, we
load a 4 into the MAR and a 98 into the MDR and perform a store. When the operation is
completed the contents of cell 4 will have been set to 98, by discarding whatever was
there previously.
The MDR is a two-way register. When data is fetched from memory and placed into the
MDR, it is written to in one direction. When there is a write instruction, the data to be
written is placed into the MDR from another CPU register, which then puts the data into
memory.
The Memory Data Register is half of a minimal interface between a micro program and
computer storage, the other half is a memory address register.
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 Index Register
A hardware element which holds a number that can be added to (or, in some cases,
subtracted from) the address portion of a computer instruction to form an effective
address. Also known as base register. An index register in a computer's CPU is a
processor register used for modifying operand addresses during the run of a program.
 Memory Buffer Register
MBR stand for Memory Buffer Register. This register holds the contents of data or
instruction read from, or written in memory. It means that this register is used to store
data/instruction coming from the memory or going to the memory.
 Data Register
A register used in microcomputers to temporarily store data being transmitted to or from
a peripheral device.
6. Micro-operations
In computer central processing units, micro-operations (also known as a micro-ops) are
detailed low-level instructions used in some designs to implement complex machine
instructions (sometimes termed macro-instructions in this context).
Usually, micro-operations perform basic operations on data stored in one or more

registers, including transferring data between registers or between registers and external
buses of the central processing unit (CPU), and performing arithmetic or logical
operations on registers. In a typical fetch-decode-execute cycle, each step of a macro-
instruction is decomposed during its execution so the CPU determines and steps through
a series of micro-operations. The execution of micro-operations is performed under
control of the CPU's control unit, which decides on their execution while performing
various optimizations such as reordering, fusion and caching.
7. Register Transfer Language

• A register transfer language is a notation used to describe the microoperation transfers
between registers.
• It is a system for expressing in symbolic form the microoperation sequences among
register that are used to implement machine-language instructions.
Registers are denoted by capital letters and are sometimes followed by numerals, e.g.,
– MAR – Memory Address Register (holds addresses for the memory unit)
– PC – Program Counter (holds the next instruction‟s address)
– IR – Instruction Register (holds the instruction being executed)
– R1 – Register 1 (a CPU register)
• We can indicate individual bits by placing them in parentheses, e.g., PC (8-15), R2 (5),
10
etc.
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Block Diagrams of Registers
Register Transfer Language Instructions
Basic Symbols for Register Transfer
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8. Instruction cycle:
An instruction cycle (sometimes called a fetch–decode–execute cycle) is the basic
operational process of a computer. It is the process by which a computer retrieves a
program instruction from its memory, determines what actions the instruction dictates,
and carries out those actions. This cycle is repeated continuously by a computer's central
processing unit (CPU), from boot-up to when the computer is shut down.
In simpler CPUs the instruction cycle is executed sequentially, each instruction being
processed before the next one is started. In most modern CPUs the instruction cycles are
instead executed concurrently, and often in parallel, through an instruction pipeline: the
next instruction starts being processed before the previous instruction has finished, which
is possible because the cycle is broken up into separate steps.
Steps:-
Each computer's CPU can have different cycles based on different instruction sets, but
will be similar to the following cycle:
1. Fetch the instruction: The next instruction is fetched from the memory address
that is currently stored in the program counter (PC), and stored in the instruction
register (IR). At the end of the fetch operation, the PC points to the next
instruction that will be read at the next cycle.
2. Decode the instruction: During this cycle the encoded instruction present in the
IR (instruction register) is interpreted by the decoder.
3. Read the effective address: In case of a memory instruction (direct or indirect)
the execution phase will be in the next clock pulse. If the instruction has
an indirect address, the effective address is read from main memory, and any
required data is fetched from main memory to be processed and then placed into
data registers (Clock Pulse: T3). If the instruction is direct, nothing is done at this
clock pulse. If this is an I/O instruction or a Register instruction, the operation is
performed (executed) at clock Pulse.
4. Execute the instruction: The control unit of the CPU passes the decoded
information as a sequence of control signals to the relevant function units of the
CPU to perform the actions required by the instruction such as reading values
from registers, passing them to the ALU to perform mathematical or logic
functions on them, and writing the result back to a register. If the ALU is
involved, it sends a condition signal back to the CU. The result generated by the
operation is stored in the main memory, or sent to an output device. Based on the
condition of any feedback from the ALU, Program Counter may be updated to a
different address from which the next instruction will be fetched.
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The cycle is then repeated.
Fig: CPU Cycle

9. Internal Communication:-
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Memory Read Operation :-
Memory Write Operation:-

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10. Instruction Set:-
The instruction set, also called instruction set architecture (ISA), an instruction set is a
group of commands for a CPU in machine language. The term can refer to all possible
instructions for a CPU or a subset of instructions to enhance its performance in certain
situations.
All CPUs have instruction sets that enable commands to the processor directing the CPU
to switch the relevant transistors. Some instructions are simple read, write and move
commands that direct data to different hardware.
The two major instruction sets architectures are

1) CISC (Complex Instruction Set Computing)
2) RISC (Reduced Instruction Set Computing)
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10.1 CISC Architecture
In the early days machines were programmed in assembly language and the memory
access is also slow. To calculate complex arithmetic operations, compilers have to create
long sequence of machine code.
This made the designers to build an architecture , which access memory less frequently
and reduce burden to compiler. Thus this lead to very power full but complex instruction
set.
CISC architectures directly use the memory, instead of a register file. The above figure
shows the architecture of CISC with micro programmed control and cache memory.
This architecture uses cache memory for holding both data and instructions. Thus, they
share the same path for both instructions and data.
CISC has instructions with variable length format. Thus, the number of clock cycles
required to execute the instructions may be varied.
Instructions in CISC are executed by micro program which has sequence of
microinstructions.
Advantages of CISC Architecture
 Microprogramming is easy to implement and much less expensive than hard

wiring a control unit.
 It is easy to add new commands into the chip without changing the structure of the
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instruction set as the architecture uses general-purpose hardware to carry out

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commands.
 This architecture makes the efficient use of main memory since the complexity (or
more capability) of instruction allows to use less number of instructions to achieve a
given task.
 The compiler need not be very complicated, as the micro program instruction sets
can be written to match the constructs of high level languages.
Disadvantages of CISC Architecture
 A new or succeeding versions of CISC processors consists early generation

processors in their subsets (succeeding version). Therefore, chip hardware and
instruction set became complex with each generation of the processor.
 The overall performance of the machine is reduced because of slower clock speed.
 The complexity of hardware and on-chip software included in CISC design to
perform many functions.
Examples of CISC processor
1. IBM 370/168
2. Intel 80486
3. VAX 11/780
10.2 RISC (Reduced Instruction Set Computer) Architecture

Although CISC reduces usage of memory and compiler, it requires more complex
hardware to implement the complex instructions.
In RISC architecture, the instruction set of processor is simplified to reduce the execution
time. It uses small and highly optimized set of instructions which are generally register to
register operations.
The speed of the execution is increased by using smaller number of instructions .This
uses pipeline technique for execution of any instruction.
The figure shown below is the architecture of RISC processor, which uses separate
instruction and data caches and their access paths also different. There is one instruction
per machine cycle in RISC processor.
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The pipelining technique allows the processor to work on different steps of instruction
like fetch, decode and execute instructions at the same time. Below is image showing
execution of instructions in pipelining technique.
Generally, execution of second instruction is started, only after the completion of the first
instruction. But in pipeline technique, each instruction is executed in number of stages
simultaneously.
When the first stage of first instruction is completed, next instruction is enters into the
fist stage. This process continuous until all the instructions are executed.
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Advantages of RISC Architecture
 The performance of RISC processors is often two to four times than that of CISC
processors because of simplified instruction set.
 This architecture uses less chip space due to reduced instruction set. This makes to
place extra functions like floating point arithmetic units or memory management units
on the same chip.
 The per-chip cost is reduced by this architecture that uses smaller chips consisting of
more components on a single silicon wafer.
 RISC processors can be designed more quickly than CISC processors due to its
simple architecture.
 The execution of instructions in RISC processors is high due to the use of many
registers for holding and passing the instructions as compared to CISC processors.
Disadvantages of RISC Architecture
 The performance of a RISC processor depends on the code that is being executed. The
processor spends much time waiting for first instruction result before it proceeds with
next subsequent instruction, when a compiler makes a poor job of scheduling
instruction execution.
 RISC processors require very fast memory systems to feed various instructions.
Typically, a large memory cache is provided on the chip in most RISC based systems.
10.3 Examples of RISC processors

This architecture includes alpha, AVR, ARM, PIC, PA-RISC, and power architecture.
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Understand RISC & CISC architecture with example

Let we take an example of multiplying two numbers
A = A * B; <<<======this is C statement
The CISC Approach: - The primary goal of CISC architecture is to complete a task in
as few lines of assembly as possible. This is achieved by building processor hardware
that is capable of understanding & executing a series of operations, this is where our
CISC architecture introduced.
For this particular task, a CISC processor would come prepared with a
specific instruction (we‟ll call it “MULT”). When executed, this instruction
1. Loads the two values into separate registers
2. Multiplies the operands in the execution unit
3. And finally third, stores the product in the appropriate register.
Thus, the entire task of multiplying two numbers can be completed with one instruction:
MULT A, B <<<======this is assembly statement
MULT is what is known as a “complex instruction.” It operates directly
on the computer‟s memory banks and does not require the programmer to explicitly call
any loading or storing functions.
The RISC Approach: - RISC processors only use simple instructions that can be
executed within one clock cycle. Thus, the “MULT” command described above could be
divided into three separate commands:
1. “LOAD” which moves data from the memory bank to a register
2. “PROD” which finds the product of two operands located within the registers
3. “STORE” which moves data from a register to the memory banks.
In order to perform the exact series of steps described in the CISC
approach, a programmer would need to code four lines of assembly:
LOAD R1, A <<<======this is assembly statement
LOAD R2,B <<<======this is assembly statement
PROD A, B <<<======this is assembly statement
STORE R3, A <<<======this is assembly statement
At first, this may seem like a much less efficient way of completing the
operation. Because there are more lines of code, more RAM is needed to store the
assembly level instructions. The compiler must also perform more work to convert a
high-level language statement into code of this form.
Which one is better?

We cannot differentiate RISC and CISC technology because both are suitable at its
specific application. What counts are how fast a chip can execute the instructions it is
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given and how well it runs existing software. Today, both RISC and CISC manufacturers
are doing everything to get an edge on the competition.
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10.4 Comparison between RISC and CISC:
RISC CISC
Acronym It stands for „Reduced Instruction Set It stands for „Complex Instruction Set
Computer‟. Computer‟.
Definition The RISC processors have a smaller set The CISC processors have a larger set of
of instructions with few addressing instructions with many addressing nodes.
nodes.
Memory unit It has no memory unit and uses a It has a memory unit to implement complex
separate hardware to implement instructions.
instructions.
Program It has a hard-wired unit of programming. It has a micro-programming unit.
Design It is a complex complier design. It is an easy complier design.

Calculations The calculations are faster and precise. The calculations are slow and precise.
Decoding Decoding of instructions is simple. Decoding of instructions is complex.

Time Execution time is very less. Execution time is very high.
External memory It does not require external memory for It requires external memory for calculations.
calculations.
Pipelining Pipelining does function correctly. Pipelining does not function correctly.
Stalling Stalling is mostly reduced in processors. The processors often stall.
Code expansion Code expansion can be a problem. Code expansion is not a problem.
Disc space The space is saved. The space is wasted.
Applications Used in high end applications such as Used in low end applications such as
video processing, telecommunications security systems, home automations, etc.
and image processing.
11. Data-transfer instructions

Following is the table showing the list of Data-transfer instructions with their meanings.
Opcode Operand Meaning Explanation

MOV Rd, Sc Copy from the source This instruction copies the contents of the source
M, Sc (Sc) to the register into the destination register without any
Dt, M destination(Dt) alteration.
Example − MOV K, L
MVI Rd, data Move immediate 8-bit The 8-bit data is stored in the destination register
M, data or memory.
Example − MVI K, 55L
LDA 16-bit address Load the accumulator The contents of a memory location, specified by a
16-bit address in the operand, are copied to the
accumulator.
Example − LDA 2034K
LDAX B/D Reg. pair Load the accumulator The contents of the designated register pair point
indirect to a memory location. This instruction copies the
contents of that memory location into the
accumulator.
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Example − LDAX K
LXI Reg. pair, 16- Load the register pair The instruction loads 16-bit data in the register
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bit data immediate pair designated in the register or the memory.

Example − LXI K, 3225L
LHLD 16-bit address Load H and L registers The instruction copies the contents of the memory
direct location pointed out by the address into register L
and copies the contents of the next memory
location into register H.
Example − LHLD 3225K
STA 16-bit address 16-bit address The contents of the accumulator are copied into
the memory location specified by the operand.
This is a 3-byte instruction, the second byte
specifies the low-order address and the third byte
specifies the high-order address.
Example − STA 325K
STAX 16-bit address Store the accumulator The contents of the accumulator are copied into
indirect the memory location specified by the contents of
the operand.
Example − STAX K
SHLD 16-bit address Store H and L registers The contents of register L are stored in the
direct memory location specified by the 16-bit address
in the operand and the contents of H register are
stored into the next memory location by
incrementing the operand.
This is a 3-byte instruction, the second byte
specifies the low-order address and the third byte
specifies the high-order address.
Example − SHLD 3225K
XCHG None Exchange H and L with The contents of register H are exchanged with the
D and E contents of register D, and the contents of register
L are exchanged with the contents of register E.
Example − XCHG
SPHL None Copy H and L registers The instruction loads the contents of the H and L
to the stack pointer registers into the stack pointer register. The
contents of the H register provide the high-order
address and the contents of the L register provide
the low-order address.
Example − SPHL
XTHL None Exchange H and L with The contents of the L register are exchanged with
top of stack the stack location pointed out by the contents of
the stack pointer register.
The contents of the H register are exchanged with
the next stack location (SP+1).
Example − XTHL
PUSH Reg. pair Push the register pair The contents of the register pair designated in the
onto the stack operand are copied onto the stack in the following
sequence.
The stack pointer register is decremented and the
contents of the high order register (B, D, H, A)
are copied into that location.
The stack pointer register is decremented again
and the contents of the low-order register (C, E,
L, flags) are copied to that location.
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Example − PUSH K
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POP Reg. pair Pop off stack to the The contents of the memory location pointed out
register pair by the stack pointer register are copied to the low-
order register (C, E, L, status flags) of the
operand.
The stack pointer is incremented by 1 and the
contents of that memory location are copied to the
high-order register (B, D, H, A) of the operand.
The stack pointer register is again incremented by
1.
Example − POPK
OUT 8-bit port Output the data from the The contents of the accumulator are copied into
address accumulator to a port the I/O port specified by the operand.
with 8bit address Example − OUT K9L
IN 8-bit port Input data to The contents of the input port designated in the
address accumulator from a port operand are read and loaded into the accumulator.
with 8-bit address Example − IN5KL
12. Instruction Format:-
The most common fields found in instruction format are:-

(1) An operation code field that specified the operation to be performed
(2) An address field that designates a memory address or a processor registers.
(3) A mode field that specifies the way the operand or the effective address is
determined.
Computers may have instructions of several different lengths containing varying number
of addresses. The number of address field in the instruction format of a computer
depends on the internal organization of its registers. Most computers fall into one of three
types of CPU organization.
(1) Single Accumulator organization ADD X AC ® AC + M [×]

(2) General Register Organization ADD R1, R2, R3 R ® R2 + R3
(3) Stack Organization PUSH X
12. 1 Three address Instruction

Computer with three addresses instruction format can use each address field to specify
either processor register are memory operand.
X = (A + B) x (C + D)
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ADD R1, A, B A1 ® M [A] + M [B]
ADD R2, C, D R2 ® M [C] + M [B]
MUL X, R1, R2 M [X] R1 * R2
The advantage of the three address formats is that it results in short program when
evaluating arithmetic expression. The disadvantage is that the binary-coded instructions
require too many bits to specify three addresses.
12.2 Two Address Instructions

Most common in commercial computers. Each address field can specify either a
processes register on a memory word.
X = (A + B) x ( C + D)
MOV R1, A R1 ® M [A]

ADD R1, B R1 ® R1 + M [B]
MOV R2, C R2 ® M [C]
ADD R2, D R2 ® R2 + M [D]
MUL R1, R2 R1 ® R1 * R2
MOV X1 R1 M [X] ® R1
12.3 One Address instruction

It used an implied accumulator (AC) register for all data manipulation. For
multiplication/division, there is a need for a second register.
X = (A +B) x (C + D)
LOAD A AC ® M [A]
ADD B AC ® AC + M [B]
STORE T M [T] ® AC
All operations are done between the AC register and a memory operand. It‟s the address
of a temporary memory location required for storing the intermediate result.
LOAD C AC ® M (C)
ADD D AC ® AC + M (D)
ML T AC ® AC + M (T)
STORE X M [×]® AC
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12.4 Zero – Address Instruction
A stack organized computer does not use an address field for the instruction ADD and
MUL. The PUSH & POP instruction, however, need an address field to specify the
operand that communicates with the stack (TOS ® top of the stack)
X = (A +B) x (C + D)
PUSH A TOS ® A
PUSH B TOS ® B
ADD TOS ® (A + B)
PUSH C TOS ® C
PUSH D TOS ® D
ADD TOS ® (C + D)
MUL TOS ® (C + D) * (A + B)
POP X M [X] TOS
13. Addressing Modes
The operation field of an instruction specifies the operation to be performed. This operation will be
executed on some data which is stored in computer registers or the main memory. The way any operand
is selected during the program execution is dependent on the addressing mode of the instruction. The
purpose of using addressing modes is as follows:
1. To give the programming versatility to the user.

2. To reduce the number of bits in addressing field of instruction.
13.1 Types of Addressing Modes:

1. Immediate Mode
In this mode, the operand is specified in the instruction itself. An immediate mode instruction has an
operand field rather than the address field.
For example: ADD 7, which says Add 7 to contents of accumulator. 7 is the operand here.
2. Direct Addressing Mode

In this mode, effective address of operand is present in instruction itself.
 Single memory reference to access data.

 No additional calculations to find the effective address of the operand.
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For Example: ADD R1, 4000 - In this the 4000 is effective address of operand.
NOTE: Effective Address is the location where operand is present.
3. Indirect Addressing Mode

In this, the address field of instruction gives the address where the effective address is stored in
memory. This slows down the execution, as this includes multiple memory lookups to find the operand.
1.1.1.1 4. Register Mode

In this mode the operand is stored in the register and this register is present in CPU. The instruction has
the address of the Register where the operand is stored.
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5. Register Indirect Mode
In this mode, the instruction specifies the register whose contents give us the address of operand which
is in memory. Thus, the register contains the address of operand rather than the operand itself.
======================
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14. 8085 Microprocessor Organization:
8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit microprocessor
designed by Intel in 1977 using NMOS technology.
It has the following configuration −
 8-bit data bus

 16-bit address bus, which can address upto 64KB
 A 16-bit program counter
 A 16-bit stack pointer
 Six 8-bit registers arranged in pairs: BC, DE, HL
 Requires +5V supply to operate at 3.2 MHZ single phase clock
It is used in washing machines, microwave ovens, mobile phones, etc.
14.1 Functional Units

8085 consists of the following functional units −
 Accumulator
It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE
operations. It is connected to internal data bus & ALU.
 Arithmetic and logic unit
As the name suggests, it performs arithmetic and logical operations like Addition,
Subtraction, AND, OR, etc. on 8-bit data.
 General purpose register
There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each
register can hold 8-bit data.
These registers can work in pair to hold 16-bit data and their pairing combination is like
B-C, D-E & H-L.
 Program counter
It is a 16-bit register used to store the memory address location of the next instruction to
be executed. Microprocessor increments the program whenever an instruction is being
executed, so that the program counter points to the memory address of the next
instruction that is going to be executed.
 Stack pointer
It is also a 16-bit register works like stack, which is always incremented/decremented by
2 during push & pop operations.
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 Temporary register
It is an 8-bit register, which holds the temporary data of arithmetic and logical
operations.
 Flag register
It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending
upon the result stored in the accumulator.
These are the set of 5 flip-flops −
 Sign (S)
 Zero (Z)
 Auxiliary Carry (AC)
 Parity (P)
 Carry (C)
Its bit position is shown in the following table −
D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY
 Instruction register and decoder

It is an 8-bit register. When an instruction is fetched from memory then it is stored in the
Instruction register. Instruction decoder decodes the information present in the
Instruction register.
 Timing and control unit
It provides timing and control signal to the microprocessor to perform operations.
Following are the timing and control signals, which control external and internal circuits
−
 Control Signals: READY, RD‟, WR‟, ALE

 Status Signals: S0, S1, IO/M‟
 DMA Signals: HOLD, HLDA
 RESET Signals: RESET IN, RESET OUT
 Interrupt control
As the name suggests it controls the interrupts during a process. When a microprocessor
is executing a main program and whenever an interrupt occurs, the microprocessor shifts
the control from the main program to process the incoming request. After the request is
32
completed, the control goes back to the main program.

Page
There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST
5.5, TRAP.
 Serial Input/output control
It controls the serial data communication by using these two instructions: SID (Serial
input data) and SOD (Serial output data).
 Address buffer and address-data buffer
The content stored in the stack pointer and program counter is loaded into the address
buffer and address-data buffer to communicate with the CPU. The memory and I/O
chips are connected to these buses; the CPU can exchange the desired data with the
memory and I/O chips.
 Address bus and data bus
Data bus carries the data to be stored. It is bidirectional, whereas address bus carries the
location to where it should be stored and it is unidirectional. It is used to transfer the
data & Address I/O devices.
8085 Architecture
We have tried to depict the architecture of 8085 with this following image −
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Shri Vaishnav Vidyapeeth Vishwavidyalaya, Indore (MP)

Think Excellence. Live Excellence.

Shri Vaishnav Institute of Information Technology

COMPUTER SYSTEM ORGANIZATION

Er. Gaurav Shrivastava

The different types of computers are

2. Functional unit of Computers

Fig : Functional units of computer

2.1 Input unit: -

Joysticks, trackballs, mouse, scanners etc. are other input devices.

2.2 Memory unit: -

2.3 Arithmetic logic unit (ALU):-

2.4 Output unit:-

Examples: - Printer, speakers, monitor etc.

2.5 Control unit:-

Components of the Von Neumann Model

1. Memory: Storage of information (data/program)

Usually, micro-operations perform basic operations on data stored in one or more

7. Register Transfer Language

Block Diagrams of Registers

Basic Symbols for Register Transfer

Fig: CPU Cycle

Memory Write Operation:-

The two major instruction sets architectures are

Advantages of CISC Architecture

 Microprogramming is easy to implement and much less expensive than hard

instruction set as the architecture uses general-purpose hardware to carry out

Disadvantages of CISC Architecture

 A new or succeeding versions of CISC processors consists early generation

Examples of CISC processor

10.2 RISC (Reduced Instruction Set Computer) Architecture

Disadvantages of RISC Architecture

10.3 Examples of RISC processors

Understand RISC & CISC architecture with example

Which one is better?

Design It is a complex complier design. It is an easy complier design.

Decoding Decoding of instructions is simple. Decoding of instructions is complex.

11. Data-transfer instructions

Opcode Operand Meaning Explanation

bit data immediate pair designated in the register or the memory.

12. Instruction Format:-

The most common fields found in instruction format are:-

(1) Single Accumulator organization ADD X AC ® AC + M [×]

12. 1 Three address Instruction

12.2 Two Address Instructions

MOV R1, A R1 ® M [A]

12.3 One Address instruction

13. Addressing Modes

1. To give the programming versatility to the user.

13.1 Types of Addressing Modes:

2. Direct Addressing Mode

 Single memory reference to access data.

3. Indirect Addressing Mode

1.1.1.1 4. Register Mode

It has the following configuration −

 8-bit data bus

14.1 Functional Units

 Instruction register and decoder

 Control Signals: READY, RD‟, WR‟, ALE

completed, the control goes back to the main program.