MOSFET DC Circuits Analysis

1. Assume an operation region (usually the saturation region)

2. Apply KVL at the gate source loop to find VGS
3. Use VGS from step 2 to calculate ID
4. Apply KVL at the drain source loop and use ID from step 3 to find VDS
5. Check the validity of operation region assumptions by comparing VDS to VDSat
6. Change assumptions and analyze again if required.

NOTES :
„ An enhancement-mode device with VDS = VGS is always in saturation
„ If we have a source resistance, we need to solve the equations in steps 2
and 3 together to find ID and VGS.
„ If we include channel length modulation or we are in the triode region, we
will solve the equations in steps 3 and 4 together
„ If we include channel length modulation or we are in the triode region and
we have a source resistance, we will solve the equations in steps 2, 3, and 4
together
 Bias Analysis: Example 1
Assumption: Transistor is
saturated, IG=IB=0
Analysis: First, simplify circuit,
split VDD into two equal-valued
sources and apply Thevenin
transformation to find VEQ and REQ
for gate-bias voltage
Problem: Find the Q-pt (ID, VDS)
Given: VTN=1V, Kn=25μA/V2
Approach: Assume operation
region, find Q-point, check to see
if result is consistent with
operation region
 Bias Analysis: Example 1 (contd.)
V 2 + 0.05V − 7.21 = 0
GS GS
∴V = −2.71V,+2.66V
GS
Since VGS<VTN for VGS= -2.71 V
and MOSFET will be cut-off,
we ignore it
V = +2.66V and ID= 34.4 μA
GS
KVL at G-S loop, =V + I R
V KVL at D-S loop,
EQ GS D S
K ⎞2
V = I ( R + R ) +V
I = n ⎛⎜V −V ⎟
DD D D S DS
D 2 ⎝ GS TN ⎠ ∴V = 6.08V
DS
⎞2
K R ⎛
∴V =V + n S ⎜V −V ⎟ VDS>VGS-VTN. Hence saturation
EQ GS 2 ⎝ GS TN ⎠
region assumption is correct.
⎛
⎜ 25×10
−6 ⎞⎛ 3⎞
⎟⎜ 39×10 ⎟
4 =V +
⎜
⎝
⎟⎜
⎠⎝
⎟
⎠ ⎛V −1⎞⎟
2 Q-pt: (34.4 μA, 6.08 V)
⎜
GS 2 ⎝ GS ⎠ with VGS= 2.66 V
 Bias Analysis: Example 2
V = I R = 22,000 I
Find the Q-point for the shown SB D S D
circuit with body effect using V = V + γ ( V + 2φ − 2φ )
TN TO SB F F
2φF=0.6 V, VTO=1V, and γ=0.5V1/2:
∴V = 1 + 0.5( V + 0.6 − 0.6 )
TN SB
⎜ 25 ×10 − 6 ⎟
⎛ ⎞
⎜ ⎟⎛ ⎞
2
I '= ⎝ ⎠ ⎜V
⎜ − V ⎟
D 2 ⎝ GS TN ⎟⎠
Iterative solution can be found
by following steps:
„ Estimate value of ID and use
it to find VGS and VSB
„ Use VSB to calculate VTN
„ Find ID’ using above 2 steps
KVL at G-S loop, „ If ID’ is not same as original
V =V − I R = 6− 22,000 I
GS EQ D S D ID estimate, start again.
 Bias Analysis: Example 2 (contd.)
The iteration sequence leads to ID= 88.0 μA
V =V − I ( R + R ) = 10 − 40,000 I = 6.48V
DS DD D D S D

VDS>VGS-VTN. Hence saturation region assumption is correct.

Q-pt: (88.0 μA, 6.48 V)
 Bias Analysis: Example 3
Find the Q-point for the shown circuit? Kn R ⎛ ⎞
2
V =V − D ⎜⎜V −V ⎟⎟
GS DD 2 ⎝ GS TN ⎠
⎜ 2.6 ×10 − 4 ⎟⎜104 ⎟
⎛ ⎞⎛ ⎞
⎜ ⎟⎜ ⎟⎛ ⎞
2
∴V = 3.3 − ⎝ ⎠ ⎝ ⎠ ⎜⎜V −1⎟⎟
GS 2 ⎝ GS ⎠

∴V = −0.769V,+2.00V
GS
Since VGS<VTN for VGS= -0.769
V and MOSFET will be cut-off,
it will be ignored.
V = +2.00V and ID= 130 μA
GS
Assumption: IG=IB=0, transistor
VDS>VGS-VTN. Hence saturation
is saturated (since VDS = VGS)
region assumption is correct.
Analysis:
Q-pt: (130 μA, 2.00 V)
V =V =V −I R
DS GS DD D D
 Bias Analysis: Example 4
( Biasing in Triode Region)
Find the Q-point for the shown circuit?
KVL at D-S loop,
V = I R +V
DD D D DS
∴4 = 1600 I +V
D DS
∴V = 2.19V
DS
But VDS<VGS-VTN. Hence, saturation
region assumption is incorrect Using
triode region equation,
μA V
4 −V = 1600* 250 (4 −1− DS )V
Assumption: IG=IB=0, DS V2 2 DS
transistor is saturated ∴V = 2.3V and ID=1.06 mA
DS
Analysis: VGS=VDD=4 V VDS<VGS-VTN, transistor is in triode region
I = 250 μA (4 −1)2 = 1.13mA Q-pt:(1.06 mA, 2.3 V)
D 2 V2
 Bias Analysis: Example 5
15V − (220kΩ)I −V =0
Find the Q-point for the shown circuit? D SG
2
∴15V − (220kΩ) 50 μA ⎛⎜V − 2 ⎞⎟ −V =0
2 V2 ⎝ SG ⎠ SG

∴V = 0.369V,3.45V
SG

Since VSG= 0.369 V is less than

|VTP|= 2 V, ∴VSG = 3.45 V
ID = 52.5 μA and VSG = 3.45 V
V >V −V
Assumption: IG=IB=0, transistor SD SG TP
is saturated (since VDS= VGS)
Hence saturation assumption is correct.
Analysis:
Q-pt: (52.5 μA, 3.45 V)
KVL at G-S loop,
 MOSFET Circuits At DC

Fig. Ex6
Fig. Ex7 Fig. Ex8

„ Example 6: Design the circuit of Fig. Ex6 so that the transistor operates at
ID=0.3 mA and VD=+1V. The NMOS transistor has Vt = 1V, μnCox=20 μA/V2,
L=1 μm, and W=30μm.

„ Example 7: Design the circuit in Fig. Ex7 to obtain a current ID of 0.4 mA. Find
the value required for R and find the DC voltage VD. The NMOS transistor has Vt
= 0.5V, μnCox=20 μA/V2, L=1 μm, and W=40μm.

„ Example 8: Design the circuit in Fig. Ex8 to establish a drain voltage of 0.1 V.
What is the effective resistance between drain and source at this operating
point? Let Vt = 1V and kn = 1 mA/V2
 MOSFET Circuits At DC (contd.)

Fig. Ex9 Fig. Ex10

„ Example 9: Analyze the circuit shown in Fig. Ex9 to determine

the voltages at all nodes and the currents through all branches.
Let Vt = 1V and kn’(W/L) = 1 mA/V2
„ Example 10: Design the circuit in Fig. Ex10 for the shown
currents and voltages (i.e find R, (W/L) for each transistor). Let
Vt=1 V, μnCox=20 μA/V2
MOSFET As A Current Source
„ Ideal current source
gives fixed output
current regardless of
the voltage across it.
„ MOSFET behaves as
as an ideal current
source if biased in
the pinch-off region
(output current
depends on terminal
voltage).
 NMOS Current Mirror
'
K ⎛W ⎞
⎞2 ⎛ ⎞
⎟ ⎜1+ λV
⎜ ⎟ ⎛
I = n
⎟ ⎝⎜V GS1 −V
REF ⎜ TN ⎠ ⎝ DS1 ⎟⎠
2 ⎜⎝ L ⎟
⎠M 1

'
K ⎛ ⎞
⎜W ⎞2 ⎛ ⎞
⎟ ⎜1+ λV
⎟ ⎛
I = n
⎟ ⎜⎝V GS2 −V
O ⎜ TN ⎠ ⎝ DS2 ⎟⎠
2 ⎜⎝ L ⎟
⎠M 2

But VGS2=VGS1
⎛W ⎞ ⎛ ⎞ ⎛
W ⎞
⎜ ⎟ ⎜1+ λV ⎟ ⎜ ⎟
∴I = I ⎝L ⎠M 2 ⎝ DS2 ⎠ ≅ ⎝ L ⎠M 2 I
O REF ⎛W ⎞ ⎛⎜1+ λV ⎞ ⎛W ⎞ REF
⎟
⎜ ⎟ ⎝ DS1 ⎠ ⎜⎝ L ⎟
Assumption: M1 and ⎝L ⎠M 1 ⎠M 1
M2 have identical VTN,
Thus, output current mirrors
Kn’, λ and W/L and are
reference current if VDS1=VDS2 or
in saturation.
λ= 0, and both transistors have
the same (W/L)
 NMOS Current Mirror: Example 11
Find the output current and the minimum output
voltage vo to maintain the given current mirror in
proper operation.
Given data: IREF= 50 μA, VO= 12 V, VTN= 1 V, Kn’= 75 μA/V2, λ= 0 V-1,
(W/L)M1 = 2, (W/L)M2=10
Analysis: ⎛W ⎞
⎜ ⎟
⎜ ⎟
⎝ L ⎠M 2
∴I = I = 250μA
O REF ⎛W ⎞
⎜ ⎟
⎜ ⎟
⎝ L ⎠M1

2I
V =V + REF = 1V + 2(50μA) = 1.82V
GS TN ⎛W ⎞ μA
K n ⎜⎜ ⎟⎟ (1+ λV
′ ) 2*75
⎜ L ⎟
⎝ ⎠
DS 1 V2

Hence, Vomin =VGS – VTN = 0.82 V.