Ad 9228

Quad, 12-Bit, 40 MSPS/65 MSPS
Serial LVDS 1.8 V A/D Converter

Data Sheet AD9228
FEATURES FUNCTIONAL BLOCK DIAGRAM
4 ADCs integrated into 1 package AVDD PDWN DRVDD DRGND
119 mW ADC power per channel at 65 MSPS AD9228

12
SNR = 70 dB (to Nyquist) VIN + A SERIAL D+A
PIPELINE
ENOB = 11.3 bits VIN – A ADC LVDS D–A
SFDR = 82 dBc (to Nyquist) 12

VIN + B PIPELINE SERIAL D+B
Excellent linearity VIN – B ADC LVDS D–B
DNL = ±0.3 LSB (typical) 12

VIN + C PIPELINE SERIAL D+C
INL = ±0.4 LSB (typical) VIN – C ADC LVDS D–C
Serial LVDS (ANSI-644, default) 12

VIN + D PIPELINE SERIAL D+D
Low power, reduced signal option (similar to IEEE 1596.3) VIN – D ADC LVDS D–D
Data and frame clock outputs VREF
315 MHz full power analog bandwidth SENSE FCO+
+
– 0.5V FCO–
2 V p-p input voltage range DATA RATE
REFT REF MULTIPLIER
1.8 V supply operation REFB SELECT SERIAL PORT DCO+
INTERFACE DCO–
Serial port control
Full chip and individual channel power-down modes RBIAS AGND CSB SDIO/ODM SCLK/DTP CLK+ CLK–
05727-001
Flexible bit orientation
Built in and custom digital test pattern generation Figure 1.
Programmable clock and data alignment
Programmable output resolution PRODUCT HIGHLIGHTS
Standby mode
1. Small Footprint. Four ADCs are contained in a small, space-
APPLICATIONS saving package.
2. Low power of 119 mW/channel at 65 MSPS.
Medical imaging and nondestructive ultrasound
3. Ease of Use. A data clock output (DCO) is provided that
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
operates at frequencies of up to 390 MHz and supports
Diversity radio receivers
double data rate (DDR) operation.
Tape drives 4. User Flexibility. The SPI control offers a wide range of flexible
Optical networking features to meet specific system requirements.
Test equipment 5. Pin-Compatible Family. This includes the AD9287 (8-bit),
AD9219 (10-bit), and AD9259 (14-bit).
GENERAL DESCRIPTION
The AD9228 is a quad, 12-bit, 40/65 MSPS analog-to-digital con- capturing data on the output and a frame clock output (FCO)
verter (ADC) with an on-chip sample-and-hold circuit designed for signaling a new output byte are provided. Individual
for low cost, low power, small size, and ease of use. The product channel power-down is supported and typically consumes
operates at a conversion rate of up to 65 MSPS and is optimized for <2 mW when all channels are disabled.
outstanding dynamic performance and low power in applications
where a small package size is critical. The ADC contains several features designed to maximize flexibility
and minimize system cost, such as programmable clock and data
The ADC requires a single 1.8 V power supply and LVPECL-/ alignment and programmable digital test pattern generation. The
CMOS-/LVDS-compatible sample rate clock for full performance available digital test patterns include built-in deterministic and
operation. No external reference or driver components are pseudorandom patterns, along with custom user-defined test
required for many applications. patterns entered via the serial port interface (SPI).
The ADC automatically multiplies the sample rate clock for the The AD9228 is available in an RoHS compliant, 48-lead LFCSP. It
appropriate LVDS serial data rate. A data clock output (DCO) for is specified over the industrial temperature range of −40°C to
+85°C.
Rev. G Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
No license is granted by implication or otherwise under any patent or patent rights of Analog Tel: 781.329.4700 ©2006–2020 Analog Devices, Inc. All rights reserved.
Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
AD9228 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Analog Input Considerations ................................................... 20
Applications ...................................................................................... 1 Clock Input Considerations ..................................................... 23
General Description ......................................................................... 1 Serial Port Interface (SPI) ............................................................. 31
Functional Block Diagram .............................................................. 1 Hardware Interface .................................................................... 31
Product Highlights ........................................................................... 1 Memory Map .................................................................................. 33
Revision History ............................................................................... 3 Reading the Memory Map Table ............................................. 33
Specifications .................................................................................... 4 Reserved Locations .................................................................... 33
AC Specifications ......................................................................... 5 Default Values ............................................................................ 33
Digital Specifications ................................................................... 6 Logic Levels ................................................................................. 33
Switching Specifications .............................................................. 7 Evaluation Board ............................................................................ 37
Timing Diagrams.............................................................................. 8 Power Supplies ........................................................................... 37
Absolute Maximum Ratings ......................................................... 10 Input Signals ............................................................................... 37
Thermal Impedance ................................................................... 10 Output Signals ............................................................................ 37
ESD Caution................................................................................ 10 Default Operation and Jumper Selection Settings ................ 38
Pin Configuration and Function Descriptions .......................... 11 Alternative Analog Input Drive Configuration ..................... 39
Equivalent Circuits ......................................................................... 13 Outline Dimensions ....................................................................... 53
Typical Performance Characteristics ........................................... 15 Ordering Guide .......................................................................... 53
Theory of Operation ...................................................................... 20
Rev. G | Page 2 of 53
Data Sheet AD9228
REVISION HISTORY
11/2020—Rev. F to Rev. G Changes to Pipeline Latency ........................................................... 6
Changed CP-48-8 to CP-48-9 ..................................... Throughout Added Endnote 2 to Table 4 ............................................................ 6
Changes to Figure 5 ........................................................................11 Changes to Figure 2 to Figure 4 ...................................................... 7
Updated Outline Dimensions .......................................................53 Changes to Figure 10 ...................................................................... 12
Changes to Ordering Guide...........................................................53 Changes to Figure 15, Figure 17 to Figure 19, Figure 37, and
Figure 39 ........................................................................................... 14
8/2018—Rev. E to Rev. F Changes to Figure 23 to Figure 26 Captions ............................... 15
Changes to Digital Outputs and Timing Section .......................28 Change to Figure 35 Caption ........................................................ 17
Added Figure 46 and Figure 47..................................................... 20
12/2011—Rev. D to Rev. E Changes to Figure 51 ...................................................................... 21
Changes to Output Signals Section and Figure 71 .....................37 Changes to Clock Duty Cycle Considerations Section .............. 22
Change to Default Operation and Jumper Selection Settings Changes to Power Dissipation and Power-Down Mode Section .. 23
Section...............................................................................................38 Changes to Figure 61 to Figure 63 Captions ............................... 25
Change to Figure 74 ........................................................................41 Changes to Table 9 Endnote.......................................................... 26
Added Endnote 3 in Ordering Guide ...........................................53 Changes to Digital Outputs and Timing Section ....................... 27
Added Table 10 ............................................................................... 27
4/2010—Rev. C to Rev. D Changes to RBIAS Pin Section...................................................... 28
Changes to Table 16 ........................................................................35 Deleted Figure 62 and Figure 63 ................................................... 27
Updated Outline Dimensions .......................................................53 Changes to Figure 67 ...................................................................... 29
Changes to Ordering Guide...........................................................53 Changes to Hardware Interface Section ...................................... 30
Added Figure 68 .............................................................................. 31
12/2009—Rev. B to Rev. C Changes to Table 15........................................................................ 31
Updated Outline Dimensions .......................................................53 Changes to Reading the Memory Map Table Section ............... 32
Changes to Ordering Guide...........................................................54 Change to Input Signals Section ................................................... 36
Changes to Output Signals Section .............................................. 36
7/2007—Rev. A to Rev. B Changes to Figure 71 ...................................................................... 36
Changes to Figure 3 .......................................................................... 7 Changes to Default Operation and Jumper Selection Settings
Change to Table 7 ...........................................................................10 Section .............................................................................................. 37
Changes to Alternative Analog Input Drive Configuration
5/2007—Rev. 0 to Rev. A Section .............................................................................................. 38
Changes to Features .......................................................................... 1 Changes to Figure 74 ...................................................................... 40
Change to Effective Number of Bits (ENOB) ............................... 4 Changes to Table 17........................................................................ 48
Changes to Logic Output (SDIO/ODM) Section ......................... 5 Changes to Ordering Guide .......................................................... 52
Added Endnote 3 to Table 3 ............................................................ 5
4/2006—Revision 0: Initial Version
AD9228 Data Sheet
SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 1.
AD9228-40 AD9228-65
Parameter1 Temperature Min Typ Max Min Typ Max Unit
RESOLUTION 12 12 Bits
ACCURACY
No Missing Codes Full Guaranteed Guaranteed
Offset Error Full ±1 ±8 ±1 ±8 mV
Offset Matching Full ±2 ±8 ±2 ±8 mV
Gain Error Full ±0.4 ±1.2 ±2 ±3.5 % FS
Gain Matching Full ±0.3 ±0.7 ±0.3 ±0.7 % FS
Differential Nonlinearity (DNL) Full ±0.25 ±0.5 ±0.3 ±0.65 LSB
Integral Nonlinearity (INL) Full ±0.4 ±1 ±0.4 ±1 LSB
TEMPERATURE DRIFT
Offset Error Full ±2 ±2 ppm/°C
Gain Error Full ±17 ±17 ppm/°C
Reference Voltage (1 V Mode) Full ±21 ±21 ppm/°C
REFERENCE
Output Voltage Error (VREF = 1 V) Full ±2 ±30 ±2 ±30 mV
Load Regulation at 1.0 mA (VREF = 1 V) Full 3 3 mV
Input Resistance Full 6 6 kΩ
ANALOG INPUTS
Differential Input Voltage (VREF = 1 V) Full 2 2 V p-p
Common-Mode Voltage Full AVDD/2 AVDD/2 V
Differential Input Capacitance Full 7 7 pF
Analog Bandwidth, Full Power Full 315 315 MHz
POWER SUPPLY
AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V
IAVDD Full 155 170 232 245 mA
IDRVDD Full 31 34 34 38 mA
Total Power Dissipation (Including Output Drivers) Full 335 367 478 510 mW
Power-Down Dissipation Full 2 5.8 2 5.8 mW
Standby Dissipation2 Full 72 72 mW
CROSSTALK Full −100 −100 dB
CROSSTALK (Overrange Condition)3 Full −100 −100 dB
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2
Can be controlled via the SPI.
3
Overrange condition is specific with 6 dB of the full-scale input range.
Data Sheet AD9228
AC SPECIFICATIONS
Table 2.
AD9228-40 AD9228-65
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz Full 70.5 70.2 dB
fIN = 19.7 MHz Full 68.5 70.2 70.0 dB
fIN = 35 MHz Full 70.2 68.5 70.0 dB
fIN = 70 MHz Full 70.0 69.5 dB
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)
fIN = 2.4 MHz Full 70.3 70.0 dB
fIN = 19.7 MHz Full 68.0 69.8 70.0 dB
fIN = 35 MHz Full 69.7 68.0 69.8 dB
fIN = 70 MHz Full 69.5 69.0 dB
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz Full 11.42 11.37 Bits
fIN = 19.7 MHz Full 11.1 11.37 11.33 Bits
fIN = 35 MHz Full 11.37 11.1 11.33 Bits
fIN = 70 MHz Full 11.33 11.25 Bits
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz Full 85 85 dBc
fIN = 19.7 MHz Full 72 82 85 dBc
fIN = 35 MHz Full 80 73 84 dBc
fIN = 70 MHz Full 80 74 dBc
WORST HARMONIC (Second or Third)
fIN = 2.4 MHz Full −85 −85 dBc
fIN = 19.7 MHz Full −82 −72 −85 dBc
fIN = 35 MHz Full −80 −84 −73 dBc
fIN = 70 MHz Full −80 −74 dBc
WORST OTHER (Excluding Second or Third)
fIN = 2.4 MHz Full −90 −90 dBc
fIN = 19.7 MHz Full −90 −80 −90 dBc
fIN = 35 MHz Full −90 −90 −79 dBc
fIN = 70 MHz Full −90 −88 dBc
TWO-TONE INTERMODULATION DISTORTION (IMD)—
AIN1 AND AIN2 = −7.0 dBFS
fIN1 = 15 MHz, fIN2 = 16 MHz 25°C 80.8 77.8 dBc
fIN1 = 70 MHz, fIN2 = 71 MHz 25°C 75.0 77.0 dBc
1
AD9228 Data Sheet
DIGITAL SPECIFICATIONS
Table 3.
AD9228-40 AD9228-65
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL
Differential Input Voltage2 Full 250 250 mV p-p
Input Common-Mode Voltage Full 1.2 1.2 V
Input Resistance (Differential) 25°C 20 20 kΩ
Input Capacitance 25°C 1.5 1.5 pF
LOGIC INPUTS (PDWN, SCLK/DTP)
Logic 1 Voltage Full 1.2 3.6 1.2 3.6 V
Logic 0 Voltage Full 0 0.3 0.3 V
Input Resistance 25°C 30 30 kΩ
LOGIC INPUT (CSB)
Logic 1 Voltage Full 1.2 3.6 1.2 3.6 V
Logic 0 Voltage Full 0 0.3 0.3 V
LOGIC INPUT (SDIO/ODM)
Logic 1 Voltage Full 1.2 DRVDD + 0.3 1.2 DRVDD + 0.3 V
Logic 0 Voltage Full 0 0.3 0 0.3 V
Input Capacitance 25°C 2 2 pF
LOGIC OUTPUT (SDIO/ODM)3
Logic 1 Voltage (IOH = 800 μA) Full 1.79 1.79 V
Logic 0 Voltage (IOL = 50 μA) Full 0.05 0.05 V
DIGITAL OUTPUTS (D + x, D − x), (ANSI-644)
Logic Compliance LVDS LVDS
Differential Output Voltage (VOD) Full 247 454 247 454 mV
Output Offset Voltage (VOS) Full 1.125 1.375 1.125 1.375 V
Output Coding (Default) Offset binary Offset binary
DIGITAL OUTPUTS (D + x, D − x),
(Low Power, Reduced Signal Option)
Logic Compliance LVDS LVDS
Differential Output Voltage (VOD) Full 150 250 150 250 mV
Output Offset Voltage (VOS) Full 1.10 1.30 1.10 1.30 V
Output Coding (Default) Offset binary Offset binary
1
2
This is specified for LVDS and LVPECL only.
3
This is specified for 13 SDIO pins sharing the same connection.
Data Sheet AD9228
SWITCHING SPECIFICATIONS
Table 4.
AD9228-40 AD9228-65
Parameter1, 2 Temp Min Typ Max Min Typ Max Unit
CLOCK3
Maximum Clock Rate Full 40 65 MSPS
Minimum Clock Rate Full 10 10 MSPS
Clock Pulse Width High (tEH) Full 12.5 7.7 ns
Clock Pulse Width Low (tEL) Full 12.5 7.7 ns
OUTPUT PARAMETERS3
Propagation Delay (tPD) Full 2.0 2.7 3.5 2.0 2.7 3.5 ns
Rise Time (tR) (20% to 80%) Full 300 300 ps
Fall Time (tF) (20% to 80%) Full 300 300 ps
FCO Propagation Delay (tFCO) Full 2.0 2.7 3.5 2.0 2.7 3.5 ns
DCO Propagation Delay (tCPD)4 Full tFCO + tFCO + ns
(tSAMPLE/24) (tSAMPLE/24)
DCO to Data Delay (tDATA)4 Full (tSAMPLE/24) − 300 (tSAMPLE/24) (tSAMPLE/24) + 300 (tSAMPLE/24) − 300 (tSAMPLE/24) (tSAMPLE/24) + 300 ps
DCO to FCO Delay (tFRAME)4 Full (tSAMPLE/24) − 300 (tSAMPLE/24) (tSAMPLE/24) + 300 (tSAMPLE/24) − 300 (tSAMPLE/24) (tSAMPLE/24) + 300 ps
Data to Data Skew Full ±50 ±150 ±50 ±150 ps
(tDATA-MAX − tDATA-MIN)
Wake-Up Time (Standby) 25°C 600 600 ns
Wake-Up Time (Power-Down) 25°C 375 375 μs
Pipeline Latency Full 8 8 CLK
cycles
APERTURE
Aperture Delay (tA) 25°C 500 500 ps
Aperture Uncertainty (Jitter) 25°C <1 <1 ps rms
Out-of-Range Recovery Time 25°C 1 2 CLK
cycles
1
2
Measured on standard FR-4 material.
3
Can be adjusted via the SPI.
4
tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
AD9228 Data Sheet
TIMING DIAGRAMS
N–1
VIN ± x tA
tEH tEL
CLK–
CLK+
tCPD
DCO–
DCO+
tFCO tFRAME
FCO–
FCO+
tPD tDATA
D–x
MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D10
05727-039
N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–8 N–8
D+x
Figure 2. 12-Bit Data Serial Stream, MSB First (Default)
N–1
VIN ± x
tA
tEH tEL
CLK–
CLK+
tCPD
DCO–
DCO+
tFCO tFRAME
FCO–
FCO+
tPD tDATA
D–x
MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D8 D7 D6 D5
N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–8 N–8 N–8 N–8 N–8
D+x
05727-040
Figure 3. 10-Bit Data Serial Stream, MSB First
Data Sheet AD9228
N–1
VIN ± x
tA
N
tEH tEL
CLK–
CLK+
tCPD
DCO–
DCO+
tFCO tFRAME
FCO–
FCO+
tPD tDATA
D–x
LSB D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 LSB D0
05727-041
N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–8 N–8
D+x
Figure 4. 12-Bit Data Serial Stream, LSB First
AD9228 Data Sheet
ABSOLUTE MAXIMUM RATINGS

Table 5. THERMAL IMPEDANCE
With Table 6.
Parameter Respect To Rating
Air Flow Velocity (m/sec) θJA1 θJB θJC Unit
ELECTRICAL
0.0 24 °C/W
AVDD AGND −0.3 V to +2.0 V
1.0 21 12.6 1.2 °C/W
DRVDD DRGND −0.3 V to +2.0 V
2.5 19 °C/W
AGND DRGND −0.3 V to +0.3 V
AVDD DRVDD −2.0 V to +2.0 V 1
θJA for a 4-layer printed circuit board (PCB) with solid ground plane
(simulated). Exposed pad soldered to PCB.
Digital Outputs DRGND −0.3 V to +2.0 V
(D + x, D − x, DCO+,
DCO−, FCO+, FCO−) ESD CAUTION
CLK+, CLK− AGND −0.3 V to +3.9 V
VIN + x, VIN − x AGND −0.3 V to +2.0 V
SDIO/ODM AGND −0.3 V to +2.0 V
PDWN, SCLK/DTP, CSB AGND −0.3 V to +3.9 V
REFT, REFB, RBIAS AGND −0.3 V to +2.0 V
VREF, SENSE AGND −0.3 V to +2.0 V
ENVIRONMENTAL
Operating Temperature −40°C to +85°C
Range (Ambient)
Maximum Junction 150°C
Temperature
Lead Temperature 300°C
(Soldering, 10 sec)
Storage Temperature −65°C to +150°C
Range (Ambient)
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Data Sheet AD9228
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
47 VIN + C
38 VIN + B
48 VIN – C
37 VIN – B
41 SENSE
40 RBIAS
46 AVDD
45 AVDD
39 AVDD
43 REFB
42 VREF
44 REFT
AVDD 1 36 AVDD
AVDD 2 35 AVDD
VIN – D 3 34 VIN – A
VIN + D 4 33 VIN + A
AD9228
AVDD 5 TOP VIEW 32 AVDD
(Not to Scale)
AVDD 6 31 PDWN
EXPOSED PADDLE, PIN 0
CLK– 7 (BOTTOM OF PACKAGE) 30 CSB
CLK+ 8 29 SDIO/ODM
AVDD 9 28 SCLK/DTP
AVDD 10 27 AVDD
DRGND 11 26 DRGND
DRVDD 12 25 DRVDD
D – D 13
D + D 14
D – C 15
D + C 16
D – B 17
D + B 18
D – A 19
D + A 20
FCO– 21
FCO+ 22
DCO– 23
05727-003
Figure 5. 48-Lead LFCSP Pin Configuration, Top View DCO+
Table 7. Pin Function Descriptions

Pin No. Mnemonic Description
0 AGND Analog Ground (Exposed Paddle). The exposed pad must be connected to analog ground.
1, 2, 5, 6, 9, 10, 27, 32, AVDD 1.8 V Analog Supply
35, 36, 39, 45, 46
11, 26 DRGND Digital Output Driver Ground
12, 25 DRVDD 1.8 V Digital Output Driver Supply
3 VIN − D ADC D Analog Input Complement
4 VIN + D ADC D Analog Input True
7 CLK− Input Clock Complement
8 CLK+ Input Clock True
13 D−D ADC D Digital Output Complement
14 D+D ADC D Digital Output True
15 D−C ADC C Digital Output Complement
16 D+C ADC C Digital Output True
17 D−B ADC B Digital Output Complement
18 D+B ADC B Digital Output True
19 D−A ADC A Digital Output Complement
20 D+A ADC A Digital Output True
21 FCO− Frame Clock Output Complement
22 FCO+ Frame Clock Output True
23 DCO− Data Clock Output Complement
24 DCO+ Data Clock Output True
28 SCLK/DTP Serial Clock/Digital Test Pattern
29 SDIO/ODM Serial Data IO/Output Driver Mode
30 CSB Chip Select Bar
31 PDWN Power-Down
33 VIN + A ADC A Analog Input True
34 VIN − A ADC A Analog Input Complement
AD9228 Data Sheet
Pin No. Mnemonic Description
37 VIN − B ADC B Analog Input Complement
38 VIN + B ADC B Analog Input True
40 RBIAS External resistor sets the internal ADC core bias current
41 SENSE Reference Mode Selection
42 VREF Voltage Reference Input/Output
43 REFB Differential Reference (Negative)
44 REFT Differential Reference (Positive)
47 VIN + C ADC C Analog Input True
48 VIN − C ADC C Analog Input Complement
Data Sheet AD9228
EQUIVALENT CIRCUITS
DRVDD
VIN ± x
V V
05727-030
D– D+
V V
05727-005
DRGND
Figure 6. Equivalent Analog Input Circuit Figure 9. Equivalent Digital Output Circuit
10Ω
CLK+
SCLK/DTP 1kΩ
AND
10kΩ PDWN
30kΩ
1.25V
10kΩ
10Ω
05727-033
CLK–
05727-032
Figure 7. Equivalent Clock Input Circuit Figure 10. Equivalent SCLK/DTP and PDWN Input Circuit
350Ω
SDIO/ODM
30kΩ 100Ω
05727-035
RBIAS
05727-031
Figure 8. Equivalent SDIO/ODM Input Circuit Figure 11. Equivalent RBIAS Circuit
AD9228 Data Sheet
AVDD
70kΩ
1kΩ VREF
05727-037
CSB
6kΩ
05727-034
Figure 12. Equivalent CSB Input Circuit Figure 14. Equivalent VREF Circuit
1kΩ
SENSE
05727-036
Figure 13. Equivalent SENSE Circuit
Data Sheet AD9228
TYPICAL PERFORMANCE CHARACTERISTICS

0 0
AIN = –0.5dBFS AIN = –0.5dBFS
SNR = 70.51dB SNR = 69.62dB
ENOB = 11.42 BITS ENOB = 11.27 BITS
–20 –20
SFDR = 86.00dBc SFDR = 72.48dBc
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–40 –40
–60 –60
–80 –80
–100 –100
05727-054
05727-052
–120 –120
0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 25 30
FREQUENCY (MHz) FREQUENCY (MHz)
Figure 15. Single-Tone 32k FFT with fIN = 2.4 MHz, fSAMPLE = 40 MSPS Figure 18. Single-Tone 32k FFT with fIN = 70 MHz, fSAMPLE = 65 MSPS
0 0
AIN = –0.5dBFS
AIN = –0.5dBFS SNR = 68.74dB
SNR = 70.38dB
–20 ENOB = 11.12 BITS
ENOB = 11.40 BITS –20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–40 –40
–60 –60
–80 –80
–100 –100
05727-055
05727-085
–120 –120
0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 25 30
Figure 16. Single-Tone 32k FFT with fIN = 35 MHz, fSAMPLE = 40 MSPS Figure 19. Single-Tone 32k FFT with fIN = 120 MHz, fSAMPLE = 65 MSPS
0 0
AIN = –0.5dBFS AIN = –0.5dBFS
SNR = 70.53dB SNR = 67.68dB
ENOB = 11.42 BITS ENOB = 10.95 BITS
–20 –20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–40 –40
–60 –60
–80 –80
–100 –100
05727-056
05727-053
–120 –120
0 5 10 15 20 25 30 0 5 10 15 20 25 30
Figure 17. Single-Tone 32k FFT with fIN = 2.3 MHz, fSAMPLE = 65 MSPS Figure 20. Single-Tone 32k FFT with fIN = 170 MHz, fSAMPLE = 65 MSPS
AD9228 Data Sheet
0 84
AIN = –0.5dBFS
SNR = 67.58dB
ENOB = 10.93 BITS 82
–20
SFDR = 68.39dBc
80
2V p-p, SFDR
AMPLITUDE (dBFS)
–40
SNR/SFDR (dB)
78
–60 76
74
–80
72
–100
70
05727-061
05727-057
2V p-p, SNR
–120 68
0 5 10 15 20 25 30 10 15 20 25 30 35 40
FREQUENCY (MHz) ENCODE (MSPS)
Figure 21. Single-Tone 32k FFT with fIN = 190 MHz, fSAMPLE = 65 MSPS Figure 24. SNR/SFDR vs. Encode, fIN = 35 MHz, fSAMPLE = 40 MSPS
0 90
AIN = –0.5dBFS
SNR = 65.56dB
ENOB = 10.6 BITS
–20 85
SFDR = 62.72dBc
2V p-p, SFDR
AMPLITUDE (dBFS)
–40 80
SNR/SFDR (dB)
–60 75
–80 70
–100 65
05727-058
05727-062
2V p-p, SNR
–120 60
0 5 10 15 20 25 30 10 20 30 40 50 60
FREQUENCY (MHz) ENCODE (MSPS)
Figure 22. Single-Tone 32k FFT with fIN = 250 MHz, fSAMPLE = 65 MSPS Figure 25. SNR/SFDR vs. Encode, fIN = 10.3 MHz, fSAMPLE = 65 MSPS
90 84
2V p-p, SFDR
82
85
2V p-p, SFDR
80
80
SNR/SFDR (dB)
SNR/SFDR (dB)
78
75 76
74
70
2V p-p, SNR
72
65
70
05727-059
05727-064
2V p-p, SNR
60 68
10 15 20 25 30 35 40 10 20 30 40 50 60
ENCODE (MSPS) ENCODE (MSPS)
Figure 23. SNR/SFDR vs. Encode, fIN = 10.3 MHz, fSAMPLE = 40 MSPS Figure 26. SNR/SFDR vs. Encode, fIN = 35 MHz, fSAMPLE = 65 MSPS
Data Sheet AD9228
100 100
90 fIN = 10.3MHz 90
fIN = 35MHz
fSAMPLE = 40MSPS fSAMPLE = 65MSPS 2V p-p, SFDR
80 80
2V p-p, SFDR
70 70
SNR/SFDR (dB)
SNR/SFDR (dB)
60 60
50 80dB 50 2V p-p, SNR

REFERENCE
2V p-p, SNR
40 40
80dB
REFERENCE
30 30
20 20
05727-070
05727-065
10 10
0 0
–60 –50 –40 –30 –20 –10 0 –60 –50 –40 –30 –20 –10 0
ANALOG INPUT LEVEL (dBFS) ANALOG INPUT LEVEL (dBFS)
Figure 27. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, fSAMPLE = 40 MSPS Figure 30. SNR/SFDR vs. Analog Input Level, fIN = 35 MHz, fSAMPLE = 65 MSPS
100 0
AIN1 AND AIN2 = –7dBFS
90 fIN = 35MHz SFDR = 80.75dBc
fSAMPLE = 40MSPS IMD2 = 85.53dBc
–20
80 IMD3 = 80.83dBc
2V p-p, SFDR
70
AMPLITUDE (dBFS)
–40
SNR/SFDR (dB)
60
50 80dB –60
REFERENCE 2V p-p, SNR
40
–80
30
20
–100
05727-049
05727-066
10
0 –120
–60 –50 –40 –30 –20 –10 0 0 2 4 6 8 10 12 14 16 18 20
ANALOG INPUT LEVEL (dBFS) FREQUENCY (MHz)
Figure 28. SNR/SFDR vs. Analog Input Level, fIN = 35 MHz, fSAMPLE = 40 MSPS Figure 31. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz,
fSAMPLE = 40 MSPS
100 0
90 fIN = 10.3MHz SFDR = 74.76dBc
fSAMPLE = 65MSPS 2V p-p, SFDR IMD2 = 81.03dBc
–20
80 IMD3 = 75.00dBc
70
AMPLITUDE (dBFS)
–40
SNR/SFDR (dB)
60
50 80dB –60
REFERENCE 2V p-p, SNR
40
30 –80
20
–100
05727-068
10
05727-050
0 –120
–60 –50 –40 –30 –20 –10 0 0 2 4 6 8 10 12 14 16 18 20
ANALOG INPUT LEVEL (dBFS) FREQUENCY (MHz)
Figure 29. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, fSAMPLE = 65 MSPS Figure 32. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz,
fSAMPLE = 40 MSPS
AD9228 Data Sheet
0 90
SFDR = 78.15dBc
IMD2 = 77.84dBc
–20 85
IMD3 = 88.94dBc
2V p-p, SFDR
AMPLITUDE (dBFS)
–40 80
SINAD/SFDR (dB)
–60 75
–80 70
2V p-p, SINAD
–100 65
05727-048
05727-072
–120 60
0 5 10 15 20 25 30 –40 –20 0 20 40 60 80
FREQUENCY (MHz) TEMPERATURE (°C)
Figure 33. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz, Figure 36. SINAD/SFDR vs. Temperature, fIN = 10.3 MHz, fSAMPLE = 65 MSPS
fSAMPLE = 65 MSPS
0 1.0
SFDR = 76.75dBc 0.8
IMD2 = 77.56dBc
–20
IMD3 = 77.01dBc 0.6
0.4
AMPLITUDE (dBFS)
–40
0.2
INL (LSB)
–60 0
–0.2
–80
–0.4
–0.6
–100
05727-051
05727-073
–0.8
–120 –1.0
0 5 10 15 20 25 30 0 500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (MHz)
CODE
Figure 34. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz, Figure 37. INL, fIN = 2.4 MHz, fSAMPLE = 65 MSPS
fSAMPLE = 65 MSPS
90 0.5
85 0.4
2V p-p, SFDR
0.3
80
0.2
SNR/SFDR (dB)
75
0.1
DNL (LSB)
70 0
2V p-p, SNR
65 –0.1
–0.2
60
–0.3
55
05727-071
05727-074
–0.4
50 –0.5
1 10 100 1000 0 500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (MHz) CODE
Figure 35. SNR/SFDR vs. Frequency, fSAMPLE = 65 MSPS Figure 38. DNL, fIN = 2.4 MHz, fSAMPLE = 65 MSPS
Data Sheet AD9228
–45.0 0
NPR = 60.83dB
NOTCH = 18.0MHz
–45.5 –20 NOTCH WIDTH = 3.0MHz
AMPLITUDE (dBFS)
–46.0 –40
CMRR (dB)
–46.5 –60
–47.0 –80
–47.5 –100
05727-076
05727-075
–48.0 –120
10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30
Figure 39. CMRR vs. Frequency, fSAMPLE = 65 MSPS Figure 41. Noise Power Ratio (NPR), fSAMPLE = 65 MSPS
1.2 0
0.26 LSB rms
–1
1.0
–2
NUMBER OF HITS (Millions)
FUNDAMENTAL LEVEL (dB) –3 –3dB CUTOFF = 315MHz

0.8
–4
0.6 –5
–6
0.4
–7
–8
0.2
05727-086
05727-077
–9
0 –10
N–3 N–2 N–1 N N+1 N+2 N+3 0 50 100 150 200 250 300 350 400 450 500
CODE FREQUENCY (MHz)
Figure 40. Input-Referred Noise Histogram, fSAMPLE = 65 MSPS Figure 42. Full-Power Bandwidth vs. Frequency, fSAMPLE = 65 MSPS
AD9228 Data Sheet
THEORY OF OPERATION
The AD9228 architecture consists of a pipelined ADC divided into The clock signal alternately switches the input circuit between
three sections: a 4-bit first stage followed by eight 1.5-bit stages and sample mode and hold mode (see Figure 43). When the input
a final 3-bit flash. Each stage provides sufficient overlap to circuit is switched to sample mode, the signal source must be
correct for flash errors in the preceding stage. The quantized capable of charging the sample capacitors and settling within
outputs from each stage are combined into a final 12-bit result one-half of a clock cycle. A small resistor in series with each
in the digital correction logic. The pipelined architecture permits input can help reduce the peak transient current injected from
the first stage to operate with a new input sample while the the output stage of the driving source. In addition, low-Q inductors
remaining stages operate with preceding samples. Sampling or ferrite beads can be placed on each leg of the input to reduce
occurs on the rising edge of the clock. high differential capacitance at the analog inputs and therefore
achieve the maximum bandwidth of the ADC. Such use of
Each stage of the pipeline, excluding the last, consists of a low low-Q inductors or ferrite beads is required when driving the
resolution flash ADC connected to a switched-capacitor DAC converter front end at high IF frequencies. Either a shunt
and an interstage residue amplifier (for example, a multiplying capacitor or two single-ended capacitors can be placed on the
digital-to-analog converter (MDAC)). The residue amplifier inputs to provide a matching passive network. This ultimately
magnifies the difference between the reconstructed DAC creates a low-pass filter at the input to limit unwanted
output and the flash input for the next stage in the pipeline. One broadband noise. See the AN-742 Application Note, the AN-827
bit of redundancy is used in each stage to facilitate digital Application Note, and the Analog Dialogue article Transformer-
correction of flash errors. The last stage simply consists of a Coupled Front-End for Wideband A/D Converters (Volume 39,
flash ADC. April 2005) for more information. In general, the precise values
The output staging block aligns the data, corrects errors, and depend on the application.
passes the data to the output buffers. The data is then serialized The analog inputs of the AD9228 are not internally dc-biased.
and aligned to the frame and data clocks. Therefore, in ac-coupled applications, the user must provide
ANALOG INPUT CONSIDERATIONS this bias externally. Setting the device so that VCM = AVDD/2 is
recommended for optimum performance, but the device can
The analog input to the AD9228 is a differential switched-
function over a wider range with reasonable performance, as
capacitor circuit designed for processing differential input
shown in Figure 44 to Figure 47.
signals. This circuit can support a wide common-mode range
while maintaining excellent performance. By using an input
common-mode voltage of midsupply, users can minimize
signal-dependent errors and achieve optimum performance.
CPAR
H
VIN + x
CSAMPLE
S S
S S
CSAMPLE
VIN – x
H
CPAR
H
05727-006
Figure 43. Switched-Capacitor Input Circuit
Data Sheet AD9228
90 90
SFDR (dBc)
85 85
80 80 SFDR (dBc)
SNR/SFDR (dB)
SNR/SFDR (dB)
75 75
SNR (dB)
70 70
SNR (dB)
65 65
60 60
55 55
05727-078
05727-100
50 50
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
ANALOG INPUT COMMON-MODE VOLTAGE (V)
ANALOG INPUT COMMON-MODE VOLTAGE (V)
Figure 44. SNR/SFDR vs. Common-Mode Voltage, Figure 46. SNR/SFDR vs. Common-Mode Voltage,
fIN = 2.4 MHz, fSAMPLE = 65 MSPS fIN = 2.4 MHz, fSAMPLE = 40 MSPS
90 90
SFDR (dBc)
85 85
80 80 SFDR (dBc)
SNR/SFDR (dB)
SNR/SFDR (dB)
75 75
SNR (dB)
70 70
SNR (dB)
65 65
60 60
55 55
05727-079
05727-101
50 50
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
ANALOG INPUT COMMON-MODE VOLTAGE (V) ANALOG INPUT COMMON-MODE VOLTAGE (V)
Figure 45. SNR/SFDR vs. Common-Mode Voltage, Figure 47. SNR/SFDR vs. Common-Mode Voltage,
fIN = 30 MHz, fSAMPLE = 65 MSPS fIN = 30 MHz, fSAMPLE = 40 MSPS
AD9228 Data Sheet
ADT1-1WT
For best dynamic performance, the source impedances driving 1:1 Z RATIO C
R
VIN + x and VIN − x must be matched such that common- VIN + x
mode settling errors are symmetrical. These errors are reduced 2V p-p 49.9Ω
ADC
*CDIFF AD9228
by the common-mode rejection of the ADC. An internal R
AVDD VIN – x AGND
reference buffer creates the positive and negative reference 1kΩ
C
voltages, REFT and REFB, respectively, that define the span of
1kΩ *CDIFF IS OPTIONAL
the ADC core. The output common-mode of the reference buffer
05727-008
0.1μF
is set to midsupply, and the REFT and REFB voltages and span
are defined as Figure 48. Differential Transformer-Coupled Configuration
REFT = 1/2 (AVDD + VREF) for Baseband Applications
REFB = 1/2 (AVDD − VREF) 2V p-p ADT1-1WT
16nH 0.1μF 1:1 Z RATIO 16nH 33Ω
Span = 2 × (REFT − REFB) = 2 × VREF VIN + x
65Ω ADC
499Ω 2.2pF 1kΩ
It can be seen from these equations that the REFT and REFB 16nH AD9228
33Ω
VIN – x
voltages are symmetrical about the midsupply voltage and, by
AVDD
definition, the input span is twice the value of the VREF voltage.
1kΩ
05727-047
Maximum SNR performance is achieved by setting the ADC to 1kΩ 0.1μF
the largest span in a differential configuration. In the case of the
AD9228, the largest input span available is 2 V p-p. Figure 49. Differential Transformer-Coupled Configuration
for IF Applications
Differential Input Configurations
Single-Ended Input Configuration
There are several ways to drive the AD9228 either actively or
passively; however, optimum performance is achieved by driving A single-ended input may provide adequate performance in cost-
the analog input differentially. For example, using the AD8332 sensitive applications. In this configuration, SFDR and distortion
differential driver to drive the AD9228 provides excellent perfor- performance degrade due to the large input common-mode swing.
mance and a flexible interface to the ADC (see Figure 51) for If the application requires a single-ended input configuration,
baseband applications. This configuration is commonly used ensure that the source impedances on each input are well matched
for medical ultrasound systems. in order to achieve the best possible performance. A full-scale
input of 2 V p-p can be applied to the VIN + x pin of the ADC
For applications where SNR is a key parameter, differential while the VIN − x pin is terminated. Figure 50 details a typical
transformer coupling is the recommended input configuration single-ended input configuration.
(see Figure 48 and Figure 49), because the noise performance of
AVDD
most amplifiers is not adequate to achieve the true performance
C
of the AD9228. R
VIN + x
2V p-p 49.9Ω 0.1µF 1kΩ
Regardless of the configuration, the value of the shunt ADC
*CDIFF
capacitor, C, is dependent on the input frequency and may AVDD AD9228
1kΩ 25Ω
need to be reduced or removed. R
VIN – x
0.1µF 1kΩ C
05727-009
*CDIFF IS OPTIONAL
Figure 50. Single-Ended Input Configuration

0.1μF
LOP VIP
AVDD
187Ω 680nH 33Ω 10kΩ

0.1μF 120nH INH VOH
VIN + x
1V p-p
AD8332 10kΩ 1kΩ
22pF
LNA VGA
+ AVDD ADC
68pF
AD9228
33Ω 10kΩ
0.1μF LMD VIN – x
VOL 187Ω 680nH 10kΩ
LON VIN LPF

05727-007
18nF 274Ω 0.1μF
Figure 51. Differential Input Configuration Using the AD8332 with Two-Pole, 16 MHz Low-Pass Filter
Data Sheet AD9228
CLOCK INPUT CONSIDERATIONS in parallel with a 39 kΩ resistor (see Figure 55). Although the
For optimum performance, the AD9228 sample clock inputs CLK+ input circuit supply is AVDD (1.8 V), this input is
(CLK+ and CLK−) must be clocked with a differential signal. designed to withstand input voltages of up to 3.3 V and
This signal is typically ac-coupled to the CLK+ and CLK− pins therefore offers several selections for the drive logic voltage.
via a transformer or capacitors. These pins are biased internally AD9510/AD9511/
and require no additional biasing. AD9512/AD9513/
0.1µF AD9514/AD9515
CLK+ CLK
Figure 52 shows a preferred method for clocking the AD9228. The OPTIONAL
50Ω* 100Ω
CMOS DRIVER CLK+
low jitter clock source is converted from a single-ended signal 0.1µF
ADC
to a differential signal using an RF transformer. The back-to- CLK AD9228
0.1µF
back Schottky diodes across the secondary transformer limit CLK–
clock excursions into the AD9228 to approximately 0.8 V p-p 0.1µF 39kΩ
05727-027
differential. This helps prevent the large voltage swings of the
*50Ω RESISTOR IS OPTIONAL
clock from feeding through to other portions of the AD9228,
Figure 55. Single-Ended 1.8 V CMOS Sample Clock
and it preserves the fast rise and fall times of the signal, which
are critical to low jitter performance. AD9510/AD9511/
AD9512/AD9513/
0.1µF AD9514/AD9515
CLK+ CLK
OPTIONAL
Mini-Circuits® 100Ω
50Ω*
ADT1-1WT, 1:1Z CMOS DRIVER CLK+
0.1µF 0.1µF 0.1µF
XFMR ADC
CLK+ CLK+ CLK AD9228
50Ω 100Ω ADC 0.1µF 0.1µF
0.1µF AD9228 CLK–
05727-024
CLK–
05727-028
SCHOTTKY *50Ω RESISTOR IS OPTIONAL
0.1µF
DIODES:
HSM2812 Figure 56. Single-Ended 3.3 V CMOS Sample Clock
Figure 52. Transformer-Coupled Differential Clock
Clock Duty Cycle Considerations
Another option is to ac-couple a differential PECL signal to the Typical high speed ADCs use both clock edges to generate a
sample clock input pins as shown in Figure 53. The AD9510/ variety of internal timing signals. As a result, these ADCs may
AD9511/AD9512/AD9513/AD9514/AD9515 family of clock be sensitive to the clock duty cycle. Commonly, a 5% tolerance is
drivers offers excellent jitter performance. required on the clock duty cycle to maintain dynamic
AD9510/AD9511/
performance characteristics. The AD9228 contains a duty cycle
AD9512/AD9513/ stabilizer (DCS) that retimes the nonsampling edge, providing
0.1µF AD9514/AD9515 0.1µF
CLK+ CLK CLK+
an internal clock signal with a nominal 50% duty cycle. This
ADC allows a wide range of clock input duty cycles without affecting
PECL DRIVER 100Ω
AD9228 the performance of the AD9228. When the DCS is on, noise
0.1µF 0.1µF
CLK– CLK–
CLK and distortion performance are nearly flat for a wide range of
05727-025
50Ω* 50Ω* 240Ω 240Ω

duty cycles. However, some applications may require the DCS
*50Ω RESISTORS ARE OPTIONAL
function to be off. If so, keep in mind that the dynamic range
Figure 53. Differential PECL Sample Clock
performance can be affected when operated in this mode. See the
Memory Map section for more details on using this feature.
AD9510/AD9511/
AD9512/AD9513/ Jitter in the rising edge of the input is an important concern, and it
0.1µF AD9514/AD9515 0.1µF
CLK+ CLK CLK+ is not reduced by the internal stabilization circuit. The duty
100Ω ADC cycle control loop does not function for clock rates of less than
LVDS DRIVER AD9228 20 MHz nominal. The loop has a time constant associated with
0.1µF 0.1µF
CLK– CLK CLK–
it that must be considered in applications where the clock rate
05727-026
50Ω* 50Ω*
can change dynamically. This requires a wait time of 1.5 μs to
*50Ω RESISTORS ARE OPTIONAL
5 μs after a dynamic clock frequency increase (or decrease)
Figure 54. Differential LVDS Sample Clock before the DCS loop is relocked to the input signal. During the
period that the loop is not locked, the DCS loop is bypassed and
In some applications, it is acceptable to drive the sample clock the internal device timing is dependent on the duty cycle of the
inputs with a single-ended CMOS signal. In such applications, input clock signal. In such applications, it may be appropriate
CLK+ must be driven directly from a CMOS gate, and the to disable the duty cycle stabilizer. In all other applications,
CLK− pin must be bypassed to ground with a 0.1 μF capacitor enabling the DCS circuit is recommended to maximize ac
performance.
AD9228 Data Sheet
Clock Jitter Considerations Power Dissipation and Power-Down Mode
High speed, high resolution ADCs are sensitive to the quality of the As shown in Figure 58 and Figure 59, the power dissipated by
clock input. The degradation in SNR at a given input frequency (fA) the AD9228 is proportional to its sample rate. The digital
due only to aperture jitter (tJ) can be calculated by power dissipation does not vary significantly because it is
SNR Degradation = 20 × log 10(1/2 × π × fA × tJ) determined primarily by the DRVDD supply and bias current of
the LVDS output drivers.
In this equation, the rms aperture jitter represents the root mean 180 360
square of all jitter sources, including the clock input, analog input
160 340
signal, and ADC aperture jitter. IF undersampling applications
AVDD CURRENT
are particularly sensitive to jitter (see Figure 57). 140 320
120 TOTAL POWER 300

The clock input must be treated as an analog signal in cases
CURRENT (mA)
POWER (mW)
where aperture jitter may affect the dynamic range of the AD9228. 100 280
Power supplies for clock drivers must be separated from the 80 260
ADC output driver supplies to avoid modulating the clock signal
60 240
with digital noise. Low jitter, crystal-controlled oscillators are
the best clock sources. If the clock is generated from another 40 DRVDD CURRENT 220
type of source (by gating, dividing, or another method), it must 20 200

be retimed by the original clock during the last step.
0 180
05727-089
10 15 20 25 30 35 40
Refer to the AN-501 Application Note and to the AN-756 ENCODE (MSPS)
Application Note for more in-depth information about jitter Figure 58. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 40 MSPS
performance as it relates to ADCs. 250 480
130 460
RMS CLOCK JITTER REQUIREMENT
120 200 AVDD CURRENT
440
110
420
TOTAL POWER
CURRENT (mA)
POWER (mW)
100 16 BITS 150
400
90 14 BITS
SNR (dB)
380
80 100
12 BITS
360
70
10 BITS 340
60 50
0.125 ps DRVDD CURRENT
50 0.25 ps 320
0.5 ps
05727-038
40 1.0 ps 0 300
05727-081
2.0 ps 10 20 30 40 50 60
30 ENCODE (MSPS)
1 10 100 1000
ANALOG INPUT FREQUENCY (MHz) Figure 59. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 65 MSPS
Figure 57. Ideal SNR vs. Input Frequency and Jitter
Data Sheet AD9228
By asserting the PDWN pin high, the AD9228 is placed into placed as close to the receiver as possible. If there is no far-end
power-down mode. In this state, the ADC typically dissipates receiver termination or there is poor differential trace routing,
3 mW. During power-down, the LVDS output drivers are placed timing errors may result. To avoid such timing errors, it is
into a high impedance state. If any of the SPI features are recommended that the trace length be less than 24 inches and
changed before the power-down feature is enabled, the chip that the differential output traces be close together and at equal
continues to function after PDWN is pulled low without lengths. An example of the FCO and data stream with proper
requiring a reset. The AD9228 returns to normal operating mode trace length and position is shown in Figure 60.
when the PDWN pin is pulled low. This pin is both 1.8 V and
3.3 V tolerant.
In power-down mode, low power dissipation is achieved by

shutting down the reference, reference buffer, PLL, and biasing
networks. The decoupling capacitors on REFT and REFB are
discharged when entering power-down mode and must be
recharged when returning to normal operation. As a result, the
wake-up time is related to the time spent in the power-down
mode: shorter cycles result in proportionally shorter wake-up
times. With the recommended 0.1 μF and 2.2 μF decoupling
capacitors on REFT and REFB, approximately 1 sec is required
05727-045
to fully discharge the reference buffer decoupling capacitors
CH1 200mV/DIV = DCO 2.5ns/DIV
and approximately 375 μs is required to restore full operation. CH2 200mV/DIV = DATA
CH3 500mV/DIV = FCO
There are several other power-down options available when Figure 60. AD9228-65, LVDS Output Timing Example in ANSI-644 Mode (Default)
using the SPI. The user can individually power down each
channel or put the entire device into standby mode. The latter An example of the LVDS output using the ANSI-644 standard
option allows the user to keep the internal PLL powered when (default) data eye and a time interval error (TIE) jitter histogram
fast wake-up times (~600 ns) are required. See the Memory with trace lengths less than 24 inches on standard FR-4 material
Map section for more details on using these features. is shown in Figure 61. Figure 62 shows an example of trace
lengths exceeding 24 inches on standard FR-4 material. Notice
Digital Outputs and Timing that the TIE jitter histogram reflects the decrease of the data eye
The AD9228 differential outputs conform to the ANSI-644 opening as the edge deviates from the ideal position. It is the
LVDS standard on default power-up. This can be changed to a low user’s responsibility to determine if the waveforms meet the
power, reduced signal option (similar to the IEEE 1596.3 standard) timing budget of the design when the trace lengths exceed 24
via the SDIO/ODM pin or SPI. The LVDS standard can further inches. Additional SPI options allow the user to further increase
reduce the overall power dissipation of the device by the internal termination (increasing the current) of all four
approximately 15 mW. See the SDIO/ODM Pin section or Table outputs in order to drive longer trace lengths (see Figure 63).
16 in the Memory Map section for more information. The LVDS Even though this produces sharper rise and fall times on the
driver current is derived on-chip and sets the output current at data edges and is less prone to bit errors, the power dissipation of
each output equal to a nominal 3.5 mA. A 100 Ω differential the DRVDD supply increases when this option is used. In
termination resistor placed at the LVDS receiver inputs results in addition, notice in Figure 63 that the histogram is improved
a nominal 350 mV swing at the receiver. compared with that shown in Figure 62. See the Memory Map
section for more details.
The AD9228 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended with a 100 Ω termination resistor
AD9228 Data Sheet
500 EYE: ALL BITS ULS: 10000/15600 400 EYE: ALL BITS ULS: 9599/15599
EYE DIAGRAM VOLTAGE (V)

200
0 0
–200
–500 –400
–1ns –0.5ns 0ns 0.5ns 1ns –1ns –0.5ns 0ns 0.5ns 1ns
100
TIE JITTER HISTOGRAM (Hits)

100
50
50
05727-042
05727-043
0 0
–100ps 0ps 100ps –150ps –100ps –50ps 0ps 50ps 100ps 150ps
Figure 61. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Figure 63. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Internal
Less than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only Termination on and Trace Lengths Greater than 24 Inches on Standard FR-4,
External 100 Ω Far Termination Only
ULS: 9600/15600
200 EYE: ALL BITS
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 8.
To change the output data format to twos complement, see the

Memory Map section.
0
Table 8. Digital Output Coding

(VIN + x) − (VIN − x), Digital Output Offset Binary
Code Input Span = 2 V p-p (V) (D11 ... D0)
4095 +1.00 1111 1111 1111
–200 2048 0.00 1000 0000 0000
2047 −0.000488 0111 1111 1111
–1ns –0.5ns 0ns 0.5ns 1ns
0 −1.00 0000 0000 0000
100
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 12 bits
times the sample clock rate, with a maximum of 780 Mbps

(12 bits × 65 MSPS = 780 Mbps). The lowest typical conversion
rate is 10 MSPS. However, if lower sample rates are required for
50 a specific application, the PLL can be set up via the SPI to allow
encode rates as low as 5 MSPS. See the Memory Map section
for details on enabling this feature.
05727-044
0
–150ps –100ps –50ps 0ps 50ps 100ps 150ps
Figure 62. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Greater than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only
Data Sheet AD9228
Two output clocks are provided to assist in capturing data from capturing. The FCO is used to signal the start of a new output
the AD9228. The DCO is used to clock the output data and is byte and is equal to the sample clock rate. See the timing
equal to six times the sample clock (CLK) rate. Data is clocked diagram shown in Figure 2 for more information.
out of the AD9228 and must be captured on the rising and
falling edges of the DCO that supports double data rate (DDR)
Table 9. Flexible Output Test Modes

Output Test Mode Subject to Data
Bit Sequence Pattern Name Digital Output Word 1 Digital Output Word 2 Format Select
0000 Off (default) N/A N/A N/A
0001 Midscale short 1000 0000 (8-bit) Same Yes
10 0000 0000 (10-bit)
1000 0000 0000 (12-bit)
10 0000 0000 0000 (14-bit)
0010 +Full-scale short 1111 1111 (8-bit) Same Yes
11 1111 1111 (10-bit)
1111 1111 1111 (12-bit)
11 1111 1111 1111 (14-bit)
0011 −Full-scale short 0000 0000 (8-bit) Same Yes
00 0000 0000 (10-bit)
0000 0000 0000 (12-bit)
00 0000 0000 0000 (14-bit)
0100 Checkerboard 1010 1010 (8-bit) 0101 0101 (8-bit) No
10 1010 1010 (10-bit) 01 0101 0101 (10-bit)
1010 1010 1010 (12-bit) 0101 0101 0101 (12-bit)
10 1010 1010 1010 (14-bit) 01 0101 0101 0101 (14-bit)
0101 PN sequence long1 N/A N/A Yes
0110 PN sequence short1 N/A N/A Yes
0111 One-/zero-word toggle 1111 1111 (8-bit) 0000 0000 (8-bit) No
11 1111 1111 (10-bit) 00 0000 0000 (10-bit)
1111 1111 1111 (12-bit) 0000 0000 0000 (12-bit)
11 1111 1111 1111 (14-bit) 00 0000 0000 0000 (14-bit)
1000 User input Register 0x19 to Register 0x1A Register 0x1B to Register 0x1C No
1001 1-/0-bit toggle 1010 1010 (8-bit) N/A No
10 1010 1010 (10-bit)
1010 1010 1010 (12-bit)
10 1010 1010 1010 (14-bit)
1010 1× sync 0000 1111 (8-bit) N/A No
00 0001 1111 (10-bit)
0000 0011 1111 (12-bit)
00 0000 0111 1111 (14-bit)
1011 One bit high 1000 0000 (8-bit) N/A No
10 0000 0000 (10-bit)
1000 0000 0000 (12-bit)
10 0000 0000 0000 (14-bit)
1100 Mixed frequency 1010 0011 (8-bit) N/A No
10 0110 0011 (10-bit)
1010 0011 0011 (12-bit)
10 1000 0110 0111 (14-bit)
1
All test mode options except PN sequence short and PN sequence long can support 8-bit to 14-bit word lengths in order to verify data capture to the receiver.
AD9228 Data Sheet
When the SPI is used, the DCO phase can be adjusted in 60° Table 10. PN Sequence
Initial First Three Output Samples
increments relative to one data cycle (30° relative to one DCO
Sequence Value (MSB First)
cycle). This enables the user to refine system timing margins if PN Sequence Short 0x0df 0xdf9, 0x353, 0x301
required. The default DCO± to output data edge timing, as PN Sequence Long 0x29b80a 0x591, 0xfd7, 0x0a3
shown in Figure 2, is 180° relative to one data cycle (90° relative
to one DCO cycle
Consult the Memory Map section for information on how to
An 8-bit, 10-bit, or 14-bit serial stream can also be initiated change these additional digital output timing features through
from the SPI. This allows the user to implement and test the SPI.
compatibility to lower and higher resolution systems. When
SDIO/ODM Pin
changing the resolution to an 8-bit or 10-bit serial stream, the
data stream is shortened. See Figure 3 for the 10-bit example. The SDIO/ODM pin is for use in applications that do not require
However, when using the 14-bit option, the data stream stuffs SPI mode operation. This pin can enable a low power, reduced
two 0s at the end of the 14-bit serial data. signal option (similar to the IEEE 1596.3 reduced range link
output standard) if it and the CSB pin are tied to AVDD during
When the SPI is used, all of the data outputs can also be device power-up. This option must only be used when the digital
inverted from their nominal state. This is not to be confused output trace lengths are less than 2 inches from the LVDS receiver.
with inverting the serial stream to an LSB-first mode. In default When this option is used, the FCO, DCO, and outputs function
mode, as shown in Figure 2, the MSB is first in the data output normally, but the LVDS signal swing of all channels is reduced
serial stream. However, this can be inverted so that the LSB is from 350 mV p-p to 200 mV p-p, allowing the user to further
first in the data output serial stream (see Figure 4). reduce the power on the DRVDD supply.
There are 12 digital output test pattern options available that For applications where this pin is not used, it must be tied low. In
can be initiated through the SPI. This is a useful feature when this case, the device pin can be left open, and the 30 kΩ internal
validating receiver capture and timing. Refer to Table 9 for the pull-down resistor pulls this pin low. This pin is only 1.8 V
output bit sequencing options available. Some test patterns tolerant. If applications require this pin to be driven from a 3.3 V
have two serial sequential words and can be alternated in logic level, insert a 1 kΩ resistor in series with this pin to limit
various ways, depending on the test pattern chosen. Note that the current.
some patterns do not adhere to the data format select option. In
addition, custom user-defined test patterns can be assigned in Table 11. Output Driver Mode Pin Settings
the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode Resulting Resulting
options except PN sequence short and PN sequence long can Selected ODM ODM Voltage Output Standard FCO and DCO
support 8-bit to 14-bit word lengths in order to verify data Normal 10 kΩ to AGND ANSI-644 ANSI-644
Operation (default) (default)
capture to the receiver.
ODM AVDD Low power, Low power,
reduced reduced
The PN sequence short pattern produces a pseudorandom bit signal option signal option
sequence that repeats itself every 29 − 1 or 511 bits. A descript-
tion of the PN sequence and how it is generated can be found in
Section 5.1 of the ITU-T 0.150 (05/96) standard. The only
difference is that the starting value must be a specific value
instead of all 1s (see Table 10 for the initial values).
The PN sequence long pattern produces a pseudorandom bit

sequence that repeats itself every 223 − 1 or 8,388,607 bits. A
description of the PN sequence and how it is generated can be
found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The
only differences are that the starting value must be a specific
value instead of all 1s (see Table 10 for the initial values) and the
AD9228 inverts the bit stream with relation to the ITU standard.
Data Sheet AD9228
SCLK/DTP Pin RBIAS Pin
The SCLK/DTP pin is for use in applications that do not To set the internal core bias current of the ADC, place a resistor
require SPI mode operation. This pin can enable a single digital (nominally equal to 10.0 kΩ) to ground at the RBIAS pin. The
test pattern if it and the CSB pin are held high during device resistor current is derived on-chip and sets the AVDD current of
power-up. When SCLK/DTP is tied to AVDD, the ADC the ADC to a nominal 232 mA at 65 MSPS. Therefore, it is
channel outputs shift out the following pattern: 1000 0000 imperative that at least a 1% tolerance on this resistor be used
0000. The FCO and DCO function normally while all channels to achieve consistent performance.
shift out the repeatable test pattern. This pattern allows the user
to perform timing alignment adjustments among the FCO, DCO,
Voltage Reference
and output data. For normal operation, this pin must be tied to A stable, accurate 0.5 V voltage reference is built into the
AGND through a 10 kΩ resistor. This pin is both 1.8 V and 3.3 V AD9228. It is gained up internally by a factor of 2, setting VREF
tolerant. to 1.0 V, which results in a full-scale differential input span of
2 V p-p. The VREF is set internally by default; however, the
Table 12. Digital Test Pattern Pin Settings VREF pin can be driven externally with a 1.0 V reference to
Resulting Resulting improve accuracy.
Selected DTP DTP Voltage D + x and D − x FCO and DCO
Normal 10 kΩ to AGND Normal Normal operation When applying the decoupling capacitors to the VREF, REFT,
Operation operation and REFB pins, use ceramic low ESR capacitors. These capacitors
DTP AVDD 1000 0000 0000 Normal operation must be close to the ADC pins and on the same layer of the
Additional and custom test patterns can also be observed when PCB as the AD9228. The recommended capacitor values and
commanded from the SPI port. Consult the Memory Map configurations for the AD9228 reference pin are shown in
section for information about the options available. Figure 64.
CSB Pin Table 13. Reference Settings

The CSB pin must be tied to AVDD for applications that do not Resulting
require SPI mode operation. By tying CSB high, all SCLK and Differential
Selected Mode SENSE Voltage Resulting VREF (V) Span (V p-p)
SDIO information is ignored. This pin is both 1.8 V and 3.3 V
External AVDD N/A 2 × external
tolerant. Reference reference
Internal, AGND to 0.2 V 1.0 2.0
2 V p-p FSR
AD9228 Data Sheet
Internal Reference Operation External Reference Operation
A comparator within the AD9228 detects the potential at the The use of an external reference may be necessary to enhance
SENSE pin and configures the reference. If SENSE is grounded, the gain accuracy of the ADC or to improve thermal drift
the reference amplifier switch is connected to the internal characteristics. Figure 67 shows the typical drift characteristics
resistor divider (see Figure 64), setting VREF to 1 V. of the internal reference in 1 V mode.
The REFT and REFB pins establish the input span of the ADC When the SENSE pin is tied to AVDD, the internal reference is
core from the reference configuration. The analog input full- disabled, allowing the use of an external reference. The external
scale range of the ADC equals twice the voltage of the reference reference is loaded with an equivalent 6 kΩ load. An internal
pin for either an internal or an external reference configuration. reference buffer generates the positive and negative full-scale
references, REFT and REFB, for the ADC core. Therefore, the
If the reference of the AD9228 is used to drive multiple converters external reference must be limited to a nominal 1.0 V.
to improve gain matching, the loading of the reference by the 5
other converters must be considered. Figure 66 depicts how the
internal reference voltage is affected by loading. 0
VIN + x –5
VREF ERROR (%)

VIN – x
REFT –10
0.1µF
ADC + –15
0.1µF 2.2µF
CORE
REFB
–20
0.1µF
VREF
–25
05727-083
1µF 0.1µF 0.5V
SELECT
LOGIC –30
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
SENSE
CURRENT LOAD (mA)
Figure 66. VREF Accuracy vs. Load

0.02
05727-010
–0.02
Figure 64. Internal Reference Configuration
–0.04
VREF ERROR (%)
VIN + x –0.06
VIN – x
REFT –0.08
0.1µF –0.10
ADC +
0.1µF 2.2µF
CORE –0.12
REFB
–0.14
0.1µF
VREF
05727-084
–0.16
1µF 0.1µF 0.5V –0.18

SELECT –40 –20 0 20 40 60 80
AVDD
LOGIC TEMPERATURE (°C)
SENSE Figure 67. Typical VREF Drift
05727-046
Figure 65. External Reference Operation
Data Sheet AD9228
SERIAL PORT INTERFACE (SPI)

The AD9228 serial port interface allows the user to configure the In addition to the operation modes, the SPI port configuration
converter for specific functions or operations through a influences how the AD9228 operates. For applications that do
structured register space provided in the ADC. This may not require a control port, the CSB line can be tied and held high.
provide the user with additional flexibility and customization, This places the remainder of the SPI pins into their secondary
depending on the application. Addresses are accessed via the modes, as defined in the SDIO/ODM Pin and SCLK/DTP Pin
serial port and can be written to or read from via the port. sections. CSB can also be tied low to enable 2-wire mode. When
Memory is organized into bytes that can be further divided into CSB is tied low, SCLK and SDIO are the only pins required for
fields, as documented in the Memory Map section. Detailed communication. Although the device is synchronized during
operational information can be found in the AN-877 power-up, the user must ensure that the serial port remains
Application Note, Interfacing to High Speed ADCs via SPI. synchronized with the CSB line when using this mode. When
operating in 2-wire mode, it is recommended to use a 1-, 2-,
There are three pins that define the SPI: SCLK, SDIO, and CSB or 3-byte transfer exclusively. Without an active CSB line,
(see Table 14). The SCLK pin is used to synchronize the read streaming mode can be entered but not exited.
and write data presented to the ADC. The SDIO pin is a dual-
purpose pin that allows data to be sent to and read from the In addition to word length, the instruction phase determines if
internal ADC memory map registers. The CSB pin is an active the serial frame is a read or write operation, allowing the serial
low control that enables or disables the read and write cycles. port to be used to both program the chip and read the contents
of the on-chip memory. If the instruction is a readback operation,
Table 14. Serial Port Pins performing a readback causes the SDIO pin to change from an
Pin Function input to an output at the appropriate point in the serial frame.
SCLK Serial Clock. The serial shift clock input. SCLK is used to
synchronize serial interface reads and writes. Data can be sent in MSB- or LSB-first mode. MSB-first mode
SDIO Serial Data Input/Output. A dual-purpose pin. The typical is the default at power-up and can be changed by adjusting the
role for this pin is as an input or output, depending on configuration register. For more information about this and
the instruction sent and the relative position in the other features, see the AN-877 Application Note, Interfacing to
timing frame. High Speed ADCs via SPI.
CSB Chip Select Bar (Active Low). This control gates the read
and write cycles. HARDWARE INTERFACE
The falling edge of the CSB in conjunction with the rising edge of The pins described in Table 14 compose the physical interface
the SCLK determines the start of the framing sequence. During an between the user’s programming device and the serial port of
instruction phase, a 16-bit instruction is transmitted followed by the AD9228. The SCLK and CSB pins function as inputs when
one or more data bytes, which is determined by Bit Field W0 and using the SPI. The SDIO pin is bidirectional, functioning as an
Bit Field W1. An example of the serial timing and its definitions input during write phases and as an output during readback.
can be found in Figure 69 and Table 15. During normal operation,
CSB is used to signal to the device that SPI commands are to be If multiple SDIO pins share a common connection, care must
received and processed. When CSB is brought low, the device be taken to ensure that proper VOH levels are met. Assuming the
processes SCLK and SDIO to obtain instructions. Normally, same load for each AD9228, Figure 68 shows the number of
CSB remains low until the communication cycle is complete. SDIO pins that can be connected together and the resulting VOH
However, if connected to a slow device, CSB can be brought level. This interface is flexible enough to be controlled by either
high between bytes, allowing older microcontrollers enough serial PROMS or PIC microcontrollers, providing the user with
time to transfer data into shift registers. CSB can be stalled an alternative method, other than a full SPI controller, to
when transferring one, two, or three bytes of data. When W0 program the ADC (see the AN-812 Application Note).
and W1 are set to 11, the device enters streaming mode and
continues to process data, either reading or writing, until
CSB is taken high to end the communication cycle. This allows
complete memory transfers without requiring additional instruc-
tions. Regardless of the mode, if CSB is taken high in the middle
of a byte transfer, the SPI state machine is reset and the device
waits for a new instruction.
AD9228 Data Sheet
1.800
1.795
If the user chooses not to use the SPI, these dual-function pins
1.790 serve their secondary functions when the CSB is strapped to
1.785 AVDD during device power-up. See the Theory of Operation
1.780
1.775 section for details on which pin-strappable functions are
1.770 supported on the SPI pins.
1.765
VOH (V)
1.760
1.755
For users who wish to operate the ADC without using the
1.750 SPI, remove any connections from the CSB, SCLK/DTP, and
1.745
SDIO/ODM pins. By disconnecting these pins from the control
1.740
1.735 bus, the ADC can function in its most basic operation. Each
1.730 of these pins has an internal termination that floats to its
1.725
1.720 respective level.
1.715
05727-102
0 10 20 30 40 50 60 70 80 90 100
NUMBER OF SDIO PINS CONNECTED TOGETHER
Figure 68. SDIO Pin Loading
tDS tHI tCLK tH

tS tDH tLO
CSB
SCLK DON’T CARE DON’T CARE
SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE
05727-012
Figure 69. Serial Timing Details
Table 15. Serial Timing Definitions

Parameter Timing (Minimum, ns) Description
tDS 5 Setup time between the data and the rising edge of SCLK
tDH 2 Hold time between the data and the rising edge of SCLK
tCLK 40 Period of the clock
tS 5 Setup time between CSB and SCLK
tH 2 Hold time between CSB and SCLK
tHI 16 Minimum period that SCLK should be in a logic high state
tLO 16 Minimum period that SCLK should be in a logic low state
tEN_SDIO 10 Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 69)
tDIS_SDIO 10 Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 69)
Data Sheet AD9228
MEMORY MAP
READING THE MEMORY MAP TABLE RESERVED LOCATIONS
Each row in the memory map register table (Table 16) has eight Undefined memory locations must not be written to except
address locations. The memory map is divided into three sections: when writing the default values suggested in this data sheet.
the chip configuration register map (Address 0x00 to Address Addresses that have values marked as 0 are considered reserved
0x02), the device index and transfer register map (Address 0x05 and have a 0 written into their registers during power-up.
and Address 0xFF), and the ADC functions register map
(Address 0x08 to Address 0x22). DEFAULT VALUES
When the AD9228 comes out of a reset, critical registers are
The leftmost column of the memory map indicates the register preloaded with default values. These values are indicated in
address number, and the default value is shown in the second Table 16, where an X refers to an undefined feature.
rightmost column. The (MSB) Bit 7 column is the start of the
default hexadecimal value given. For example, Address 0x09, LOGIC LEVELS
the clock register, has a default value of 0x01, meaning that Bit 7 An explanation of various registers follows: Bit is set is
= 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, synonymous with bit is set to Logic 1 or writing Logic 1 for the
and bit. Similarly, clear a bit is synonymous with bit is set to Logic 0
Bit 0 = 1, or 0000 0001 in binary. This setting is the default for or writing Logic 0 for the bit.
the duty cycle stabilizer in the on condition. By writing a 0 to Bit 6
of this address followed by a 0x01 in Register 0xFF (transfer bit),
the duty cycle stabilizer turns off. It is important to follow each
writing sequence with a transfer bit to update the SPI registers.
For more information on this and other functions, consult the
AN-877 Application Note, Interfacing to High Speed ADCs via
SPI.
AD9228 Data Sheet
Table 16. Memory Map Register

Default
Addr. (MSB) (LSB) Value Default Notes/
(Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Comments
Chip Configuration Registers
00 chip_port_config 0 LSB first Soft 1 1 Soft LSB first 0 0x18 The nibbles
1 = on reset reset 1 = on should be
0 = off 1 = on 1 = on 0 = off mirrored so that
(default) 0 = off 0 = off (default) LSB- or MSB-first
(default) (default) mode is set cor-
rectly regardless
of shift mode.
01 chip_id 8-bit Chip ID Bits [7:0] 0x02 Default is unique
(AD9228 = 0x02), (default) chip ID, different
for each device.
This is a read-
only register.
02 chip_grade X Child ID [6:4] X X X X Read Child ID used to
(identify device variants of Chip ID) only differentiate
000 = 65 MSPS graded devices.
001 = 40 MSPS
Device Index and Transfer Registers
05 device_index_A X X Clock Clock Data Data Data Data 0x0F Bits are set to
Channel Channel Channel Channel Channel Channel determine which
DCO FCO D C B A on-chip device
1 = on 1 = on 1 = on 1 = on 1 = on 1 = on receives the next
0 = off 0 = off (default) (default) (default) (default) write command.
(default) (default) 0 = off 0 = off 0 = off 0 = off
FF device_update X X X X X X X SW 0x00 Synchronously
transfer transfers data
1 = on from the master
0 = off shift register to
(default) the slave.
ADC Functions
08 modes X X X X X Internal power-down mode 0x00 Determines
000 = chip run (default) various generic
001 = full power-down modes of chip
010 = standby operation.
011 = reset
09 clock X X X X X X X Duty 0x01 Turns the
cycle internal duty
stabilizer cycle stabilizer
1 = on on and off.
(default)
0 = off
0D test_io User test mode Reset PN Reset Output test mode—see Table 9 in the 0x00 When this reg-
00 = off (default) long gen PN short Digital Outputs and Timing section ister is set, the
01 = on, single alternate 1 = on gen 0000 = off (default) test data is placed
10 = on, single once 0 = off 1 = on 0001 = midscale short on the output
11 = on, alternate once (default) 0 = off 0010 = +FS short pins in place of
(default) 0011 = −FS short normal data.
0100 = checkerboard output
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = one-/zero-word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
(format determined by output_mode)
Data Sheet AD9228
Default
Addr. (MSB) (LSB) Value Default Notes/
(Hex) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Comments
14 output_mode X 0 = LVDS X X X Output 00 = offset binary 0x00 Configures the
ANSI-644 invert (default) outputs and the
(default) 1 = on 01 = twos format of the
1 = LVDS 0 = off complement data.
low power (default)
(IEEE
1596.3
similar)
15 output_adjust X X Output driver X X X X 0x00 Determines
termination LVDS or other
00 = none (default) output properties.
01 = 200 Ω Primarily func-
10 = 100 Ω tions to set the
11 = 100 Ω LVDS span and
common-mode
levels in place of
an external
resistor.
16 output_phase X X X X 0011 = output clock phase adjust 0x03 On devices that
(0000 through 1010) utilize global
0000 = 0° relative to data edge clock divide,
0001 = 60° relative to data edge determines
0010 = 120° relative to data edge which phase of
0011 = 180° relative to data edge (default) the divider
0101 = 300° relative to data edge output is used to
0110 = 360° relative to data edge supply the
1000 = 480° relative to data edge output clock.
1001 = 540° relative to data edge Internal latching
1010 = 600° relative to data edge is unaffected.
1011 to 1111 = 660° relative to data edge
19 user_patt1_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined
pattern, 1 LSB.
1A user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined
pattern, 1 MSB.
1B user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined
pattern, 2 LSB.
1C user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined
pattern, 2 MSB.
21 serial_control LSB first X X X <10 000 = 12 bits (default, normal bit 0x00 Serial stream
1 = on MSPS, stream) control. Default
0 = off low 001 = 8 bits causes MSB first
(default) encode 010 = 10 bits and the native
rate 011 = 12 bits bit stream
mode 100 = 14 bits (global).
1 = on
0 = off
(default)
22 serial_ch_stat X X X X X X Channel Channel 0x00 Used to power
output power- down individual
reset down sections of a
1 = on 1 = on converter (local).
0 = off 0 = off
(default) (default)
AD9228 Data Sheet
Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations
When connecting power to the AD9228, it is recommended It is required that the exposed paddle on the underside of the
that two separate 1.8 V supplies be used: one for analog (AVDD) ADC be connected to analog ground (AGND) to achieve the
and one for digital (DRVDD). If only one supply is available, it best electrical and thermal performance of the AD9228. An
must be routed to the AVDD first and then tapped off and exposed continuous copper plane on the PCB mates to the
isolated with a ferrite bead or a filter choke preceded by AD9228 exposed paddle, Pin 0. The copper plane must have
decoupling capacitors for the DRVDD. The user can employ several vias to achieve the lowest possible resistive thermal path
several different decoupling capacitors to cover both high and for heat dissipation to flow through the bottom of the PCB.
low frequencies. These must be located close to the point of These vias must be solder-filled or plugged.
entry at the PCB board level and close to the components, with
minimal trace lengths. To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a
A single PCB ground plane is sufficient when using the silkscreen on the PCB into several uniform sections. This provides
AD9228. With proper decoupling and smart partitioning of the several tie points between the ADC and PCB during the reflow
analog, digital, and clock sections of the PCB, optimum process, whereas using one continuous plane with no partitions
performance can be easily achieved. only guarantees one tie point. See Figure 70 for a PCB layout
example. For detailed information on packaging and the PCB
layout of chip scale packages, see the AN-772 Application Note,
A Design and Manufacturing Guide for the Lead Frame Chip
Scale Package (LFCSP).
SILKSCREEN PARTITION
PIN 1 INDICATOR
05727-013
Figure 70. Typical PCB Layout
Data Sheet AD9228
EVALUATION BOARD
The AD9228 evaluation board provides all of the support cir- section of the board individually. Use P501 to connect a
cuitry required to operate the ADC in its various modes and different supply for each section. At least one 1.8 V supply is
configurations. The converter can be driven differentially using a needed for AVDD_DUT and DRVDD_DUT; however, it is
transformer (default) or an AD8332 driver. The ADC can also be recommended that separate supplies be used for analog and
driven in a single-ended fashion. Separate power pins are provided digital signals and that each supply have a current capability of 1
to isolate the DUT from the drive circuitry of the AD8332. Each A. To operate the evaluation board using the VGA option, a
input configuration can be selected by changing the connection separate 5.0 V analog supply (AVDD_5 V) is needed. To
of various jumpers (see Figure 73 to Figure 77). Figure 71 shows operate the evaluation board using the SPI and alternate clock
the typical bench characterization setup used to evaluate the ac options, a separate 3.3 V analog supply (AVDD_3.3 V) is
performance of the AD9228. It is critical that the signal sources needed in addition to the other supplies.
used for the analog input and clock have very low phase noise INPUT SIGNALS
(<1 ps rms jitter) to realize the optimum performance of the
converter. Proper filtering of the analog input signal to remove When connecting the clock and analog sources to the
harmonics and lower the integrated or broadband noise at the evaluation board, use clean signal generators with low phase
input is also necessary to achieve the specified noise performance. noise, such as Rohde & Schwarz SMHU or HP8644B signal
generators or the equivalent, as well as a 1 m, shielded, RG-58, 50
See Figure 73 to Figure 81 for the complete schematics and Ω coaxial cable. Enter the desired frequency and amplitude from
layout diagrams demonstrating the routing and grounding the ADC specifications tables. Typically, most Analog Devices
techniques that must be applied at the system level. evaluation boards can accept approximately 2.8 V p-p or
13 dBm sine wave input for the clock. When connecting the
POWER SUPPLIES analog input source, it is recommended to use a multipole,
This evaluation board has a wall-mountable switching power narrow-band, band-pass filter with 50 Ω terminations. Good
supply that provides a 6 V, 2 A maximum output. Connect the choices of such band-pass filters are available from TTE, Allen
supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to Avionics, and K&L Microwave, Inc. The filter must be
63 Hz. The other end of the supply is a 2.1 mm inner diameter connected directly to the evaluation board if possible.
jack that connects to the PCB at P503. When on the PCB, the
6 V supply is fused and conditioned before connecting to three OUTPUT SIGNALS
low dropout linear regulators that supply the proper bias to The default setup uses the Analog Devices HSC-ADC-FIFO5-
each of the various sections on the board. INTZ to interface with the Analog Devices standard dual-channel
FIFO data capture board (HCS-ADC-EVALCZ). Two of the
When operating the evaluation board in a nondefault eight channels can be evaluated at the same time. For more
condition, L504 to L507 can be removed to disconnect the information on the channel settings and optional settings of
switching power supply. This enables the user to bias each these boards, visit www.analog.com/FIFO.
WALL OUTLET
100V TO 240V AC
47Hz TO 63Hz
6V DC
2A MAX
5.0V 1.8V 1.8V 3.3V 3.3V
– + – + – + – + – +
SWITCHING
POWER
SUPPLY
GND
VCC
GND
GND
GND
GND
AVDD_5V
AVDD_3.3V
AVDD_DUT
DRVDD_DUT
PC
RUNNING
ADC
ROHDE & SCHWARZ, ANALYZER
SMHU, INTERPOSER HSC-ADC-EVALCZ
BAND-PASS XFMR FIFO DATA AND SPI
2V p-p SIGNAL BOARD USER
FILTER INPUT CAPTURE
SYNTHESIZER AD9228 BOARD SOFTWARE
EVALUATION BOARD CH A TO CH D
ROHDE & SCHWARZ, 12-BIT USB
SMHU, CLK SERIAL CONNECTION
LVDS
05727-014
2V p-p SIGNAL
SYNTHESIZER SPI SPI SPI SPI
Figure 71. Evaluation Board Connection
AD9228 Data Sheet
DEFAULT OPERATION AND JUMPER SELECTION A differential LVPECL clock can also be used to clock the
SETTINGS ADC input using the AD9515 (U202). Populate R225 and
R227 with 0 Ω resistors and remove R217 and R218 to
The following is a list of the default and optional settings or disconnect the default clock path inputs. In addition, populate
modes allowed on the AD9228 Rev. A evaluation board. C207 and C208 with a 0.1 μF capacitor and remove C210 and
C211 to disconnect the default clock path outputs. The
 POWER: Connect the switching power supply that is
AD9515 has many pin-strappable options that are set to a
provided with the evaluation kit between a rated 100 V
default mode of operation. Consult the AD9515 data sheet
ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P503.
for more information about these and other options.
 AIN: The evaluation board is set up for a transformer-
coupled analog input with an optimum 50 Ω impedance
In addition, an on-board oscillator is available on the OSC201
match of 200 MHz of bandwidth (see Figure 72). For more
and can act as the primary clock source. The setup is quick
bandwidth response, the differential capacitor across the
and involves installing R212 with a 0 Ω resistor and setting
analog inputs can be changed or removed. The common
the enable jumper (J205) to the on position. If the user wishes
mode of the analog inputs is developed from the center tap
to employ a different oscillator, two oscillator footprint
of the transformer or AVDD_DUT/2.
options are available (OSC201) to check the ADC
0 performance.
–2
 PDWN: To enable the power-down feature, short J201 to
–3dB CUTOFF = 200MHz AVDD on the PDWN pin.
–4
 SCLK/DTP: To enable the digital test pattern on the digital
AMPLITUDE (dBFS)
–6 outputs of the ADC, use J204. If J204 is tied to AVDD during

device power-up, Test Pattern 1000 0000 0000 is enabled. See
–8
the SCLK/DTP Pin section for details.
–10  SDIO/ODM: To enable the low power, reduced signal option
(similar to the IEEE 1595.3 reduced range link LVDS output
–12
standard), use J203. If J203 is tied to AVDD during device
–14 power-up, it enables the LVDS outputs in a low power,
05727-088
reduced signal option from the default ANSI-644 standard.

–16
0 50 100 150 200 250 300 350 400 450 500 This option changes the signal swing from 350 mV p-p to
FREQUENCY (MHz)
200 mV p-p, reducing the power of the DRVDD supply. See
Figure 72. Evaluation Board Full-Power Bandwidth the SDIO/ODM Pin section for more details.
 CSB: To enable processing of the SPI information on the
 VREF: VREF is set to 1.0 V by tying the SENSE pin to
SDIO and SCLK pins, tie J202 low in the always enable
ground, R237. This causes the ADC to operate in 2.0 V p-p
mode. To ignore the SDIO and SCLK information, tie J202
full-scale range. A separate external reference option using
to AVDD.
the ADR510 is also included on the evaluation board.
 Non-SPI Mode: For users who wish to operate the DUT
Populate R231 and R235 and remove C214. Proper use of the
without using SPI, remove Jumpers J302, J303, and J304.
VREF options is noted in the Voltage Reference section.
This disconnects the CSB, SCLK/DTP, and SDIO/ODM pins
 RBIAS: RBIAS has a default setting of 10 kΩ (R201) to
from the control bus, allowing the DUT to operate in its
ground and is used to set the ADC core bias current.
simplest mode. Each of these pins has internal termination
 CLOCK: The default clock input circuitry is derived from
and floats to its respective level.
a simple transformer-coupled circuit using a high
 D + x, D − x: If an alternative data capture method to the
bandwidth 1:1 impedance ratio transformer (T201) that
setup shown in Figure 73 is used, optional receiver
adds a very
terminations, R206 to R211, can be installed next to the
low amount of jitter to the clock path. The clock input is
high speed backplane connector.
50 Ω terminated and ac-coupled to handle single-ended
sine wave types of inputs. The transformer converts the
single-ended input to a differential signal that is clipped
before entering the ADC clock inputs.
Data Sheet AD9228
ALTERNATIVE ANALOG INPUT DRIVE  Remove R102, R115, R128, R141, R161, R162, R163, R164,
CONFIGURATION T101, T102, T103, and T104 in the default analog input
path.
The following is a brief description of the alternative analog input
 Populate R101, R114, R127, and R140 with 0 Ω resistors in
drive configuration using the AD8332 dual VGA. If this drive
the analog input path.
option is in use, some components may need to be populated, in
 Populate R105, R113, R118, R124, R131, R137, R151, and
which case all the necessary components are listed in Table 17. For
R160 with 0 Ω resistors in the analog input path to connect
more details on the AD8332 dual VGA, including how it works
the AD8332.
and its optional pin settings, consult the AD8332 data sheet.
 Populate R152, R153, R154, R155, R156, R157, R158, R159,
To configure the analog input to drive the VGA instead of the C103, C105, C110, C112, C117, C119, C124, and C126
default transformer option, the following components need to with 10 kΩ resistors to provide an input common-mode
be removed and/or changed. level to the ADC analog inputs.
 Remove R305, R306, R313, R314, R405, R406, R412, and
R424 to configure the AD8332.
In this configuration, L301 to L308 and L401 to L408 are

populated with 0 Ω resistors to allow signal connection and use
of a filter if additional requirements are necessary.
AD9228 Data Sheet
AVDD_DUT
R105
DNP R152
CH_A DNP
C101 FB102 R108
P102 R104 0.1µF T101 10Ω 33Ω
VGA INPUT CONNECTION DNP 0Ω 1 6
INH1 AIN VIN_A
R106
CHANNEL A DNP
P101 R101 2 5 R161 R109
DNP CM1 CM1 499Ω C103 C104
1kΩ
AIN 3 4 DNP 2.2pF
FB101 R113 R107
R103 10Ω C102 DNP DNP
R102 0Ω 0.1µF CH_A
64.9Ω VIN_A
CM1 FB103 R110 C105 R156
10Ω 33Ω DNP DNP
E101
AVDD_DUT C106
R111 DNP
1kΩ R112 C107 AVDD_DUT
1kΩ 0.1µF
AVDD_DUT
R118
VGA INPUT CONNECTION DNP
INH2 R153
CH_B DNP
CHANNEL B
R114 FB105 R121
P103 T102 10Ω 33Ω
DNP
1 6
AIN VIN_B
R115 FB104 R119
64.9Ω 10Ω C108 DNP
0.1µF R162
P104 CM2 2 5 R123
CM2 499Ω C110 C111
1kΩ
DNP 3 4 DNP 2.2pF
AIN R116 R124 R120
0Ω C109 DNP DNP
R117 0.1µF CH_B VIN_B
0Ω CM2 FB106 R122 C112 R157
10Ω 33Ω DNP DNP
E102
AVDD_DUT C113
R125 DNP
1kΩ 0.1µF AVDD_DUT
R131
DNP R154
CH_C DNP
C115 FB108 R134
P106 R130 0.1µF T103 10Ω 33Ω
VGA INPUT CONNECTION DNP 0Ω 1 6
INH3 AIN VIN_C
R132
CHANNEL C DNP
P105 R127 2 5 R163 R135
DNP CM3 CM3 499Ω C117 C118
1kΩ
AIN 3 4 DNP 2.2pF
FB107 R137 R133
R128 0Ω 0.1µF CH_C
64.9Ω VIN_C
CM3 FB109 R136 C119 R158
10Ω 33Ω DNP DNP
E103
AVDD_DUT C120
R138 DNP
1kΩ 0.1µF
AVDD_DUT
VGA INPUT CONNECTION R151

DNP R155
INH4 CH_D DNP
CHANNEL D
R140 FB111 R146
P107 T104 10Ω 33Ω
DNP
1 6
AIN VIN_D
R141 FB110 C122 R144
64.9Ω 10Ω 0.1µF DNP
2 5 R164 R148
P108 CM4 CM4 499Ω C124 C125
1kΩ
DNP 3 4 DNP 2.2pF
AIN R143 R160 R145
0.1µF CH_D VIN_D
0Ω FB112 R147
CM4 C126 R159
10Ω 33Ω DNP DNP
E104
AVDD_DUT C127
R149 C128 DNP
1kΩ R150 AVDD_DUT
05727-015
1kΩ 0.1µF
DNP: DO NOT POPULATE
Figure 73. Evaluation Board Schematic, DUT Analog Inputs
REFERENCE CIRCUIT
OPTIONAL
EXT REF AVDD_DUT
U203 VREF SELECT
C204 REFERENCE ADR510 R229 VREF_DUT VSENSE_DUT DIGITAL OUTPUTS
R231 R234
0.1µF DECOUPLING 1V 4.99kΩ DNP DNP
Data Sheet
DNP VREF = 0.5V P202

TRIM/NC V+ GNDCD10
V–
DNP R232 R235 60
C202 C203 DNP DNP DNP VREF = EXTERNAL DCO C10 D10 DCO R206
2.2µF 0.1µF R201 C212 R230 40 GNDCD9 50 DNP
10kΩ R228 0.1µF 10kΩ C214 R236 59
DNP VREF = 0.5V(1+R232/R233) R207
AVDD_DUT
470kΩ 1µF DNP FCO C9 D9 FCO DNP
C201 C213 39 GNDCD8 49
CW
0.1µF 0.1µF R233 R237 58
DNP 0Ω VREF = 1V CHA D8 CHA R208
C8
38 GNDCD7 48 DNP
VIN_C
AVDD_DUT
AVDD_DUT
VREF_DUT
VSENSE_DUT
AVDD_DUT
VIN_B
57
VIN_C
VIN_B
CHB C7 D7 CHB R209
AVDD_DUT REMOVE C214 WHEN USING EXTERNAL VREF 37 GNDCD6 47 DNP
48
47
46
45
44
43
42
41
40
39
38
37
U201
56
CHC C6 D6 CHC R210
AVDD_DUT 1 AVDD AVDD 36 AVDD_DUT 36 GNDCD5 46 DNP
REFT
VREF
REFB
AVDD
AVDD
AVDD
55
RBIAS
2 35 R202
SENSE
VIN – C
VIN – B
VIN + C
VIN + B
AVDD_DUT AVDD AVDD AVDD_DUT
R267
100kΩ CHD C5 D5 CHD R211
VIN_D 3 VIN – D VIN – A 34 VIN_A 35 GNDCD4 45
J201 DNP
VIN_D 4 VIN + D VIN + A 33 VIN_A 1 3 54
PWDN ENABLE
2
C4 D4
100kΩ - DNP
5 32
R266
100kΩ - DNP
AVDD_DUT AVDD AVDD AVDD_DUT 34 GNDCD3 44
1 J202 R244 R245
AVDD_DUT 6 AVDD AD9228LFCSP PDWN 31 3 ALWAYS ENABLE SPI
DNP 0Ω 53
2
7 30 CSB_DUT AVDD_3.3V C3
CLK CLK– CSB 33 GNDCD2
D3 43
8 29 1 J203 S0
CLK CLK+ SDIO/ODM 3
ODM ENABLE R246 R247 R256 R257 52
2
AVDD_DUT 9 AVDD SCLK/DTP 28 SDIO_ODM DNP 0Ω DNP 0Ω 32 C2GNDCD1 D2 42
10 27 1 J204 3 AVDD_3.3V AVDD_3.3V
AVDD_DUT AVDD AVDD AVDD_DUT DTP ENABLE S1 S6 51
2
GND 11 DRGND DRGND 26 GND SCLK_DTP R248 R249 R258 R259 C1 D1 41
12 25 DNP 0Ω DNP 0Ω 31 GNDAB10
DRVDD_DUT DRVDD DRVDD DRVDD_DUT
AVDD_3.3V AVDD_3.3V 30
D–D
D+D
D–C
D+C
D–B
D+B
D–A
D+A
FCO–
FCO+
DCO–
DCO+
S2 S7 C10
R203
R204
R205
10kΩ
B10 20
100kΩ
100kΩ
R250 R251 R260 R261 10 GNDAB9
13
14
15
16
17
18
19
20
21
22
23
24
DNP 0Ω DNP 0Ω 29
AVDD_3.3V AVDD_3.3V A9 B9
S3 S8 9 GNDAB8 19
FCO
FCO
CHD
CHD
CHC
CHC
CHB
CHB
CHA
CHA
R252 R253 R262 R263
DCO
DCO
DNP 0Ω DNP 0Ω 28
A8 B8
AVDD_3.3V AVDD_3.3V 8 GNDAB7 18
AVDD_3.3V S4 S9
R254 R255 R264 R265 27
A7 B7
DNP 0Ω DNP 0Ω 7 GNDAB6 17
C224 AVDD_3.3V AVDD_3.3V
0.1µF S5 S10 26
R214 A6 B6
6 GNDAB5 16
OPTIONAL CLOCK 10kΩ
25
3
OSCILLATOR A5 B5
ENABLE OPTIONAL CLOCK DRIVE CIRCUIT SCLK_CHB SCLK_CHA
AVDD_3.3V AVDD_3.3V 5 GNDAB4 15
2 R222
J205 4.12kΩ 24
OSC201 C207 SDI_CHB A4 B4 SDI_CHA
DISABLE AVDD_3.3V 4 GNDAB3
14 VCC OE 1 0.1µF 14
1
12 VCC' OE' 3 R219 R220 R221 DNP 23
R215 DNP DNP 10kΩ B3
10 5 10kΩ CLK CSB3__CHB A3 CSB1_CHA
OUT' GND' 3 GNDAB2 13
OPT_CLK
33
ENCODE 8 OUT GND 7 U202 R242 C208
0.1µF LVPECL OUTPUT 22
INPUT R225 GND_PAD 23 100Ω CSB4_CHB A2 B2 CSB2_CHA
VS 1
VFAC3H-L R226 2 CLK OUT0 DNP
0Ω 2 GNDAB1 12
GND 31
3 22
RSET 32
R212 DNP 49.9Ω CLKB OUT0B CLK
DNP AD9515 21
0Ω
DNP OPT_CLK SIGNAL=AVDD_3.3V;4,17,20,21,24,26,29,30 R240 R241 SDO_CHB A1 B1 SDO_CHA
5 243Ω 243Ω 1 11
Figure 74. Evaluation Board Schematic, DUT, VREF, Clock Inputs, and Digital Output Interface
SYNCB OUT1 19
R227 SIGNAL=DNC;27,28 18 NC = NO CONNECT HEADER 6469169-1
0Ω OUT1B 1
P201 OPT_CLK R238 R239 E202
DNP
VREF
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
DNP 10kΩ C209 R205–R211

ENC
6
7
8
9
R243 0.1µF OPTIONAL OUTPUT
10
11
12
13
14
15
16
25
C205 100Ω DNP LVDS OUTPUT AVDD_3.3V

R213 0.1µF 1 TERMINATIONS
49.9kΩ 1 E203
E201
CLOCK CIRCUIT R217 R223 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 C215
OPT_CLK 0Ω T201 0Ω CLK 0.1µF
P203 CR201 C210 C217 C218 C219 C220 C221 C222 C223
3
3 4 HSMS2812 DNP
ENC 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
DNP CLIP SINE OUT (DEFAULT)
R216 C216 2 5
2
1
0Ω 0.1µF
R218 1 6 R224
C206 CLK
0Ω 0Ω C211
0.1µF
0.1µF
05727-016
AD9228
AD9228 Data Sheet
POPULATE L301-L308 WITH 0Ω
CH_D
CH_D
CH_C
CH_C
RESISTORS OR DESIGN YOUR
OWN FILTER.
R301 R302
DNP DNP EXTERNAL VARIABLE GAIN DRIVE
VG
C301 C302
1
VARIABLE GAIN CIRCUIT
JP301
L301 DNP L302 L303 DNP L304
0Ω 0Ω 0Ω 0Ω (0-1.0V DC) VG
GND
2
CW
C303 C304 AVDD_5V
L305 DNP L306 L307 DNP L308 R320 R319
0Ω R303 0Ω 0Ω 0Ω 39kΩ 10kΩ
R304
(0-1V = DISABLE POWER)

DNP DNP
POWER DOWN ENABLE
OPTIONAL VGA DRIVE CIRCUIT FOR CHANNEL C AND CHANNEL D
C305 C306 C307 C308
HILO PIN = LO = ±50mV

0.1µF 0.1µF 0.1µF 0.1µF
HILO PIN = H = ±75mV

R306
AVDD_5V
R305 374Ω C309 R311
374Ω 1000pF 10kΩ
C310 DNP
R307 R308 R309 R310
RCLAMP PIN
AVDD_5V
0.1µF
187Ω 187Ω 187Ω 187Ω
AVDD_5V
24
23
22
21
20
19
18
17
R312 U301
10kΩ
VOL1
VOL2
VOH1
VPSV
VOH2
COMM
COMM
NC
R313 25
ENBV RCLMP R314
10kΩ 26 16 10kΩ
ENBL GAIN VG
DNP 27 15 DNP
HILO MODE
14
NEGATIVE GAIN SLOPE = 2.25V-5.0V

28
VCM1 VCM2
HI GAIN RANGE = 2.25V-5.0V
29 AD8332 13
VIN1 VIN2
30 12
POSITIVE GAIN SLOPE = 0-1.0V

LO GAIN RANGE = 0-1.0V
VIP1 VIP2
C311 31 11 C313
COM1 COM2
0.1µF 32 10 0.1µF
LOP2
LMD1
LMD2
LOP1
LON1
LON2
VPS1
VPS2
INH1
INH2
C312 C314
1
2
3
4
5
6
7
8
0.1µF 0.1µF
HILO PIN
AVDD_5V
AVDD_5V
MODE PIN
R316 C320
274Ω R317
0.1µF C321 274Ω
R315 C315 C316 C325 C326 R318
10kΩ 10µF 0.1µF 0.1µF 0.1µF 10µF 10kΩ
C317
0.018µF C322
0.018µF
C318 C323
22pF 22pF
L309 L310
120nH 120nH
C319 C324
05727-017
0.1µF 0.1µF
DNP: DO NOT POPULATE INH4 INH3
Figure 75. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface Circuit
Data Sheet
CH_B
CH_B
CH_A
CH_A
R401 R402
DNP DNP
C401 C402
L401 DNP L402 L403 DNP L404
0Ω 0Ω 0Ω 0Ω
C403 C404 SPI CIRCUITRY FROM FIFO

L405 DNP L406 L407 DNP L408
0Ω R403 0Ω 0Ω 0Ω
R404
POWER DOWN ENABLE

(0–1V = DISABLE POWER)
DNP DNP +5V = PROGRAMMING = AVDD_5V
+3.3V = NORMAL OPERATION = AVDD_3.3V
POPULATE L401-L408 WITH 0Ω

RESISTORS OR DESIGN YOUR
OWN FILTER.
REMOVE WHEN USING
C405 C406 C407 C408 OR PROGRAMMING PIC (U402)
CSB1_CHA
SCLK_CHA
SDI_CHA
SDO_CHA
0.1µF 0.1µF 0.1µF 0.1µF AVDD_3.3V AVDD_5V

R406
R405 374Ω C411 R413 J402
374Ω 1000pF 10kΩ AVDD_3.3V
C412 C427 0Ω
0Ω
0Ω
0Ω
R407 R408 R409 DNP

R426
R428
R420
R427
R410 0.1µF 0.1µF
AVDD_5V
187Ω 187Ω 187Ω 187Ω U402
1 VDD 8 R421 R433
VSS 1kΩ
24
23
22
21
20
19
18
17
0-DNP
AVDD_5V
R411 U401 2 7
GP5 GP0
AVDD_5V
10kΩ 3 6
RCLAMP PIN
HILO PIN = LO = ±50mV
HILO PIN = H = ±75mV
GP4 GP1
NC
S401
R418
R422
4.75kΩ
R412 25 1 3 MCLR/
VOL1
VOL2
VPSV
R424
VOH1
VOH2
ENBV RCLMP 4 0-DNP
COMM
COMM
10kΩ 26 16 10kΩ 2 4 GP3 GP2 5
ENBL GAIN VG SDIO_ODM
DNP 27 15 DNP R423
HILO MODE RESET/REPROGRAM PIC12F629 0-DNP
28 14 AVDD_DUT
VCM1 VCM2 R419
29 AD8332 13 261Ω
VIN1 VIN2
30 12
VIP1 VIP2 CR401 R432
C409 31 11 C423 NC7WZ07 1kΩ R431
COM1 COM2 1kΩ
OPTIONAL
0.1µF 32 10 0.1µF 1 A1 Y1 6
LOP1 LOP2
9 2 GND VCC 5
LON1
VPS1
INH1
LMD1
LMD2
INH2
VPS2
LON2
AVDD_DUT
R425 3 A2 Y2 4
C410 C424 10kΩ
1
2
3
4
5
6
7
8
0.1µF 0.1µF
E401 C429
U403 0.1µF
R415 C416
HILO PIN
HI GAIN RANGE = 2.25V-5.0V
LO GAIN RANGE = 0-1.0V
OPTIONAL VGA DRIVE CIRCUIT FOR CHANNEL A AND CHANNEL B

274Ω 0.1µF
GP1
C417
R416
R414 C413 C414 C425 C426 R417 NC7WZ16
0.1µF
AVDD_5V
AVDD_5V
10kΩ 10µF 0.1µF 0.1µF 10µF 10kΩ 1 A1 Y1 6
MCLR/GP3 7
GP0 5
3
PICVCC 1
C415 SCLK_DTP
0.018µF
MODE PIN
POSITIVE GAIN SLOPE = 0-1.0V
NEGATIVE GAIN SLOPE = 2.25V-5.0V
2 GND VCC 5 AVDD_DUT
J401
9 10
8
6
4
2
C420
3 A2 Y2 4
0.018µF 274Ω
CSB_DUT
R430 R429 C428
C418 C421 10kΩ 10kΩ U404
GP0
GP1
22pF 0.1µF
22pF
PICVCC
MCLR/GP3
PIC PROGRAMMING HEADER
L409 L410
120nH 120nH
C419 C422
0.1µF 0.1µF
Figure 76. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface Circuit (Continued)
05727-018 INH2 INH1 DNP: DO NOT POPULATE
AD9228
D502
3A
POWER SUPPLY INPUT SHOT_RECT
6V, 2V MAXIMUM F501 DO-214AB
AD9228
FER501
PWR_IN
P503 1 2
1 SMDC110F
+ 4 3 CR501
C501 D501
S2A_RECT CHOKE_COIL
2
10µF 2A
3 DO-214AA R501
261Ω
OPTIONAL POWER INPUT DECOUPLING CAPACITORS

L503
P501 10µH
5V_AVDD
P1 1 AVDD_5V +5.0V AVDD_5V
P2 2 C502 C518 C519 C520 C521 C522 C523
DUT_AVDD 10µF C503
P3 3 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
0.1µF
P4 4
3.3V_AVDD L502
P5 5 10µH
P6 6 AVDD_DUT +1.8V AVDD_DUT
DUT_DRVDD
P7 7 C504 C526 C527 C528 C529 C530 C531
10µF C505 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
P8 8 0.1µF
L508
10µH
AVDD_3.3V +3.3V AVDD_3.3V
C508 C524 C525
10µF C509
0.1µF 0.1µF 0.1µF
L501 H1 H3
10µH
DRVDD_DUT +1.8V DRVDD_DUT
C506 C516 C517 H2 H4
10µF C507 0.1µF 0.1µF
0.1µF
MOUNTING HOLES
CONNECTED TO GROUND
Figure 77. Evaluation Board Schematic, Power Supply Inputs

U501 U502
L505 L506
ADP3339AKC-1.8 10µH ADP3339AKC-3.3 10µH
3 2 3 2
PWR_IN INPUT OUTPUT1 DUT_AVDD PWR_IN INPUT OUTPUT1 3.3V_AVDD
OUTPUT4 4 OUTPUT4 4
C514 C515 C532 C533
GND
GND
1µF 1µF 1µF 1µF
1
1
U503 U504
L504 L507
ADP3339AKC-1.8 10µH ADP3339AKC-5 10µH
3 2 3 2
PWR_IN INPUT OUTPUT1 DUT_DRVDD PWR_IN INPUT OUTPUT1 5V_AVDD
4
OUTPUT4 C534 OUTPUT4 4
C512 C513 C535
GND
GND
1µF
1µF 1µF 1µF
1
1

05727-019
Data Sheet
Data Sheet AD9228
05727-020
Figure 78. Evaluation Board Layout, Primary Side
AD9228 Data Sheet
05727-021
Figure 79. Evaluation Board Layout, Ground Plane
Data Sheet AD9228
05727-022
Figure 80. Evaluation Board Layout, Power Plane
AD9228 Data Sheet
05727-023
Figure 81. Evaluation Board Layout, Secondary Side (Mirrored Image)
Data Sheet AD9228
Table 17. Evaluation Board Bill of Materials (BOM)1

Manufacturer’s
Item Qty. Reference Designator Device Package Value Manufacturer Part Number
1 1 AD9228LFCSP_REVA PCB PCB PCB
2 75 C101, C102, C107, Capacitor 402 0.1 μF, ceramic, Murata GRM155R71C104KA88D
C108, C109, C114, X5R, 10 V, 10% tol
C115, C116, C121,
C122, C123, C128,
C201, C203, C204,
C205, C206, C210,
C211, C212, C213,
C216, C217, C218,
C219, C220, C221,
C222, C223, C224,
C310, C311, C312,
C313, C314, C316,
C319, C320, C321,
C324, C325, C409,
C410, C412, C414,
C416, C417, C419,
C422, C423, C424,
C425, C427, C428,
C429, C503, C505,
C507, C509, C516,
C517, C518, C519,
C520, C521, C522,
C523, C524, C525,
C526, C527, C528,
C529, C530, C531
3 4 C104, C111, C118, Capacitor 402 2.2 pF, ceramic, Murata GRM1555C1H2R2GZ01B
C125 COG, 0.25 pF tol,
50 V
4 4 C315, C326, C413, Capacitor 805 10 μF, 6.3 V ±10% Murata GRM219R60J106KE19D
C426 ceramic, X5R
5 1 C202 Capacitor 603 2.2 μF, ceramic, Murata GRM188C70J225KE20D
X5R, 6.3 V, 10% tol
6 2 C309, C411 Capacitor 402 1000 pF, ceramic, Murata GRM155R71H102KA01D
X7R, 25 V, 10% tol
7 4 C317, C322, C415, Capacitor 402 0.018 μF, ceramic, AVX 0402YC183KAT2A
C420 X7R, 16 V, 10% tol
8 4 C318, C323, C418, Capacitor 402 22 pF, ceramic, Murata GRM1555C1H220JZ01D
C421 NPO, 5% tol, 50 V
9 1 C501 Capacitor 1206 10 μF, tantalum, Rohm TCA1C106M8R
16 V, 20% tol
10 9 C214, C512, C513, Capacitor 603 1 μF, ceramic, X5R, Murata GRM188R61C105KA93D
C514, C515, C532, 6.3 V, 10% tol
C533, C534, C535
11 8 C305, C306, C307, Capacitor 805 0.1 μF, ceramic, Murata GRM21BR71H104KA01L
C308, C405, C406, X7R, 50 V, 10% tol
C407, C408
12 4 C502, C504, C506, Capacitor 603 10 μF, ceramic, Murata GRM188R60J106M
C508 X5R, 6.3 V, 20% tol
13 1 CR201 Diode SOT-23 30 V, 20 mA, dual Agilent HSMS2812-TRIG
Schottky Technologies
14 2 CR401, CR501 LED 603 Green, 4 V, 5 m Panasonic LNJ314G8TRA
candela
15 1 D502 Diode DO-214AB 3 A, 30 V, SMC Micro SK33-TP
Commercial Co.
16 1 D501 Diode DO-214AA 2 A, 50 V, SMC Micro S2A-TP
Commercial Co.
AD9228 Data Sheet
Manufacturer’s
17 1 F501 Fuse 1210 6.0 V, 2.2 A trip- Tyco/Raychem NANOSMDC110F-2
current resettable
fuse
18 1 FER501 Choke coil 2020 10 μH, 5 A, 50 V, Murata DLW5BSN191SQ2L
190 Ω at 100 MHz
19 12 FB101, FB102, FB103, Ferrite bead 603 10 Ω, test freq Murata BLM18BA100SN1B
FB104, FB105, FB106, 100 MHz, 25% tol,
FB107, FB108, FB109, 500 mA
FB110, FB111, FB112
20 1 JP301 Connector 2-pin 100 mil header Samtec TSW-102-07-G-S
jumper, 2-pin
21 2 J205, J402 Connector 3-pin 100 mil header Samtec TSW-103-07-G-S
jumper, 3-pin
22 1 J201 to J204 Connector 12-pin 100 mil header Samtec TSW-104-08-G-T
male, 4 × 3 triple
row straight
23 1 J401 Connector 10-pin 100 mil header, Samtec TSW-105-08-G-D
male, 2 × 5 double
row straight
24 8 L501, L502, L503, L504, Ferrite bead 1210 10 μH, bead core Murata BLM31PG500SN1L
L505, L506, L507, L508 3.2 × 2.5 × 1.6
SMD, 2 A
25 4 L309, L310, L409, L410 Inductor 402 120 nH, test freq Murata LQG15HNR12J02B
100 MHz, 5% tol,
150 mA
26 16 L301, L302, L303, L304, Resistor 805 0 Ω, 1/8 W, 5% tol NIC NRC10ZOTRF
L305, L306, L307, L308, Components
L401, L402, L403, L404,
L405, L406, L407, L408
27 1 OSC201 Oscillator SMT Clock oscillator, Valpey Fisher VFAC3H-L-65MHz
65.00 MHz, 3.3 V
28 5 P101, P103, P105, Connector SMA Side-mount SMA Johnson 142-0710-851
P107, P201 for 0.063" board Components
thickness
29 1 P202 Connector Header 1469169-1, right Tyco 6469169-1
angle 2-pair,
25 mm, header
assembly
30 1 P503 Connector 0.1", SC1153, power Switchcraft RAPC722X
PCMT supply connector
31 15 R201, R205, R214, Resistor 402 10 kΩ, 1/16 W, NIC NRC04J103TRF
R215, R221, R239, 5% tol Components
R312, R315, R318,
R411, R414, R417,
R425, R429, R430
32 14 R103, R117, R129, Resistor 402 0 Ω, 1/16 W, NIC NRC04Z0TRF
R218, R223, R224,
R237, R420, R426,
R427, R428
33 4 R102, R115, R128, Resistor 402 64.9 Ω, 1/16 W, NIC NRC04F64R9TRF
R141 1% tol Components
34 4 R104, R116, R130, Resistor 603 0 Ω, 1/10 W, NIC NRC06Z0TRF
Data Sheet AD9228
Manufacturer’s
35 15 R109, R111, R112, Resistor 402 1 kΩ, 1/16 W, NIC NRC04F1001TRF
R135, R138, R139,
R148, R149, R150,
R431, R432, R433
36 8 R108, R110, R121, Resistor 402 33 Ω, 1/16 W, 5% NIC NRC04J330TRF
R122, R134, R136, tol Components
R146, R147
37 4 R161, R162, R163, Resistor 402 499 Ω, 1/16 W, NIC NRC04F4990TRF
38 3 R202, R203, R204 Resistor 402 100 kΩ, 1/16 W, NIC NRC04F1003TRF
1% tol Components
39 1 R222 Resistor 402 4.12 kΩ, 1/16 W, NIC NRC04F4121TRF
1% tol Components
40 1 R213 Resistor 402 49.9 Ω, 1/16 W, Susumu RR0510R-49R9-D
0.5% tol
41 1 R229 Resistor 402 4.99 kΩ, 1/16 W, NIC NRC04F4991TRF
5% tol Components
42 2 R230, R319 Potentiometer 3-lead 10 kΩ, cermet BC CT94EW103
trimmer Components
potentiometer,
18-turn top adjust,
10%, 1/2 W
43 1 R228 Resistor 402 470 kΩ, 1/16 W, NIC NRC04J474TRF
5% tol Components
44 1 R320 Resistor 402 39 kΩ, 1/16 W, NIC NRC04J393TRF
5% tol Components
R409, R410
48 11 R245, R247, R249, Resistor 201 0 Ω, 1/20 W, 5% tol Panasonic ERJ-1GE0R00C
R251, R253, R255,
R257, R259, R261,
R263, R265
49 1 R418 Resistor 402 4.75 kΩ, 1/16 W, NIC NRC04J472TRF
1% tol Components
50 1 R419 Resistor 402 261 Ω, 1/16 W, NIC NRC04F2610TRF
1% tol Components
51 1 R501 Resistor 603 261 Ω, 1/16 W, NIC NRC06F2610TRF
1% tol Components
52 2 R240, R241 Resistor 402 243 Ω, 1/16 W, NIC NRC04F2430TRF
1% tol Components
53 2 R242, R243 Resistor 402 100 Ω, 1/16 W, NIC NRC04F1000TRF
1% tol Components
54 1 S401 Switch SMD Light touch, Panasonic EVQ-PLDA15
100GE, 5 mm
55 5 T101, T102, T103, Transformer CD542 ADT1-1WT, 1:1 Mini-Circuits ADT1-1WT+
T104, T201 impedance ratio
transformer
56 2 U501, U503 IC SOT-223 ADP33339AKC-1.8, Analog Devices ADP33339AKCZ-1.8
1.5 A, 1.8 V LDO
regulator
AD9228 Data Sheet
Manufacturer’s
57 2 U301, U401 IC LFCSP, AD8332ACP, Analog Devices AD8332ACPZ
CP-32 ultralow noise
precision dual
VGA
58 1 U504 IC SOT-223 ADP3339AKC-5 Analog Devices ADP3339AKCZ-5
59 1 U502 IC SOT-223 ADP3339AKC-3.3 Analog Devices ADP3339AKCZ-3.3
60 1 U201 IC LFCSP, AD9228BCPZ-65, Analog Devices AD9228BCPZ-65
CP-48-1 quad, 12-bit, 65
MSPS serial LVDS
1.8 V ADC
61 1 U203 IC SOT-23 ADR510ARTZ, 1.0 Analog Devices ADR510ARTZ
V, precision low
noise shunt
voltage reference
62 1 U202 IC LFCSP AD9515BCPZ Analog Devices AD9515BCPZ
CP-32-2
63 1 U403 IC SC70, NC7WZ07 Fairchild NC7WZ07P6X_NL
MAA06A
64 1 U404 IC SC70, NC7WZ16 Fairchild NC7WZ16P6X_NL
MAA06A
65 1 U402 IC 8-SOIC Flash prog Microchip PIC12F629-I/SN
mem 1k × 14,
RAM size 64 × 8,
20 MHz speed,
PIC12F controller
series
1
This bill of materials is RoHS compliant.
Data Sheet AD9228
OUTLINE DIMENSIONS
DETAIL A
7.10 (JEDEC 95)
7.00 SQ 0.30
6.90 0.23
PIN 1
INDICATOR 0.18
AREA P IN 1
37 48 IN D IC ATO R AR E A OP T I O N S
(SEE DETAIL A)
36 1
0.50
BSC 5.65
EXPOSED 5.50 SQ
PAD
5.35
24 13
TOP VIEW
0.45 BOTTOM VIEW 0.20 MIN
0.40
0.35 5.50 REF
0.80
0.75 END VIEW FOR PROPER CONNECTION OF
0.05 MAX THE EXPOSED PAD, REFER TO
0.70 THE PIN CONFIGURATION AND
0.02 NOM
FUNCTION DESCRIPTIONS
COPLANARITY SECTION OF THIS DATA SHEET.
SEATING 0.08
PKG-003641/004499
PLANE 0.20 REF
10-10-2018-B
COMPLIANT TO JEDEC STANDARDS MO-220-WKKD
Figure 82. 48-Lead Lead Frame Chip Scale Package [LFCSP]

7 mm × 7 mm Body and 0.75 mm Package Height
(CP-48-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2, 3 Temperature Range Package Description Package Option
AD9228ABCPZ-40 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP] CP-48-9
AD9228ABCPZRL7-40 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP] CP-48-9
AD9228ABCPZ-65 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP] CP-48-9
AD9228ABCPZRL7-65 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP] CP-48-9
AD9228-65EBZ Evaluation Board
1
Z = RoHS Compliant Part.
2
Reference PCN 09_0156.
3
For the AD9228-65EBZ, the interposer board (HSC-ADC-FIFO5-INTZ) is required to connect to the HSC-ADC-EVALCZ data capture board.
©2006–2020 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D05727-11/20(G)

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Quad, 12-Bit, 40 MSPS/65 MSPS

Serial LVDS 1.8 V A/D Converter

119 mW ADC power per channel at 65 MSPS AD9228

SFDR = 82 dBc (to Nyquist) 12

DNL = ±0.3 LSB (typical) 12

Serial LVDS (ANSI-644, default) 12

Applications ...................................................................................... 1 Clock Input Considerations ..................................................... 23

General Description ......................................................................... 1 Serial Port Interface (SPI) ............................................................. 31

Functional Block Diagram .............................................................. 1 Hardware Interface .................................................................... 31

Product Highlights ........................................................................... 1 Memory Map .................................................................................. 33

Specifications .................................................................................... 4 Reserved Locations .................................................................... 33

AC Specifications ......................................................................... 5 Default Values ............................................................................ 33

Digital Specifications ................................................................... 6 Logic Levels ................................................................................. 33

Switching Specifications .............................................................. 7 Evaluation Board ............................................................................ 37

Timing Diagrams.............................................................................. 8 Power Supplies ........................................................................... 37

Absolute Maximum Ratings ......................................................... 10 Input Signals ............................................................................... 37

Thermal Impedance ................................................................... 10 Output Signals ............................................................................ 37

Equivalent Circuits ......................................................................... 13 Outline Dimensions ....................................................................... 53

Typical Performance Characteristics ........................................... 15 Ordering Guide .......................................................................... 53

Theory of Operation ...................................................................... 20

Figure 2. 12-Bit Data Serial Stream, MSB First (Default)

Figure 3. 10-Bit Data Serial Stream, MSB First

Figure 4. 12-Bit Data Serial Stream, LSB First

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 7. Pin Function Descriptions

Figure 13. Equivalent SENSE Circuit

TYPICAL PERFORMANCE CHARACTERISTICS

50 80dB 50 2V p-p, SNR

FUNDAMENTAL LEVEL (dB) –3 –3dB CUTOFF = 315MHz

Figure 43. Switched-Capacitor Input Circuit

Figure 50. Single-Ended Input Configuration

187Ω 680nH 33Ω 10kΩ

LON VIN LPF

18nF 274Ω 0.1μF

50Ω* 50Ω* 240Ω 240Ω

120 TOTAL POWER 300

type of source (by gating, dividing, or another method), it must 20 200

In power-down mode, low power dissipation is achieved by

EYE DIAGRAM VOLTAGE (V)

TIE JITTER HISTOGRAM (Hits)

To change the output data format to twos complement, see the

Table 8. Digital Output Coding

times the sample clock rate, with a maximum of 780 Mbps

Table 9. Flexible Output Test Modes

The PN sequence long pattern produces a pseudorandom bit

CSB Pin Table 13. Reference Settings

VREF ERROR (%)

Figure 66. VREF Accuracy vs. Load

1µF 0.1µF 0.5V –0.18

Figure 65. External Reference Operation

SERIAL PORT INTERFACE (SPI)

Figure 68. SDIO Pin Loading

tDS tHI tCLK tH

SCLK DON’T CARE DON’T CARE

SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE

Table 15. Serial Timing Definitions

Table 16. Memory Map Register

Figure 71. Evaluation Board Connection