Logic Double Patterning

Logic Double Patterning at Pitches Below 80 nm
Sokudo Lithography Forum

Semicon West 2009
Tom Wallow
Logic Pathfinding Complexity Below 80 nm
Lithography challenges
too many to mention
Design challenges
living with simpler geometries
Process challenges
cost-effective double patterning
Materials challenges
for resists, size matters as much as wavelength
Æ Why does all this matter for tracks?
7/15/2009 2
The Low-k1 Lithographic Resolution Regime
Low k1: 0.5 > k1> k1 <
p λ
= k1
2 NA
NA(max) = 1.35
k1(min) ~ 0.28
Æ p(min) ~ 80 nm
Only 2 diffracted orders Only 1 diffracted order

form image at wafer plane captured
No modulation at wafer
plane
7/15/2009 3
ITRS Lithography Roadmap 2007
Logic
nodes
32 nm
22 nm
15 nm 80 nm pitch
Logic pitch is relaxed vs. DRAM, but will transition

below 80 nm for 15 nm node.
7/15/2009 4
Patterning and k1 Factor
Process
Improvement
RB OPC
k1 > 0.6
7/15/2009 5
Including process
Print Image at bestvariation
focus
Process
Improvement
RB OPC
Problems everywhere!
k1 Æ 0.35
7/15/2009 6
Process
Improvement
RB OPC
It’s not enough MB OPC

OAI
k1 ~ 0.35
7/15/2009 7
Process
Improvement
RB OPC
MB OPC
OAI
RDR
DFM
k1 = 0.35
7/15/2009 8
Process
Improvement
RB OPC
MB OPC
OAI
RDR
DFM
k1 ~ 0.3
7/15/2009 9
Process
Improvement
RB OPC
MB OPC
OAI
RDR
DFM
DDL (DE)
Single
Orientation
Cut Masks
(LELE)
k1 ~ 0.28
7/15/2009 10
Transition at 80 nm Pitch for Logic
80 nm pitch is ultra-low k1 factor

Unidirectional control only
Requires double patterning already, but not necessarily pitch-split
Solutions at 80 nm must address:

Both 1D at 2D layout
Both brightfield and darkfield
(pitch splitting is not fundamentally required for 193i)
Solutions below 80 nm must address:

Same issues as >80 nm, but with minimal increased mask count
(pitch splitting is fundamentally required for 193i)
Æ Solutions for device and gate will not be same as solutions for
contacts, metals, and vias
7/15/2009 11
Options Below 80 nm
Option 1: Pitch split double patterning

Litho-Etch-Litho-Etch (LELE)
Spacer patterning (SADP)
Litho-Freeze-Litho-Etch (LFLE)
Option 2: EUV
Option 3: Next generation lithography
NIL
DW EB
New technologies
7/15/2009 12
Effective k1 Below 0.25: Pitch Splitting
k1 at 2x half-pitch single pattern k1

64 nm HP
k1 ~ 0.45
k1 (@1.35 NA)
45 nm HP
k1 ~ 0.32
44 nm HP
k1 ~ 0.31
double patterning
effective k1
32 nm HP k1(effective) ~0.224
64 nm HP k1 ~0.45 Half-pitch (nm)
7/15/2009 13
Double Patterning Options
Additional dimensions:
Development maturity
Spacer SIT EDA implementation
Projected cost per wafer level
Process Complexity
LELE Throughput
etc.
Ion-beam,
e-beam, Image
plasma... LFLE Reversal
Coating
Dual-tone,
UV, VUV multi-solvent
Vapor Freeze ‘Double Exposure’
Thermal Cure Nonlinear Resists

Dual-develop Memoryless Resists
DDL SIT etc.
Patterning Materials Complexity

Many process options are under development
7/15/2009 14
LFLE Processes
Ion-beam,
Dual-tone, Image
Thermal Cure Coating UV, VUV Vapor Freeze e-beam,
multi-solvent Reversal
plasma...
Many outstanding materials and process innovations

(Too many examples to include in .pdf version)
7/15/2009 15
LFLE Interest
LFLE Publications by year

30
SPIE
25 Photopolymers
Engagement by:
Other
20 All resist suppliers
Total
Major tool suppliers
15 Consortia
10 Semi Manufacturer R&D
EDA vendors
5
0
05
06
07
08
09
20
20
20
20
20
7/15/2009 16
Steps Toward LFLE Maturity and Production Use
Clear level targets for LFLE implementation

FEOL vs. BEOL
Decomposition-friendly design; mature EDA tools

Superior process and device performance
Minimal CDU contributions from additional LFLE process steps
Competitive defectivity and yield
Throughput advantages
Cost advantages
7/15/2009 17
Where Does LFLE Fit?
Brightfield: relatively straightforward examples

Gate level patterning with LFLE vs. incumbent methods
Darkfield examples:
contacts
BEOL- trenches and vias
Æ Fundamentally different implementations

‘Decomposition-friendly’ design
7/15/2009 18
Examples of Contact/Via Double Patterning
Checkerboard LELE Cross-Grid LFLE
k1(contacts) = *k1(lines)
-Burkhardt and Colburn, JVSTB 2009 (in press) k1 ~ 0.28
-many reports starting 2005
Decomposition-friendly design is key
How will these accommodate gate pitch <80nm?

7/15/2009 19
LFLE Trench Pitch Splitting
LELE LFLE
Mask 1 Mask 2 Mask 1 Mask 2
No opening!
Resist 2 Resist 2
Hard Mask Frozen Resist 1
First pattern Second pattern LELE decomposition

doesn’t work for LFLE
7/15/2009 20
LFLE Trench Decomposition
Mask 1 Mask 2
+ =
Resist
Frozen Resist
First pattern Second pattern
7/15/2009 21
What else may we need from Tracks
for Double Patterning?
Patterning at 1:3 duty cycle is harder...
Lines: Is trim etch enough?
Trenches and contacts: is taper etch enough?
Ancillaries
Track based vs. etch based 0.13
0.12
Cost of ownership
0.11
0.1
0.09 Target CD
0.08
0.07
0.06 Isofocal
0.05
0.04
-60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60
Æ Additional modules, additional reagents, additional process steps

7/15/2009 22
Other Resist Performance Limits Below 80 nm
Fundamental materials properties scaling in ultrathin films

Materials strength scaling- pattern collapse
Resist structure homogeneity

component segregation
interfacial confinement
Why discuss this in the context of track processing?

Resists become ‘stacks’
Ancillary processing gains in importance
More process steps, more coats, more reagents
7/15/2009 23
Pattern Collapse
c) d)
-Cao et al., JVSTB 2000
-Yoshimoto et al. J. Appl. Phys. 2004
Critical height for collapse (Hc) does not scale with CD for any current model
Deviation from linear scaling becomes more severe as modulus decreases
7/15/2009 24
Scaling of Materials Properties
Glassy core;
softened exterior
σ (MD segment size; σ ~1.5 nm)

-Van Workum and de Pablo -Yoshimoto et al.
Phys. Rev. Lett. 2003 J. Chem. Phys. 2005
Independent simulation methods Softened shell grows vs.

predict nonlinear modulus decrease glassy core below 40 nm CD
below 40 nm CD
7/15/2009 25
Process Improvement
with Development Modifications
Surfactant Rinse No Surfactant Rinse
72
Pitch (nm)
Baseline Process
LER = 4.3 +/- 0.4 nm
64
Pattern Collapse Suppression

-Sugiyama, M. et. al., Proc. SPIE 2007 Surface Conditioner Process
-Jouve, A. et al., Proc. SPIE 2006 LER = 3.2 +/- 0.4 nm
-Wallow, T. et al, Proc. SPIE 2008
LER Reduction
7/15/2009 26
Substrate Confinement Effects
-Naulleau, P. et al., JVSTB 2008
-Singh, L. et al., Proc. SPIE 2006
78 nm
3σ LER (nm)
Underlayer A
220 nm Underlayer B
Reflectivity control is no longer enough

Interfacial engineering
Resist/interface matching- resist
becomes a ‘stack’ Defocus (nm)
7/15/2009 27
Conclusions
Regardless of which lithographic technologies win

below 80 nm pitch, patterning processes will become
more complex.
Double patterning: LFLE will require greater track flexibility and

configurability vs. LELE
Double patterning: any method is likely to require more

complex process flows to compensate for 1:3 duty cycle
Fundamental scaling: resist structures will be smaller, weaker,

and more sensitive to stack and process. ‘Nice to have’
ancillary track processes are likely to become a necessity
7/15/2009 28
Acknowledgments
Yunfei Deng
Ryoung-han Kim
Oleg Kritsun
Jongwook Kye
Bruno La Fontaine
Harry Levinson
Yuansheng Ma
Uzo Okoroanyanwu
Kenji Yoshimoto
Equipment and Materials Suppliers
7/15/2009 29

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Logic Double Patterning at Pitches Below 80 nm

Sokudo Lithography Forum

 Æ Why does all this matter for tracks?

Low k1: 0.5 > k1> k1 <

Only 2 diffracted orders Only 1 diffracted order

 Logic pitch is relaxed vs. DRAM, but will transition

It’s not enough MB OPC

 80 nm pitch is ultra-low k1 factor

 Solutions at 80 nm must address:

 Solutions below 80 nm must address:

 Option 1: Pitch split double patterning

k1 at 2x half-pitch single pattern k1

 64 nm HP k1 ~0.45 Half-pitch (nm)

Thermal Cure Nonlinear Resists

Patterning Materials Complexity

 Many outstanding materials and process innovations

LFLE Publications by year

 Clear level targets for LFLE implementation

 Decomposition-friendly design; mature EDA tools

 Brightfield: relatively straightforward examples

 Æ Fundamentally different implementations

Checkerboard LELE Cross-Grid LFLE

 Decomposition-friendly design is key

 How will these accommodate gate pitch <80nm?

First pattern Second pattern LELE decomposition

First pattern Second pattern

 Æ Additional modules, additional reagents, additional process steps

 Fundamental materials properties scaling in ultrathin films

 Resist structure homogeneity

 Why discuss this in the context of track processing?

 Ancillary processing gains in importance

 More process steps, more coats, more reagents

-Cao et al., JVSTB 2000

-Yoshimoto et al. J. Appl. Phys. 2004

σ (MD segment size; σ ~1.5 nm)

Independent simulation methods Softened shell grows vs.

Pattern Collapse Suppression

 Reflectivity control is no longer enough

 Regardless of which lithographic technologies win

 Double patterning: LFLE will require greater track flexibility and

 Double patterning: any method is likely to require more

 Fundamental scaling: resist structures will be smaller, weaker,

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Æ Why does all this matter for tracks?

Logic pitch is relaxed vs. DRAM, but will transition

80 nm pitch is ultra-low k1 factor

Solutions at 80 nm must address:

Solutions below 80 nm must address:

Option 1: Pitch split double patterning

64 nm HP k1 ~0.45 Half-pitch (nm)

Many outstanding materials and process innovations

Clear level targets for LFLE implementation

Decomposition-friendly design; mature EDA tools

Brightfield: relatively straightforward examples

Æ Fundamentally different implementations

Decomposition-friendly design is key

How will these accommodate gate pitch <80nm?

Æ Additional modules, additional reagents, additional process steps

Fundamental materials properties scaling in ultrathin films

Resist structure homogeneity

Why discuss this in the context of track processing?

Ancillary processing gains in importance

More process steps, more coats, more reagents

Reflectivity control is no longer enough

Regardless of which lithographic technologies win

Double patterning: LFLE will require greater track flexibility and

Double patterning: any method is likely to require more

Fundamental scaling: resist structures will be smaller, weaker,