Digital System

Design

Lab Manual

Department of Electronics and Communication

Manipal Institute of Technology
Manipal
Expt. No Name of the Experiment

1 Arithmetic circuits

2 Multiplexers & Demultiplexers

3 Encoders & Decoders

4 Study of Flip-flops

5 Counters and Shift Registers

 Expt. No. 1
ARITHMETIC CIRCUITS

Aim:
 To design, implement and test half adder and half subtractor, Full adder and Full subtractor.
 To study 4-bit parallel adder – IC 7483
 To design, implement BCD code arithmetic circuits using IC 7483

Equipment & Components Required:

 ICs 7408, 7432, 7404, 7400, 7486, 7410, 7483
 IC trainer kit, Connecting wires

A. Half Adder

Truth table:

A B C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

S=A⊕B C=AB
B. Half Subtractor

Truth Table
Input Output
X Y D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

D=X⊕Y B= X Y
C. Full adder

Truth Table

Input Output
A B Cin Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

S=A⊕B⊕C in C out =AB+BC in +C in A

D. Full Subtractor
Truth Table

Input Output
X Y Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

D=X⊕Y⊕B in B out =X⊕Y Bin + X Y

E. 4-Bit adder / 2’s complement subtractor

When control (Cin) input is 0, input B = B3 B2 B1 B0 is added to input A = A3 A2 A1 A0.

When control (Cin) input is 1, 2’s complement of B is added to input A. (i.e., A-B)
Difference is available at S3 S2 S1 S0, borrow output at Cout.

F. BCD adder

When two 4- bit BCD numbers are added, if the sum exceeds 9 or if there is a carry ,then
6 is added to the sum and a carry is generated to the next decimal digit. Carry from the
addition of 6 (if any) is neglected.
Exercises:
1. Implement a full adder using two half adders and one OR gate.
2. Implement a full subtractor using two half subtractors and any additional gate.
 Expt. No. 2
MULTIPLEXERS AND DEMULTIPLEXERS
Aim:
 To design and implement various multiplexer circuits and to generate logic
functions using multiplexers.
 To design and implement Demultiplexer.

Components & Equipment Required:

 ICs 74151, 74153
 Logic gates
 IC trainer kit, connecting wires

A. 4:1 Multiplexer using only NAND gates

Function Table:

S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

Y= S1 S0 D 0 + S1 S0 D 1 +S 1 S 0 D2 +S 1 S 0 D3
B. Implement f = Σm (0, 3, 5, 7, 8, 10, 14) using i) 8:1 MUX ii) 4:1 MUX and additional gates

Function Table:

Using Using
A B C D F
8:1 MUX 4:1 MUX
0 0 0 0 1 I0 = D
0 0 0 1 0 I0 =C⊕D
0 0 1 0 0 I1 = D
0 0 1 1 1
0 1 0 0 0 I2 = D
0 1 0 1 1 I1 =D
0 1 1 0 0 I3 = D
0 1 1 1 1
1 0 0 0 1 I 4= D
1 0 0 1 0 I2 =D
1 0 1 0 1 I5 = D
1 0 1 1 0
1 1 0 0 0 I6 =0
1 1 0 1 0 I3 =C D
1 1 1 0 1 I7 = D
1 1 1 1 0

Using 8:1 Mux Using 4:1 Mux

C. Design a 1 to 4 Demux using basic gates.

Select Data Output

lines
S1 S0 D Y0 Y1 Y2 Y3
0 0 0/1 D 0 0 0
0 1 0/1 0 D 0 0
1 0 0/1 0 0 D 0
1 1 0/1 0 0 0 D

Exercises:
1. Implement 8:1 MUX using 2:1 multiplexers.
2. Implement F =Σm(0,5,7,11,15,16,18,25,29 ) using two 8:1 and one 2:1 MUX.
 Expt. No. 3
ENCODERS AND DECODERS
Aim:
 To design and implement Decoders and Encoders.

Components and Equipment required :

 ICs 74139, 74138, 74154, 74148
 Logic gates, IC trainer kit, connecting wires

A. Design and implement 2 to 4 decoder using basic gates:

Function Table:

INPUT OUTPUT
A B D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

B. Design and implement 2 to 4 decoder with enable input using only NAND gates

Input Output
E A B D0 D1 D2 D3
0 X X 1 1 1 1
1 0 0 0 1 1 1
1 0 1 1 0 1 1
1 1 0 1 1 0 1
1 1 1 1 1 1 0
C. Design and implement Octal to Binary Priority encoder using basic gates

Truth Table:

Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 A B C

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 1 0 0 0 1 0 0

0 0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 0 1 1 1 1

A= D4+D5+D6++D7

B= D2+D3+D6+D7

C= D1+D3+D5+D7
Exercises:

1. Design and implement a 4 to 16 decoder using two 74138 decoders.

2. Implement f(A, B, C, D) = Σm(0, 3, 5, 9) using two 74138 ICs and additional gate
 Expt. No. 4
STUDY OF FLIP-FLOPS
Aim:
 To study the operations of SR Flip-flop, D Flip-flop, JK Flip-flop, T Flip-flop.
 To study the IC –7474 & IC – 7473.

Components & Equipment Required:

 ICs 7400, 7473, 7474
 IC trainer kit, connecting wires
 Cathode Ray Oscilloscope

A. SR Flip-flop using NAND gates:

Truth Table:

INPUT OUTPUT

CLK S R Qn 1 Qn 1

Rising Edge 0 0 Qn Qn
Rising Edge 0 1 0 1
Rising Edge 1 0 1 0
Rising Edge 1 1 Not Allowed

Note : Apply high-going mono pulse to CLK

B. D Flip-flop using NAND gates:

Truth Table:

INPUT OUTPUT

CLK D Qn 1 Qn 1

LOW X Qn Qn
Rising
0 0 1
Edge
Rising
1 1 0
Edge

Note: Use NAND gates to implement SR Flip-flop

C. JK Flip-Flop using NAND gates:

Truth Table

INPUT OUTPUT

J K Qn 1 Qn 1
Rising Edge 0 0 Qn Qn
Rising Edge 0 1 0 1
Rising Edge 1 0 1 0
Rising Edge 1 1 Qn Qn
D. T Flip-Flop using NAND gates:

Truth Table:

INPUT OUTPUT

CLK T Qn 1 Qn 1

LOW X Qn Qn
Rising Qn
0 Qn
Edge
Rising
1 Toggling
Edge

Note: Implement JK flip-flop using NAND gates

E. Study of IC 7474: Positive edge triggered dual D Flip-flops with preset and clear.

Truth table:

PRESET CLEAR CLOCK DATA

Qn 1 Qn 1
PR CLR CLK D
0 1 X X 1 0
1 0 X X 0 1
1 1 0 X Qn Qn
1 1 Rising Edge 1 1 0
1 1 Rising Edge 0 0 1

F. Study of 74LS73A: Negative edge triggered dual JK Flip-flops with clear

Truth Table:

CLR CLK J K Qn 1 Qn 1

0 X X X 0 1

1 Falling Edge 0 0 Qn Qn
1 Falling Edge 1 0 1 0
1 Falling Edge 0 1 0 1
1 Falling Edge 1 1 Qn Qn
1 1 X X Qn Qn

G. Conversion of Flip-Flops

Convert D to SR Flip-flop

S R Qn Qn 1 D
0 0 0 0 0
0 0 1 1 1
0 1 0 0 0
0 1 1 0 0
1 0 0 1 1
1 0 1 1 1
1 1 0 X X
1 1 1 X X

D=S+ R Q
Exercise:
1. Convert D flip-flop to T Flip- flop
2. Convert JK flip-flop to SR Flip-flop.
 Expt. No. 5
COUNTERS & SHIFT REGISTERS

Aim:
 To design and test 4 bit ripple up-counter using 7473.
 To design and test 4-bit Synchronous up counter using IC7473.
 To test Johnson and Ring counters.
 To test SISO and SIPO shift register

Components & Equipment Required:

 ICs 7408, 7473, 7474
 IC trainer kit, connecting wires

A. 4 bit ripple up counter

Count from QDQCQBQA 0000 to 1111

B. 4 bit Synchronous up counter

Excitation Table of JK Flip-Flop

Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

In the Excitation table shown above Qn and Qn+1 are present and next state outputs. For a 4- bit
counter, it is required to count from 0 to 15, which requires 4 JK Flip-Flops.

Let the outputs of these Flip-Flops be QD,QC,QB,QA respectively and JA,KA be the inputs of Flip-
Flop A. JB,KB of Flip-Flop B & so on.
 QD QC QB QA QD+1 QC+1 QB+1 QA+1 JD KD JC KC JB KB JA KA
0 0 0 0 0 0 0 1 0 X 0 X 0 X 1 X
0 0 0 1 0 0 1 0 0 X 0 X 1 X X 1
0 0 1 0 0 0 1 1 0 X 0 X X 0 1 X
0 0 1 1 0 1 0 0 0 X 1 X X 1 X 1
0 1 0 0 0 1 0 1 0 X X 0 0 X 1 X
0 1 0 1 0 1 1 0 0 X X 0 1 X X 1
0 1 1 0 0 1 1 1 0 X X 0 X 0 1 X
0 1 1 1 1 0 0 0 1 X X 1 X 1 X 1
1 0 0 0 1 0 0 1 X 0 0 X 0 X 1 X
1 0 0 1 1 0 1 0 X 0 0 X 1 X X 1
1 0 1 0 1 0 1 1 X 0 0 X X 0 1 X
1 0 1 1 1 1 0 0 X 0 1 X X 1 X 1
1 1 0 0 1 1 0 1 X 0 X 0 0 X 1 X
1 1 0 1 1 1 1 0 X 0 X 0 1 X X 1
1 1 1 0 1 1 1 1 X 0 X 0 X 0 1 X
1 1 1 1 0 0 0 0 X 1 X 1 X 1 X 1

Draw K-maps for various Js & Ks and simplify. Implement the logic circuit and verify.

1. Connect the circuit.

2. Momentarily clear all the inputs by giving CLR = 0 & then make it permanently
high by giving CLR = 1.
3. Verify the circuit by observing the output for each clock pulse. After the 15th clock
pulse (i.e. for the 16th clock pulse) output QDQCQBQA = 0000
C. Ring Counter

CLK QD QC QB QA
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 1 0 0 0

D. Jhonson Counter

CLK QD QC QB QA
1 0 0 0 0
2 1 0 0 0
3 1 1 0 0
4 1 1 1 0
5 1 1 1 1
6 0 1 1 1
7 0 0 1 1
8 0 0 0 1
E. SISO and SIPO Shift Register

1. Connect the circuit as shown in the circuit diagram

2. Switch on & momentarily clear all the Flip-Flops by giving low to the clear input. Then
make it permanently logic1.
3. Enter any 4-bit serial input using clock pulse for every bit.
4. For example, to enter 1011
5. First make serial input =1, apply a clock pulse,
6. Make serial input=1, again apply a clock pulse,
7. Make serial input=0 ,again apply a clock pulse,
8. Make serial input =1, apply a clock pulse.
9. This ensures that the register has word 1011 stored in it.
10. Observe the data at the output of each shift register simultaneously.
11. This constitutes parallel output data.
12. To observe the output data in serial fashion, apply clock pulse by keeping serial input data
zero.

Exercises:

1. Design and implement a ripple decade counter and verify its operation.