4-Phase Adiabatic Logic Design Using VHDL: End Semester Presentation

22 Dec, 2020
4-phase Adiabatic Logic Design using VHDL

END SEMESTER PRESENTATION
Project Pannel: Prof. S. Baishya (Chairman)

Dr. P. K. Paul
Dr. M. Kavicharan (Convener)
Presented by: K. V. Lakshmi Sri

Scholar No: 2024204
1
Mtech, Microelectronics and VLSI, NIT Silchar
OBJECTIVE
To learn about the 4-phase Adiabatic Logic Circuits, their advantages and
disadvantages over static CMOS circuits, study the methodology and
implementation in VHDL, as performed in the reference paper [1].
2
INTRODUCTION
Static CMOS Logic Circuits
Fig 1 : switching power dissipations in static CMOS circuits

3
Fig 2 : Charging transition in CMOS inverter (capacitor charging)
Energy supplied = Energy dissipated =
Half of the power supplied is dissipated as heat.

Our objective is to design a circuit while lowering the switching power dissipation
4
Adiabatic Logic Circuits
The term ‘adiabatic’ refers to thermodynamics.
Analogy - both in thermodynamic systems and our logic circuits, the energy is transferred
to the environment in the form of heat.
‘Adiabatic Logic Circuits’ - circuits which do not transfer any energy to the environment in
the form of heat.
5
Conventional Charging
Fig 3 : (a) Circuit for Conventional Charging; (b) Change in current and charge with respect to time (current decreases and charge increases)
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Adiabatic Charging
Fig 4 : Circuit for Adiabatic Charging; derivation of energy dissipated

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Thus instead of applying a voltage that rises quickly, we need to apply a voltage that rises
more slowly.
Fig 5 : Applied voltage rising with different T values; here T1is greater than T2
Fig 6 : Pulsed Power Supply Signal

8
Two key rules:
● Never turn ‘ON’ a transistor when there is a voltage potential between

the source and drain.
● Never turn ‘OFF’ a transistor when current is flowing through it.
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Realization of Adiabatic Logic Circuits
We apply the pulse power supply instead of constant Vdd supply as we did in static CMOS.
The inputs and outputs are dual rail encoded.
Fig 7 : (a) Static CMOS logic implementation; (b) Adiabatic logic implementation
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PFAL - Positive Feedback Adiabatic Circuits : A technique to realize Partially Adiabatic Logic Circuits (PALC)
Fig. 9(a): PFAL general logic circuit;

supply voltage is the pulsed power supply
Fig 9(b): PFAL inverter logic circuit; phi(t)is the pulsed power
supply
We can notice that the input nMOS network is connected in parallel with the pMOS transistors. 11
Disadvantages of Adiabatic Circuits
● the complexity of the circuit increases and the number of transistors increases
● we trade off dynamic power dissipation for delay
● number of transistors increases, so they require more area than the Static- CMOS
● design is much more complicated
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4-Phase Adiabatic Logic Circuit
The adiabatic circuit operates in 4 phases as shown in Fig 10.
These phases are namely the Evaluation(E), Hold(H), Recovery(R) and Idle(I).
Fig 10 : The 4 - phases; 1.8 is the Vdd in this example figure

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LITERATURE REVIEW
Paper - VHDL-based Modelling Approach for the Digital Simulation of 4-phase Adiabatic
Logic Design
Sachin Maheshwari, Viv A. Bartlett and Izzet Kale
28th International Symposium on Power and Timing Modeling, Optimization and Simulation,
Costa Brava, Spain, 2 to 4 July 2018.
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VHDL-based Modelling Approach for the Digital Simulation of 4-phase Adiabatic Logic Design
● The paper proposes a VHDL-based modelling approach for the design and verification of the
4-phase adiabatic logic systems
● The proposed approach includes the modelling of the dual rail input and output signals
● A new approach for modelling 4-phase adiabatic logic circuits using VHDL is presented
● The exact behaviour of the trapezoidal power clock is represented by modelling all the four
periods distinctively
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METHODOLOGY
The steps are as follows, with regard to the reference paper:
1. Simulate the power clock signal in VHDL

2. Conversion of Dual rail input to adiabatic inputs
3. Gate level modelling of adiabatic logic gates
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1. How to implement the pulsed power signal?
Two types of modeling: voltage level event based modeling and multi level event based modeling.
Paper implements the latter.
Fig 11 : voltage level event based modelling [1]
Fig 12 : multi level event based modelling [1]

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Fig 13 : The power clock signal simulated in VHDL [1]
4 states and 3 logic levels are being used.
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2. Conversion of the dual rail pulse input to adiabatic inputs
An equivalent dual-rail adiabatic outputs (A, Ab) are generated from the dual-rail pulse
signals (IN, INb).
Fig 14 : Conversion of the dual-rail pulse input to adiabatic inputs [1]
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3. Gate Level Modelling:
VHDL modelling for an adiabatic NOT/BUF gate is done using the power clock generator,
pulse input to adiabatic input (multi-level) conversion and the package defining the four
periods of the power clock.
Fig 15 : A conceptual block diagram of an adiabatic NOT/BUF Gate [1] 20

Fig. 16(a) : Waveform results for PFAL NOT/BUF gate (a) VHDL Model [1].
21
Fig. 16(b) : Waveform results for PFAL NOT/BUF gate (b) SPICE [1].
22
REFERENCES
[1] VHDL-based Modelling Approach for the Digital Simulation of 4-phase Adiabatic Logic Design,
Sachin Maheshwari, Viv A. Bartlett and Izzet Kale - 28th International Symposium on Power and Timing
Modeling, Optimization and Simulation, Costa Brava, Spain, 2 to 4 July 2018.
[2] https://nptel.ac.in/courses/106/105/106105034/ - NPTEL course, CSE, Low Power VLSI CIrcuits and
Systems, Lec-36 - Adiabatic Logic Circuits by Prof. Ajit Pal, IIT Kharagpur.
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Thank You
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22 Dec, 2020

4-phase Adiabatic Logic Design using VHDL

Project Pannel: Prof. S. Baishya (Chairman)

Presented by: K. V. Lakshmi Sri

Fig 1 : switching power dissipations in static CMOS circuits

Energy supplied = Energy dissipated =

Half of the power supplied is dissipated as heat.

The term ‘adiabatic’ refers to thermodynamics.

Fig 4 : Circuit for Adiabatic Charging; derivation of energy dissipated

Fig 6 : Pulsed Power Supply Signal

● Never turn ‘ON’ a transistor when there is a voltage potential between

The inputs and outputs are dual rail encoded.

Fig. 9(a): PFAL general logic circuit;

● we trade off dynamic power dissipation for delay

● design is much more complicated

Fig 10 : The 4 - phases; 1.8 is the Vdd in this example ﬁgure

1. Simulate the power clock signal in VHDL

3. Gate level modelling of adiabatic logic gates

Fig 11 : voltage level event based modelling [1]

Fig 12 : multi level event based modelling [1]

4 states and 3 logic levels are being used.

Fig 14 : Conversion of the dual-rail pulse input to adiabatic inputs [1]

Fig 15 : A conceptual block diagram of an adiabatic NOT/BUF Gate [1] 20

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