Kalinga University

Department of Computer Science

Course- DICS Sem-IV

Subject- Computer Organization
Subject Code: DICS405

UNIT-III

A Peripheral Device is defined as the device which provides input/output functions for a

computer and serves as an auxiliary computer device without computing-intensive
functionality. Generally peripheral devices, however, are not essential for the computer to
perform its basic tasks, they can be thought of as an enhancement to the user’s experience.
A peripheral device is a device that is connected to a computer system but is not part of the
core computer system architecture. Generally, more people use the term peripheral more
loosely to refer to a device external to the computer case.

Classification of Peripheral devices:

It is generally classified into 3 basic categories which are given below:

1. Input Devices:

The input devices is defined as it converts incoming data and instructions into a
pattern of electrical signals in binary code that are comprehensible to a digital
computer.

Example:
Keyboard, mouse, scanner, microphone etc.

2. Output Devices:

An output device is generally reverse of the input process and generally

translating the digitized signals into a form intelligible to the user. The output
device is also performed for sending data from one computer system to another.
For some time punched-card and paper-tape readers were extensively used for
input, but these have now been supplanted by more efficient devices.
Example:
Monitors, headphones, printers etc.

3. Storage Devices:

Storage devices are used to store data in the system which is required for
performing any operation in the system. The storage device is one of the most
requirement devices and also provide better compatibility.

Example:

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 Hard disk, magnetic tape, Flash memory etc.

Advantage of Peripherals Devices:

Peripheral’s devices provides more feature due to this operation of the system is easy.
These are given below:
 It is helpful for taking input very easily.
 It is also provided a specific output.
 It has a storage device for storing information or data
 It also improves the efficiency of the system.

Input/Output Interface
Input-Output Interface is used as an method which helps in transferring of information
between the internal storage devices i.e. memory and the external peripheral device. A
peripheral device is that which provide input and output for the computer, it is also called
Input-Output devices. For Example: A keyboard and mouse provide Input to the computer
are called input devices while a monitor and printer that provide output to the computer are
called output devices. Just like the external hard-drives, there is also availability of some
peripheral devices which are able to provide both input and output.

In micro-computer base system, the only purpose of peripheral devices is just to

provide special communication links for the interfacing them with the CPU. To resolve
the differences between peripheral devices and CPU, there is a special need for
communication links.

The major differences are as follows:

1. The nature of peripheral devices is electromagnetic and electro-mechanical. The
nature of the CPU is electronic. There is a lot of difference in the mode of
operation of both peripheral devices and CPU.
2. There is also a synchronization mechanism because the data transfer rate of
peripheral devices are slow than CPU.

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 3. In peripheral devices, data code and formats are differ from the format in the
CPU and memory.
4. The operating mode of peripheral devices are different and each may be
controlled so as not to disturb the operation of other peripheral devices
connected to CPU.
There is a special need of the additional hardware to resolve the differences between CPU
and peripheral devices to supervise and synchronize all input and output devices. 

Functions of Input-Output Interface:

1. It is used to synchronize the operating speed of CPU with respect to input-output

devices.
2. It selects the input-output device which is appropriate for the interpretation of
the input-output device.
3. It is capable of providing signals like control and timing signals.
4. In this data buffering can be possible through data bus.
5. There are various error detectors.
6. It converts serial data into parallel data and vice-versa.
7. It also convert digital data into analog signal and vice-versa.

he block diagram of an Input-Output Interface unit contain the following blocks :

1. Data Bus Buffer
2. Read/Write Control Logic
3. Port A, Port B register
4. Control and Status register

Data Bus Buffer :

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The bus buffer use bi-directional data bus to communicate with CPU. All control word data
and status information between interface unit and CPU are transferred through data bus.

Port A and Port B :

Port A and Port B are used to transfer data between Input-Output device and Interface Unit.
Each port consist of bi-directional data input buffer and bi-directional data output buffer.
Interface unit connect directly with an input device and output disk or with device that
require both input and output through Port A and Port B i.e. modem, external hard-drive,
magnetic disk.

Control and Status Register :

CPU gives control information to control register on basis of control information. Interface
unit control input and output operation between CPU and input-output device. Bits which
are present in status register are used for checking of status conditions. Status register
indicate status of data register, port A, port B and also record error that may be occur
during transfer of data.

Read/Write Control Logic :

This block generates necessary control signals for overall device operations. All commands
from CPU are accepted through this block. It also allow status of interface unit to be
transferred onto data bus through this block accept CS, read and write control signal from
system bus and S0 , S1 from system address bus. Read and Write signal are used to define
direction of data transfer over data bus.
Read Operation: CPU <---- I/O device
Write Operation: CPU ----> I/O device

The read signal direct data transfer from interface unit to CPU and write signal direct data
transfer from CPU to interface unit through data bus.
Address bus is used to select to interface unit. Two least significant lines of address bus
( A0 , A1 ) are connected to select lines S0, S1. This two select input lines are used to select
any one of four registers in interface unit. The selection of interface unit is according to the
following criteria :

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Example :
 If S0, S1 = 0 1, then Port B data register is selected for data transfer between
CPU and I/O device.
 If S0, S1 = 1 0, then Control register is selected and store the control information
send by the CPU.

Synchronous Vs Asynchronous Data Transfer

In Synchronous data transfer, the sending and receiving units are enabled with same
clock signal. It is possible between two units when each of them knows the behaviour of the

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other. The master performs a sequence of instructions for data transfer in a predefined
order. All these actions are synchronized with the common clock. The master is designed to
supply the data at a time when the slave is definitely ready for it. Usually, the master will
introduce sufficient delay to take into account the slow response of the slave, without any
request from the slave. 

The master does not expect any acknowledgment signal from the slave when data is sent by
the master to the slave. Similarly, when data from the slave is read by the master, neither
the slave informs that the data has been placed on the data bus nor the master acknowledges
that the data has been read. Both the master and slave perform their own task of transferring
data at a designed clock period. Since both devices know the behaviour (response time) of
each other, no difficulty arises. 

Prior to transferring data, the master must logically select the slave either by sending
slave’s address or sending “device select” signal to the slave. But there is
no acknowledgment signal from the slave to the master if the device is selected. 

In this timing diagram, the master first places slave’s address in the address bus and read
signal in the control line at the falling edge of the clock. The entire read operation is over in
one clock period.

Advantages –

The design procedure is easy. The master does not wait for any acknowledges signal from
the slave, though the master waits for a time equal to slave’s response time.

The slave does not generate an acknowledge signal, though it obeys the timing rules as per
the protocol set by the master or system designer.

Disadvantages –

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If a slow speed unit connected to a common bus, it can degrade the overall rate of transfer
in the system.

If the slave operates at a slow speed, the master will be idle for some time during data
transfer and vice versa.

Asynchronous Data Transfer

The asynchronous data transfer between two independent units requires that control signals
be transmitted between the communicating units to indicate when they send the data. Thus,
the two methods can achieve the asynchronous way of data transfer.

1. Strobe Control Method

The Strobe Control method of asynchronous data transfer employs a single control line to
time each transfer. This control line is also known as a strobe, and it may be achieved either
by source or destination, depending on which initiate the transfer.

Source initiated strobe: In the below block diagram, you can see that strobe is initiated by
source, and as shown in the timing diagram, the source unit first places the data on the data
bus.

After a brief delay to ensure that the data resolve to a stable value, the source activates a
strobe pulse. The information on the data bus and strobe control signal remains in the active
state for a sufficient time to allow the destination unit to receive the data.

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The destination unit uses a falling edge of strobe control to transfer the contents of a data
bus to one of its internal registers. The source removes the data from the data bus after it
disables its strobe pulse. Thus, new valid data will be available only after the strobe is
enabled again.

In this case, the strobe may be a memory-write control signal from the CPU to a memory
unit. The CPU places the word on the data bus and informs the memory unit, which is the
destination.

Destination initiated strobe: In the below block diagram, you see that the strobe initiated by
destination, and in the timing diagram, the destination unit first activates the strobe pulse,
informing the source to provide the data.

The source unit responds by placing the requested binary information on the data bus. The
data must be valid and remain on the bus long enough for the destination unit to accept it.

The falling edge of the strobe pulse can use again to trigger a destination register. The
destination unit then disables the strobe. Finally, and source removes the data from the data
bus after a determined time interval.

In this case, the strobe may be a memory read control from the CPU to a memory unit. The
CPU initiates the read operation to inform the memory, which is a source unit, to place the
selected word into the data bus.

2. Handshaking Method

The strobe method has the disadvantage that the source unit that initiates the transfer has no
way of knowing whether the destination has received the data that was placed in the bus.
Similarly, a destination unit that initiates the transfer has no way of knowing whether the
source unit has placed data on the bus.

o this problem is solved by the handshaking method. The handshaking method introduces a
second control signal line that replays the unit that initiates the transfer.

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In this method, one control line is in the same direction as the data flow in the bus from the
source to the destination. The source unit uses it to inform the destination unit whether
there are valid data in the bus.

The other control line is in the other direction from the destination to the source. This is
because the destination unit uses it to inform the source whether it can accept data. And in
it also, the sequence of control depends on the unit that initiates the transfer. So it means
the sequence of control depends on whether the transfer is initiated by source and
destination.

Source initiated handshaking: In the below block diagram, you can see that two
handshaking lines are "data valid", which is generated by the source unit, and "data
accepted", generated by the destination unit.

The timing diagram shows the timing relationship of the exchange of signals between the
two units. The source initiates a transfer by placing data on the bus and enabling its data
valid signal. The destination unit then activates the data accepted signal after it accepts the
data from the bus.

The source unit then disables its valid data signal, which invalidates the data on the bus.

After this, the destination unit disables its data accepted signal, and the system goes into its
initial state. The source unit does not send the next data item until after the destination unit
shows readiness to accept new data by disabling the data accepted signal.

This sequence of events described in its sequence diagram, which shows the above
sequence in which the system is present at any given time.

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Destination initiated handshaking: In the below block diagram, you see that the two
handshaking lines are "data valid", generated by the source unit, and "ready for data"
generated by the destination unit.

Note that the name of signal data accepted generated by the destination unit has been
changed to ready for data to reflect its new meaning.

The destination transfer is initiated, so the source unit does not place data on the data bus
until it receives a ready data signal from the destination unit. After that, the handshaking
process is the same as that of the source initiated.

The sequence of events is shown in its sequence diagram, and the timing relationship
between signals is shown in its timing diagram. Therefore, the sequence of events in both
cases would be identical.

Advantages of Asynchronous Data Transfer

Asynchronous Data Transfer in computer organization has the following advantages, such
as:

It is more flexible, and devices can exchange information at their own pace. In addition,
individual data characters can complete themselves so that even if one packet is corrupted,
its predecessors and successors will not be affected.

It does not require complex processes by the receiving device. Furthermore, it means that
inconsistency in data transfer does not result in a big crisis since the device can keep up
with the data stream. It also makes asynchronous transfers suitable for applications where
character data is generated irregularly.

Disadvantages of Asynchronous Data Transfer

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There are also some disadvantages of using asynchronous data for transfer in computer
organization, such as:

The success of these transmissions depends on the start bits and their recognition.
Unfortunately, this can be easily susceptible to line interference, causing these bits to be
corrupted or distorted.

A large portion of the transmitted data is used to control and identify header bits and thus
carries no helpful information related to the transmitted data. This invariably means that
more data packets need to be sent.

Direct Memory Access (DMA)

DMA Controller is a hardware device that allows I/O devices to directly access memory
with less participation of the processor. DMA controller needs the same old circuits of an
interface to communicate with the CPU and Input/Output devices.

Fig-1 below shows the block diagram of the DMA controller. The unit communicates with
the CPU through data bus and control lines. Through the use of the address bus and
allowing the DMA and RS register to select inputs, the register within the DMA is chosen
by the CPU. RD and WR are two-way inputs. When BG (bus grant) input is 0, the CPU can
communicate with DMA registers. When BG (bus grant) input is 1, the CPU has
relinquished the buses and DMA can communicate directly with the memory.

DMA controller registers :

The DMA controller has three registers as follows.

Address register – It contains the address to specify the desired location in memory.

Word count register – It contains the number of words to be transferred.

Control register – It specifies the transfer mode.

All registers in the DMA appear to the CPU as I/O interface registers. Therefore, the CPU
can both read and write into the DMA registers under program control via the data bus.

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  The CPU initializes the DMA by sending the given information through the data
bus.
 The starting address of the memory block where the data is available (to read) or
where data are to be stored (to write).
 It also sends word count which is the number of words in the memory block to be
read or write.
 Control to define the mode of transfer such as read or write.
 A control to begin the DMA transfer.

Priority Interrupt

In a typical application, a number of I/O devices are attached to computer, with each device
being able to originate an interrupt request, so to provide services to device which initiate
interrupt request, the task of interrupt system is to identify the source(device) of interrupt
and then provide services to them.

But, in most cases there is a possibility that several sources will request service
simultaneously. So, in this case, the interrupt system must also need to decide which device
to service first. But, these simple interrupt system are not able for that, so, another system
known as Priority interrupt system is provided.

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Priority Interrupt are systems, that establishes a Priority over the various sources (interrupt
devices) to determine which condition is to be serviced first when two or more requests
arrive simultaneously. This system may also determine which condition are permitted to
interrupt to the computer while another interrupt is being serviced.

Usually, in Priority Systems, higher-priority interrupt levels are served first, as if they
delayed or interrupted, could have serious consequences. And the devices with high-speed
transfer such as magnetic disks are given high-priority, and slow devices such as keyboards
receives low-priority.

Establishing Priority of Simultaneous Interrupt:

The priority of simultaneous interrupts can be established either by software method or

hardware.

The software method which gives priority to simultaneous interrupt is:

Polling

And the hardware method which gives priority to simultaneous interrupt is:

Daisy-Chaining Priority

Now, we will explore to each one of them one by one.

1. Polling:

Polling is the software method of establishing priority of simultaneous interrupt.In this

method, when the processor detects an interrupt, it branches to an interrupt service routine
whose job is to pull each I/O module to determine which module caused the interrupt.

The poll could be in the form of separate command line(e.g., Test I/O).In this case, the
processor raises the Test I/O and places the address of particular I/O module on the address
line. If it has interrupt that is, if interrupt is identified in it.

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 And, it is the order in which they are tested i.e., the order in which they appear on
address line(Service Routine) determine the priority of each interrupt. As while testing,
highest priority source(devices) are tested first then lower-priority devices.

This is very simple method of establishing priority on simultaneous interrupt. But the
disadvantage of polling is that it is very time consuming.

2. Daisy-Chaining Priority

The Daisy–Chaining method of establishing priority on interrupt sources uses the

hardware i.e., it is the hardware means of establishing priority.

In this method, all the device, whether they are interrupt sources or not, connected in a
serial manner. Means the device with highest priority is placed in the first position, which is
followed by lowest priority device. And all device share a common interrupt request line,
and the interrupt acknowledge line is daisy chained through the modules.

The figure shown below, this method of connection with three devices and the CPU.

It works as follows:

When any device raise an interrupt, the interrupt request line goes activated, the
processor when sense it, it sends out an interrupt acknowledge which is first received by

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device1.If device1 does not need service, i.e., processor checks, whether the device has
pending interrupt or initiate interrupt request, if the result is no, then the signal is passed to
device2 by placing 1 in the PO(Priority Out) of device1.And if device need service then
service is given to them by placing first 0 in the PO of device1, which indicate the next-
lower-priority device that acknowledge signal has been blocked. And device that have
processor responds by inserting its own interrupt vector address (VAD) into the data bus for
the CPU to use during interrupt cycle.

In this way, it gave services to interrupt source according to their priority. And thus, we
can say that, it is the order of device in chain that determine the priority of interrupt
sources.

Input/Output Processor

The DMA mode of data transfer reduces CPU’s overhead in handling I/O operations. It also
allows parallelism in CPU and I/O operations. Such parallelism is necessary to avoid
wastage of valuable CPU time while handling I/O devices whose speeds are much slower as
compared to CPU. The concept of DMA operation can be extended to relieve the CPU
further from getting involved with the execution of I/O operations. This gives rises to the
development of special purpose processor called Input-Output Processor (IOP) or IO
channel.

The Input Output Processor (IOP) is just like a CPU that handles the details of I/O
operations. It is more equipped with facilities than those are available in typical DMA
controller. The IOP can fetch and execute its own instructions that are specifically designed
to characterize I/O transfers. In addition to the I/O – related tasks, it can perform other
processing tasks like arithmetic, logic, branching and code translation. The main memory
unit takes the pivotal role. It communicates with processor by the means of DMA.

The Input Output Processor is a specialized processor which loads and stores data into
memory along with the execution of I/O instructions. It acts as an interface between system

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and devices. It involves a sequence of events to executing I/O operations and then store the
results into the memory.

Advantages –

The I/O devices can directly access the main memory without the intervention by the
processor in I/O processor based systems.

It is used to address the problems that are arises in Direct memory access method.

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