Co Unit 6

Input-Output Organization
INPUT-OUTPUT ORGANIZATION
Peripheral Devices Input-Output Interface Asynchronous Data Transfer Modes of Transfer Priority Interrupt Direct Memory Access Input-Output Processor
Serial Communication
Computer Organization
Computer Architectures Lab
Peripheral Devices
PERIPHERAL DEVICES
Input Devices
Keyboard Optical input devices - Card Reader - Paper Tape Reader - Bar code reader - Digitizer - Optical Mark Reader Magnetic Input Devices - Magnetic Stripe Reader Screen Input Devices - Touch Screen - Light Pen - Mouse Analog Input Devices
Output Devices
Card Puncher, Paper Tape Puncher CRT Printer (Impact, Ink Jet, Laser, Dot Matrix) Plotter Analog Voice
Input/Output Interfaces
INPUT/OUTPUT INTERFACE
Provides a method for transferring information between internal storage (such as memory and CPU registers) and external I/O devices Resolves the differences between the computer and peripheral devices
Peripherals - Electromechanical Devices CPU or Memory - Electronic Device
Data Transfer Rate Peripherals - Usually slower CPU or Memory - Usually faster than peripherals
Some kinds of Synchronization mechanism may be needed
Unit of Information Peripherals Byte,Block, CPU or Memory Word Data representations may differ
Computer Organization Computer Architectures Lab
I/O BUS AND INTERFACE MODULES

I/O bus Processor Data Address Control
Interface
Interface
Interface
Interface
Keyboard and display terminal
Printer
Magnetic disk
Magnetic tape
Each peripheral has an interface module associated with it
Interface
- Decodes the device address (device code) - Decodes the commands (operation) - Provides signals for the peripheral controller - Synchronizes the data flow and supervises the transfer rate between peripheral and CPU or Memory Typical I/O instruction
Op. code Device address Function code (Command)
CONNECTION OF I/O BUS

Connection of I/O Bus to CPU
Op. code Device Function address code Accumulator register Computer I/O control
CPU I/O bus
Sense lines Data lines Function code lines Device address lines
Connection of I/O Bus to One Interface

Data lines Peripheral register
Device address
Buffer register
I/O bus
Function code
AD = 1101
Interface Logic
Output peripheral device and controller
Command decoder Status register
Sense lines
I/O BUS AND MEMORY BUS

Functions of Buses * MEMORY BUS is for information transfers between CPU and the MM * I/O BUS is for information transfers between CPU and I/O devices through their I/O interface Physical Organizations * Many computers use a common single bus system for both memory and I/O interface units
- Use one common bus but separate control lines for each functio - Use one common bus with common control lines for both functions
* Some computer systems use two separate buses, one to communicate with memory and the other with I/O interfaces I/O Bus - Communication between CPU and all interface units is via a common I/O Bus - An interface connected to a peripheral device may have a number of data registers , a control register, and a status register - A command is passed to the peripheral by sending to the appropriate interface register - Function code and sense lines are not needed (Transfer of data, control, and status information is always via the common I/O Bus)
ISOLATED vs MEMORY MAPPED I/O

Isolated I/O - Separate I/O read/write control lines in addition to memory read/write control lines - Separate (isolated) memory and I/O address spaces - Distinct input and output instructions
Memory-mapped I/O
- A single set of read/write control lines (no distinction between memory and I/O transfer) - Memory and I/O addresses share the common address space -> reduces memory address range available - No specific input or output instruction -> The same memory reference instructions can be used for I/O transfers - Considerable flexibility in handling I/O operations
I/O INTERFACE
Port A register Bidirectional data bus Bus buffers Port B register I/O data I/O data
CPU
Chip select Register select Register select I/O read I/O write
CS
RS1 RS0
RD WR
Timing and Control
Control register
Control
I/O Device
Status register
Status
Programmable Interface - Information in each port can be assigned a meaning depending on the mode of operation of the I/O device Port A = Data; Port B = Command; Port C = Status
CS RS1 RS0 0 x x 1 0 0 1 0 1 1 1 0 1 1 1
Register selected None - data bus in high-impedence Port A register Port B register Control register Status register
- CPU initializes(loads) each port by transferring a byte to the Control Register Allows CPU can define the mode of operation of each port Programmable Port: By changing the bits in the control register, it is possible to change the interface characteristics
Asynchronous Data Transfer
ASYNCHRONOUS DATA TRANSFER

Synchronous and Asynchronous Operations
Synchronous - All devices derive the timing information from common clock line Asynchronous - No common clock

Asynchronous data transfer between two independent units requires that control signals be transmitted between the communicating units to indicate the time at which data is being transmitted
Two Asynchronous Data Transfer Methods

Strobe pulse - A strobe pulse is supplied by one unit to indicate the other unit when the transfer has to occur Handshaking - A control signal is accompanied with each data being transmitted to indicate the presence of data - The receiving unit responds with another control signal to acknowledge receipt of the data
10
STROBE CONTROL
* Employs a single control line to time each transfer * The strobe may be activated by either the source or the destination unit
Source-Initiated Strobe for Data Transfer

Block Diagram
Data bus
Source unit Strobe Destination unit
Destination-Initiated Strobe for Data Transfer

Block Diagram
Data bus Source unit Strobe Destination unit
Timing Diagram
Data Valid data
Timing Diagram
Valid data Data
Strobe
Strobe
11
HANDSHAKING
Strobe Methods
Source-Initiated The source unit that initiates the transfer has no way of knowing whether the destination unit has actually received data Destination-Initiated The destination unit that initiates the transfer no way of knowing whether the source has actually placed the data on the bus To solve this problem, the HANDSHAKE method introduces a second control signal to provide a Reply to the unit that initiates the transfer
12
SOURCE-INITIATED TRANSFER USING HANDSHAKE

Block Diagram
Source unit Data bus Data valid Data accepted Destination unit
Timing Diagram
Data bus
Valid data
Data valid
Data accepted
Sequence of Events
Source unit Place data on bus. Enable data valid.
Destination unit
Accept data from bus. Enable data accepted Disable data valid. Invalidate data on bus.
Disable data accepted. Ready to accept data (initial state).
* Allows arbitrary delays from one state to the next * Permits each unit to respond at its own data transfer rate * The rate of transfer is determined by the slower unit
13
DESTINATION-INITIATED TRANSFER USING HANDSHAKE

Block Diagram
Source unit Data bus Data valid Ready for data Destination unit
Timing Diagram
Ready for data
Data valid
Data bus
Valid data
Sequence of Events
Source unit Place data on bus. Enable data valid.
Destination unit Ready to accept data. Enable ready for data.
Disable data valid. Invalidate data on bus (initial state).
Accept data from bus. Disable ready for data.
* Handshaking provides a high degree of flexibility and reliability because the successful completion of a data transfer relies on active participation by both units * If one unit is faulty, data transfer will not be completed -> Can be detected by means of a timeout mechanism
14
ASYNCHRONOUS SERIAL TRANSFER

Four Different Types of Transfer Asynchronous serial transfer Synchronous serial transfer Asynchronous parallel transfer Synchronous parallel transfer
Asynchronous Serial Transfer - Employs special bits which are inserted at both ends of the character code - Each character consists of three parts; Start bit; Data bits; Stop bits.
1 Start bit (1 bit) 1 0 0 0 1 0 1 Stop bits (at least 1 bit)
Character bits
A character can be detected by the receiver from the knowledge of 4 rules; - When data are not being sent, the line is kept in the 1-state (idle state) - The initiation of a character transmission is detected by a Start Bit , which is always a 0 - The character bits always follow the Start Bit - After the last character , a Stop Bit is detected when the line returns to the 1-state for at least 1 bit time The receiver knows in advance the transfer rate of the bits and the number of information bits to expect
15
UNIVERSAL ASYNCHRONOUS RECEIVER-TRANSMITTER - UART A typical asynchronous communication interface available as an IC

Bidirectional data bus Bus buffers Transmitter register Shift register Transmit data
Chip select Register select I/O read I/O write
CS RS Timing and Control
Internal Bus
Control register
Transmitter Transmitter clock control and clock Receiver control and clock Shift register Receiver clock Receive data CS RS 0 x 1 0 1 1 1 0 1 1 Oper. x WR WR RD RD Register selected None Transmitter register Control register Receiver register Status register
Status register
RD
WR
Receiver register
Transmitter Register - Accepts a data byte(from CPU) through the data bus - Transferred to a shift register for serial transmission Receiver - Receives serial information into another shift register - Complete data byte is sent to the receiver register Status Register Bits - Used for I/O flags and for recording errors Control Register Bits - Define baud rate, no. of bits in each character, whether to generate and check parity, and no. of stop bits
16
FIRST-IN-FIRST-OUT(FIFO) BUFFER
* Input data and output data at two different rates * Output data are always in the same order in which the data entered the buffer. * Useful in some applications when data is transferred asynchronously 4 x 4 FIFO Buffer (4 4-bit registers Ri), 4 Control Registers(flip-flops Fi, associated with each Ri)
R1 Data input 4-bit register Clock R2 4-bit register Clock R3 4-bit register Clock R4 4-bit register Clock Data output
Insert
S R Input ready Master clear
F1 F' 1
S R
F2 F'2 F
S R
F3 F' 3
S R
F4 F' 4
Output ready Delete
17
Modes of Transfer
MODES OF TRANSFER - PROGRAM-CONTROLLED I/O 3 different Data Transfer Modes between the central computer(CPU or Memory) and peripherals; Program-Controlled I/O Interrupt-Initiated I/O Direct Memory Access (DMA) Program-Controlled I/O(Input Dev to CPU)
Data bus
Address bus CPU I/O read I/O write Status register F Interface Data register
I/O bus
Data valid Data accepted
I/O device
Read status register Check flag bit =0
flag =1
Polling or Status Checking

Continuous CPU involvement CPU slowed down to I/O speed Simple Least hardware
Read data register Transfer data to memory no
Operation complete? yes Continue with program
18
Modes of Transfer
MODES OF TRANSFER - INTERRUPT INITIATED I/O & DMA

Interrupt Initiated I/O - Polling takes valuable CPU time - Open communication only when some data has to be passed -> Interrupt. - I/O interface, instead of the CPU, monitors the I/O device - When the interface determines that the I/O device is ready for data transfer, it generates an Interrupt Request to the CPU - Upon detecting an interrupt, CPU stops momentarily the task it is doing, branches to the service routine to process the data transfer, and then returns to the task it was performing DMA (Direct Memory Access) - Large blocks of data transferred at a high speed to or from high speed devices, magnetic drums, disks, tapes, etc. - DMA controller Interface that provides I/O transfer of data directly to and from the memory and the I/O device - CPU initializes the DMA controller by sending a memory address and the number of words to be transferred - Actual transfer of data is done directly between the device and memory through DMA controller -> Freeing CPU for other tasks
19
Priority Interrupt
PRIORITY INTERRUPT
Priority - Determines which interrupt is to be served first when two or more requests are made simultaneously - Also determines which interrupts are permitted to interrupt the computer while another is being serviced - Higher priority interrupts can make requests while servicing a lower priority interrupt Priority Interrupt by Software(Polling) - Priority is established by the order of polling the devices(interrupt sources) - Flexible since it is established by software - Low cost since it needs a very little hardware - Very slow Priority Interrupt by Hardware - Require a priority interrupt manager which accepts all the interrupt requests to determine the highest priority request - Fast since identification of the highest priority interrupt request is identified by the hardware - Fast since each interrupt source has its own interrupt vector to access directly to its own service routine
20
Priority Interrupt
HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN VAD 1

Device 1 PI PO
Processor data bus VAD 2 VAD 3

Device 2 PI PO Device 3 PI PO To next device
Interrupt request Interrupt acknowledge
* Serial hardware priority function * Interrupt Request Line - Single common line * Interrupt Acknowledge Line - Daisy-Chain
INT
CPU
INTACK
Interrupt Request from any device(>=1) -> CPU responds by INTACK <- 1 -> Any device receives signal(INTACK) 1 at PI puts the VAD on the bus Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK=1, and it blocks INTACK to propagate to the next device One stage of the daisy chain priority arrangement
PI Interrupt request from device Priority in
S Q
Enable
VAD
Vector address
RF
Priority out
PO
Delay Interrupt request to CPU Computer Organization
PI RF PO Enable 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1
21
Priority Interrupt
PARALLEL PRIORITY INTERRUPT

Interrupt register Disk Printer Reader Keyboard 0 1 2 3 I0 I1 Priority I 2 encoder I3 IEN
Bus Buffer
y x 0 0 0 0 0 0 Enable Interrupt to CPU INTACK from CPU
VAD to CPU
0 Mask register 1 2 3
IST
IEN: Set or Clear by instructions ION or IOF IST: Represents an unmasked interrupt has occurred. INTACK enables tristate Bus Buffer to load VAD generated by the Priority Logic Interrupt Register: - Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level - Each bit can be cleared by a program instruction Mask Register: - Mask Register is associated with Interrupt Register - Each bit can be set or cleared by an Instruction
22
Priority Interrupt
INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt when more than one interrupts take place Priority Encoder Truth table
Inputs I0 1 0 0 0 0 I1 d 1 0 0 0 I2 d d 1 0 0 d d d 1 0 I3 Outputs x 0 0 1 1 d y IST 0 1 0 1 d 1 1 1 1 0 Boolean functions
x = I0' I1' y = I0' I1 + I0I2 (IST) = I0 + I1 + I2 + I3
23
Priority Interrupt
INTERRUPT CYCLE
At the end of each Instruction cycle - CPU checks IEN and IST - If IEN IST = 1, CPU -> Interrupt Cycle SP SP - 1 M[SP] PC INTACK 1 PC VAD IEN 0 Go To Fetch Decrement stack pointer Push PC into stack Enable interrupt acknowledge Transfer vector address to PC Disable further interrupts to execute the first instruction in the interrupt service routine
24
Priority Interrupt
INTERRUPT SERVICE ROUTINE

address
0 1 2 3
Memory
JMP DISK JMP PTR JMP RDR JMP KBD Main program current instr. Stack 256 750 KBD 5 4 DISK PTR 8 RDR 7
I/O service programs Program to service magnetic disk Program to service line printer Program to service character reader Program to service keyboard 255 256 6 9 10
VAD=00000011
KBD interrupt
749 750
11 2
Disk interrupt
Initial and Final Operations Each interrupt service routine must have an initial and final set of operations for controlling the registers in the hardware interrupt system
Initial Sequence [1] Clear lower level Mask reg. bits [2] IST <- 0 [3] Save contents of CPU registers [4] IEN <- 1 [5] Go to Interrupt Service Routine
Final Sequence [1] IEN <- 0 [2] Restore CPU registers [3] Clear the bit in the Interrupt Reg [4] Set lower level Mask reg. bits [5] Restore return address, IEN <- 1
25
Direct Memory Access
DIRECT MEMORY ACCESS

* Block of data transfer from high speed devices, Drum, Disk, Tape * DMA controller - Interface which allows I/O transfer directly between Memory and Device, freeing CPU for other tasks * CPU initializes DMA Controller by sending memory address and the block size(number of words) CPU bus signals for DMA transfer
Bus request Bus granted BR CPU BG ABUS DBUS RD WR Address bus Data bus Read Write
High-impedence (disabled) when BG is enabled
Block diagram of DMA controller

Address bus Data bus Data bus buffers Internal Bus Address bus buffers
DMA select Register select Read Write Bus request Bus grant Interrupt
DS RS RD WR BR BG Interrupt Control logic
Address register Word count register Control register
DMA request DMA acknowledge to I/O device
26
DMA I/O OPERATION

Starting an I/O - CPU executes instruction to Load Memory Address Register Load Word Counter Load Function(Read or Write) to be performed Issue a GO command Upon receiving a GO Command DMA performs I/O operation as follows independently from CPU Input [1] Input Device <- R (Read control signal) [2] Buffer(DMA Controller) <- Input Byte; and assembles the byte into a word until word is full [4] M <- memory address, W(Write control signal) [5] Address Reg <- Address Reg +1; WC(Word Counter) <- WC - 1 [6] If WC = 0, then Interrupt to acknowledge done, else go to [1] Output [1] M <- M Address, R M Address R <- M Address R + 1, WC <- WC - 1 [2] Disassemble the word [3] Buffer <- One byte; Output Device <- W, for all disassembled bytes [4] If WC = 0, then Interrupt to acknowledge done, else go to [1]
27
CYCLE STEALING
While DMA I/O takes place, CPU is also executing instructions
DMA Controller and CPU both access Memory -> Memory Access Conflict Memory Bus Controller
- Coordinating the activities of all devices requesting memory access - Priority System
Memory accesses by CPU and DMA Controller are interwoven, with the top priority given to DMA Controller -> Cycle Stealing Cycle Steal - CPU is usually much faster than I/O(DMA), thus CPU uses the most of the memory cycles - DMA Controller steals the memory cycles from CPU - For those stolen cycles, CPU remains idle - For those slow CPU, DMA Controller may steal most of the memory cycles which may cause CPU remain idle long time
28
DMA TRANSFER
Interrupt
BG BR RD WR Addr Data Read control Write control Data bus Address bus Address select RD DS RS BR BG Interrupt DMA Controller DMA request WR Addr Data DMA ack. I/O Peripheral device RD WR Addr Data CPU Random-access memory unit (RAM)
29
Input/Output Processor
INPUT/OUTPUT PROCESSOR - CHANNEL Channel - Processor with direct memory access capability that communicates with I/O devices - Channel accesses memory by cycle stealing - Channel can execute a Channel Program - Stored in the main memory - Consists of Channel Command Word(CCW) - Each CCW specifies the parameters needed by the channel to control the I/O devices and perform data transfer operations - CPU initiates the channel by executing an channel I/O class instruction and once initiated, channel operates independently of the CPU
Central processing unit (CPU) Peripheral devices PD Input-output processor (IOP) PD PD PD
Memory unit
Memory Bus
I/O bus
30
Input/Output Processor
CHANNEL / CPU COMMUNICATION

CPU operations
Send instruction to test IOP.path
Transfer status word to memory If status OK, then send start I/O instruction to IOP.
IOP operations
Access memory for IOP program
CPU continues with another program
Conduct I/O transfers using DMA; Prepare status report. I/O transfer completed; Interrupt CPU
Request IOP status Transfer status word to memory location
Check status word for correct transfer.
Continue

Co Unit 6

Uploaded by

Copyright:

Co Unit 6

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Co Unit 6

Uploaded by

Copyright:

Input-Output Organization

Computer Architectures Lab

Computer Architectures Lab

I/O BUS AND INTERFACE MODULES

Keyboard and display terminal

Each peripheral has an interface module associated with it

Computer Architectures Lab

CONNECTION OF I/O BUS

CPU I/O bus

Connection of I/O Bus to One Interface

Output peripheral device and controller

Command decoder Status register

Computer Architectures Lab

I/O BUS AND MEMORY BUS

ISOLATED vs MEMORY MAPPED I/O

Computer Architectures Lab

Timing and Control

Asynchronous Data Transfer

ASYNCHRONOUS DATA TRANSFER

Asynchronous Data Transfer

Two Asynchronous Data Transfer Methods

Asynchronous Data Transfer

Source-Initiated Strobe for Data Transfer

Destination-Initiated Strobe for Data Transfer

Computer Architectures Lab

Asynchronous Data Transfer

Computer Architectures Lab

Asynchronous Data Transfer

SOURCE-INITIATED TRANSFER USING HANDSHAKE

Source unit Place data on bus. Enable data valid.

Disable data accepted. Ready to accept data (initial state).

Asynchronous Data Transfer

DESTINATION-INITIATED TRANSFER USING HANDSHAKE

Ready for data

Source unit Place data on bus. Enable data valid.

Destination unit Ready to accept data. Enable ready for data.

Disable data valid. Invalidate data on bus (initial state).

Accept data from bus. Disable ready for data.

Asynchronous Data Transfer

ASYNCHRONOUS SERIAL TRANSFER

Asynchronous Data Transfer

UNIVERSAL ASYNCHRONOUS RECEIVER-TRANSMITTER - UART A typical asynchronous communication interface available as an IC

Chip select Register select I/O read I/O write

CS RS Timing and Control

Asynchronous Data Transfer

S R Input ready Master clear

Output ready Delete

Computer Architectures Lab

Read status register Check flag bit =0

Polling or Status Checking

Read data register Transfer data to memory no

Operation complete? yes Continue with program

Computer Architectures Lab

MODES OF TRANSFER - INTERRUPT INITIATED I/O & DMA

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN VAD 1

Processor data bus VAD 2 VAD 3

Interrupt request Interrupt acknowledge

Delay Interrupt request to CPU Computer Organization

Computer Architectures Lab

PARALLEL PRIORITY INTERRUPT

INTERRUPT PRIORITY ENCODER

x = I0' I1' y = I0' I1 + I0I2 (IST) = I0 + I1 + I2 + I3