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    Simulation and Timing in VHDL: EE 595 EDA / ASIC Design Lab

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    bijoiuu
    This document discusses simulation and timing in VHDL. It describes how VHDL uses a two-list algorithm to track previous and new signal values, allowing it to handle zero-delay events like simultaneous signal assignments. It also discusses the use of "delta time" to model zero-delay event ordering. Finally, it covers the different delay types in VHDL - transport delay, inertial delay, and delta delay - and how they model propagation delays and minimum pulse widths.

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    Simulation and Timing in VHDL: EE 595 EDA / ASIC Design Lab

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    bijoiuu
    49 views15 pages
    This document discusses simulation and timing in VHDL. It describes how VHDL uses a two-list algorithm to track previous and new signal values, allowing it to handle zero-delay events like simultaneous signal assignments. It also discusses the use of "delta time" to model zero-delay event ordering. Finally, it covers the different delay types in VHDL - transport delay, inertial delay, and delta delay - and how they model propagation delays and minimum pulse widths.

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    simulation and timing VHDL

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    lecture 3

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    This document discusses simulation and timing in VHDL. It describes how VHDL uses a two-list algorithm to track previous and new signal values, allowing it to handle zero-delay events like simultaneous signal assignments. It also discusses the use of "delta time" to model zero-delay event ordering. Finally, it covers the different delay types in VHDL - transport delay, inertial delay, and delta delay - and how they model propagation delays and minimum pulse widths.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    49 views15 pages

    Simulation and Timing in VHDL: EE 595 EDA / ASIC Design Lab

    Uploaded by

    bijoiuu
    This document discusses simulation and timing in VHDL. It describes how VHDL uses a two-list algorithm to track previous and new signal values, allowing it to handle zero-delay events like simultaneous signal assignments. It also discusses the use of "delta time" to model zero-delay event ordering. Finally, it covers the different delay types in VHDL - transport delay, inertial delay, and delta delay - and how they model propagation delays and minimum pulse widths.

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    EE 595

    Part III
    Simulation and Timing in
    VHDL
    EE 595 EDA / ASIC Design Lab
    Simulation Cycle in VHDL
    First-Generation simulators used a technique CAD developers call a one-list algorithm,
    which is relatively fast but cannot handle parallel zero delay events such as exchanging
    A and B.
    AA<=
    <=B;
    B; zero
    zerodelay
    delay
    BB<=
    <=A;
    A; zero
    zerodelay
    delay

    This example would not exchange the values of A and B, but would give both A and B the
    old value of B, using one-list algorithm.

    VHDL uses a two-list algorithm, which tracks the previous and new values of signals. In
    this method, expressions are first evaluated, then signals are assigned new values. In
    VHDL, the example code performs a data exchange between the two signals A and B at
    some point in simulation time. In operation, the old values of A and B are fetched and
    scheduled for assignment, for zero delay, after a subsequent WAIT statement is executed.

    EE 595 EDA / ASIC Design Lab


    Simulation Cycle in VHDL
    (cont’d)
    The ordering of zero delay events is handled with a fictitious unit called
    delta time. Delta time represents the execution of a simulation cycle without
    advancing Simulation time.

    Process Execution Time


    Signal Assignments
    Signal Evaluations

    Enter Begin Middle End Leave

    All right-hand side assignments (evaluations) are calculated after assignments


    are made.
    EE 595 EDA / ASIC Design Lab
    Simulation Cycle in VHDL
    (cont’d)
    „ The key points of simulation and delta time
    are:
    „ The simulator models zero-delay events using
    delta time.
    „ Events scheduled at the same time are simulated
    in specific order during a delta time step.
    „ Related logic is then re-simulated to propagate the
    effects for another delta time time step.
    „ Delta time steps continue until there is no activity
    for the same instant of simulated time.

    EE 595 EDA / ASIC Design Lab


    Timing Model of VHDL
    Simulation Cycle
    „ VHDL uses a simulation cycle to model the stimulus and
    response nature of digital hardware

    Start
    StartSimulation
    Simulation
    Delay

    Update
    UpdateSignals
    Signals Execute
    ExecuteProcesses
    Processes

    End
    EndSimulation
    Simulation

    EE 595 EDA / ASIC Design Lab


    Delay Types
    „ All VHDL signal assignment statements prescribe an
    amount of time that must transpire before the signal
    assumes its new value

    „ This prescribed delay can be in one of three forms:


    „ Transport -- prescribes propagation delay only
    „ Inertial -- prescribes minimum input pulse width and
    propagation delay
    „ Delta -- the default, if no delay time is explicitly specified

    EE 595 EDA / ASIC Design Lab


    Transport Delay
    „ Delay must be explicitly specified by user
    „ Keyword “TRANSPORT” must be used
    „ Signal will assume its new value after specified delay
    ----TRANSPORT
    TRANSPORTmust
    mustbe
    bespecified
    specified
    Output
    Output<=
    <=TRANSPORT
    TRANSPORTNOTNOT(Input)
    (Input)AFTER
    AFTER10
    10ns;
    ns;
    Input Output

    Input

    Output

    EE 595 EDA / ASIC Design Lab


    Inertial Delay
    „ Provides for specification of input pulse width, i.e. ‘inertia’ of output, and
    propagation delay :
    target
    target<=
    <=[REJECT
    [REJECTtime_expression]
    time_expression]INERTIAL
    INERTIALwaveform;
    waveform;

    „ Inertial delay is default and REJECT is optional :


    Output
    Output<=
    <=not(Input)
    not(Input)after
    after10
    10ns;
    ns;
    ----Propagation
    Propagationdelay
    delayand
    andminimum
    minimumpulse
    pulsewidth
    widthare
    are10ns
    10ns

    Input Output Input

    Output

    EE 595 EDA / ASIC Design Lab


    Inertial Delay (cont’d)
    „ Example of gate with ‘inertia’ smaller than propagation delay
    „ e.g. Inverter with propagation delay of 10ns which suppresses
    pulses shorter than 5ns

    Output
    Output<=
    <= REJECT
    REJECT5ns
    5nsINERTIAL
    INERTIALnot(Input)
    not(Input)after
    after10ns;
    10ns;

    Input

    Output

    0 5 10 15 20 25 30 35
    „ Note that REJECT feature is new to VHDL 1076-1993

    EE 595 EDA / ASIC Design Lab


    Delta Delay
    „ Default signal assignment propagation delay if no delay is
    explicitly prescribed
    „ VHDL signals assignment cannot take place immediately
    „ Delta is an infinitesimal VHDL time unit so that all signal
    assignments can result in signals assuming their values at some
    future time
    „ E.g.

    Output
    Output<=
    <=not(Input);
    not(Input);
    ----Output
    Outputassumes
    assumesnew
    newvalue
    valueininone
    onedelta
    deltacycle
    cycle

    „ Supports a model of concurrent VHDL process execution


    „ The order in which processes are executed by simulator does not
    affect simulation output

    EE 595 EDA / ASIC Design Lab


    Delta Delay
    An Example Without Delta Delay
    „ What is the behavior of C?

    IN: 1->0 C
    A

    AND
    ANDgate
    gateevaluated
    evaluatedfirst:
    first:
    NAND
    NANDgate
    gateevaluated
    evaluatedfirst:
    first: IN:
    IN:1->0
    1->0
    IN:
    IN:1->0
    1->0 A:A: 0->1
    0->1
    A:
    A: 0->1
    0->1 C:C: 0->1
    0->1
    B:
    B: 1->0
    1->0 B:B: 1->0
    1->0
    C:
    C: 0->0
    0->0 C:C: 1->0
    1->0

    EE 595 EDA / ASIC Design Lab


    Delta Delay
    An Example With Delta Delay
    „ What is the behavior of C?
    IN: 1->0 A C

    Using
    Usingdelta
    deltadelay
    delayschedulingA
    scheduling B
    Time Delta Event
    0 ns 1 IN: 1->0
    eval INVERTER
    2 A: 0->1
    eval NAND, AND
    3 B: 1->0
    C: 0->1
    eval AND
    4 C: 1->0
    1 ns

    EE 595 EDA / ASIC Design Lab


    Transport Versus Inertial Delay
    „ Inertial Delay
    „ Default in VHDL
    „ Can be similar to actual device behavior
    „ Spikes are “swallowed”
    „ Most commonly used in simulator

    „ Transport Delay
    „ Must specify with key word TRANSPORT
    „ Ideal delay., passes any width pulse
    „ Good for wire delay and time modeling.

    EE 595 EDA / ASIC Design Lab


    Delta Time
    „ Delta Time is a simulation time cycle It is used to order
    sequential events during simulation. More than one event can
    occur during a delta time.
    „ The time between any two sequential events is called a delta.
    These two events may be happening at the same real time but
    in a specific order, or they may be separated by a large real time
    during which time the circuit has been “quiet”
    „ A delta is the default value or if zero delay is specified as in
    A <= not B; These are the same
    A <= not B after 0 ns;

    EE 595 EDA / ASIC Design Lab


    Relation Between Delta Delay
    and Real Time
    „ A combinational Circuit, in which all elements have zero delay, would
    settle down in 0 ns, but could occupy many deltas.
    Deltas 16
    15
    14 Relationship of
    4 13 20 deltas and real time
    3 9 12 19
    2 6 8 11 18
    1 5 7 10 17

    Time
    0 ns 10 ns 18 ns 24 ns 40 ns

    EE 595 EDA / ASIC Design Lab

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