Society of St.

Francis Xavier, Pilar’s

Fr. Conceicao Rodrigues College of Engineering
Fr. Agnel Technical Education Complex Bandstand
Bandra (West) Mumbai -400 050

Module Unit
Topics Ref. Hrs.
No. No.
3 Design abstractions and Modeling Styles 1,2 4
3.1 Design Abstractions, Behavioral, Data flow, Gate level and Switch level modelling
3.2 Procedural Assignment and Continuous Assignment

Dr. Surendra Singh Rathod

Principal, Fr. Conceicao Rodrigues College of Engineering
principal.crce@fragnel.edu.in

1 Moulding Engineers Who Can Build the Nation

2
 LEVELS OF ABSTRACTION

• Verilog is both, behavioral and structural language. Designs in Verilog can be

described at all the four levels of abstraction depending on the needs of design.

• Behavioral Level : Used to model behavior of design without concern for the
hardware implementation details. Designing at this level is very similar to C
programming.
• Dataflow Level [ RTL ] : Module is specified by specifying the data flow. The designer
is aware of how the data flows between registers.
• Gate Level : Module is implemented in terms of logic gates & interconnections
between these gates. Design at this level is similar to describing design in terms of
gate level logical diagram.
• Switch Level : Lowest level of abstraction provided by verilog. Module can be
implemented in terms of switches, storage nodes & interconnection between them.
3 Moulding Engineers Who Can Build the Nation

• Verilog designs can mix several levels of abstraction.

• Register Transfer Level ( RTL ) uses combination of behavioral & data flow constructs.

Switch Level
(synthesis only)
Custom ASIC
Gate Level
(synthesis only) Technology
Technology ASIC/PLD Independent
RTL Level
Specific
(synthesis only)
ASIC/PLD
Behavioral Level
ASIC/PLD

Intense Level Of Abstraction Very

Definition Abstract

4 Moulding Engineers Who Can Build the Nation

 HALF ADDER
BEHAVIORAL LEVEL DATA FLOW LEVEL GATE LEVEL

//Behavioral level // Data flow level //Gate Level

module HalfAdd(sum,carry,A,B); module Half_Adder(sum,carry,A,B); module HalfAdd(sum,carry,A,B);
//outputs //outputs //outputs//Outputs
output sum; reg sum; output sum; reg sum; output sum; reg sum;
output carry; reg carry; output carry; reg carry; output carry; reg carry;
//inputs //inputs
//inputs
input A,B; input A,B;
input A,B;
//calculate sum & carry //Instantiate logic gates//gates
always @ ( A or B) //continuous assignments
xor my_xor(sum,A,B);
begin assign sum = (~A&B) + (A&~B); and my_and(carry,A,B);
{carry , sum } = A + B; assign carry = A&B;
end endmodule endmodule
endmodule

5 Moulding Engineers Who Can Build the Nation

One language, Many Coding Style

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 Dataflow style: Verilog Code

One language, Many Coding Style

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 Behavioral style: Verilog Code

Structural style: Verilog Code

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 DATA FLOW MODELING
— Continuous Assignment
— Delayed Continuous Assignment

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CONTINUOUS ASSIGNMENT
— A continuous assignment is the most basic statement in DATA FLOW modeling.

input A,B,C;
output Y.
assign Y = ~ (( A & B ) | C)

— Continuous assignment, models a combinational hardware driving values onto a net.

[ Infers a Driver]

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 CONTINUOUS ASSIGNMENT
Continuous assignment characteristics :
— Identifier being assigned must be of type wire.
— Assignments can be scalar or vector.
— Values being Read [ on RHS ] can be registers or nets.
— Continuous assignment can be done,
— Implicitly, i.e value is assigned, while the wire is being declared
— Explicitly, i.e . By having the declaration and assignment statements separate.

Explicit Usage Implicit Usage

input A,B; input A,B;
output C; output C;
assign C = A & B; wire C = A & B;

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Assign
• The “assign” technique is called a “continuous assignment.”
• Assign can be used only on wire types
• Continuous assignment
—Left operand continuously gets a new value
• E.g.
—assign c = a & b;

• Only one assign can drive a single variable

• Multiple assigns operate parallel to each other
• Can be used to describe combinatorial logic

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 Two-input NAND gate based on assign keyword
module example(c, a, b);
input a, b; a
output c; c
b
// Functionality
assign c = ~(a & b);
endmodule

If there are several continuous assignments, the order does not matter, they are
executed concurrently.
Example: assign c=~(a&b);
assign d=a^b;
The code has to be modified accordingly adding the signal “d” as an output.
Signals a, b, c are wires by default, we do not have to declare them in this example.

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DELAYED CONTINUOUS ASSIGNMENT

— Delayed Continuous Assignment, models inertial delay of gate.
— Delayed values can be specified to control the time when a net is assigned
the evaluated value.
— Thus useful in modeling timing behavior in real circuits.

— The delay in continuous assignment statement can be specified as

— Regular assignment delay
— Implicit continuous assignment delay.
— Net declaration delay.
A delay can be specified on a net when it is declared without putting a
continuous assignment on the net.
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 DELAYED CONTINUOUS ASSIGNMENT

Regular assignment delay Implicit assignment delay

input A, B; input A, B;
output C; output C;
assign #10 C = A & B; wire #10 C = A & B;

Net declaration delay

input A,B;
output C;
wire #10 C;
assign C = A & B

— All three statements produces the same result

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Example: Full Adder

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 BEHAVIORAL MODELING

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BEHAVIORAL MODELING

— BEHAVIORAL MODELING FEATURES

— PROCEDURAL ASSIGNMENT
— TIMING CONTROL
— CONDITIONAL STATEMENTS
— MULTIWAY BRANCHING ( LOOP STATEMENTS )
— PROCEDURAL CONTINUOUS ASSIGNMENT

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 BEHAVIORAL MODELING FEATURES
— Describes the functionality in an algorithmic manner.
— Code independent of vendor technology.
— But difficult to visualize the actual hardware.
— Logic structure implementation left to the synthesis tool.

21

BEHAVIORAL MODELING
Ø In Verilog the behavioral representation is described using two procedural blocks :
Ø initial block : Executes at beginning of simulation (time 0 ) only once & then is
suspended forever.
Ø always block : Starts at time 0. All the statements are executed in an infinite loop as
long as simulation is performed.
Note: Procedural Blocks are the sequential region of a verilog module
reg clock; always @ (....)
initial begin Sensitivity list

clock = 1’b0;
always
#10 clock = ~ clock; end
initial
• A variable should be written only in one always block
#1000 $finish;
• The sensitivity list cannot contain the outputs (left-side
As shown clock initialization is done in variables) of the always block
Separate initial block. $finish is used to • Assign cannot be used within an always block
22 stop simulation at 1000 time units. • Multiple always blocks are executed in parallel
 BEHAVIORAL MODELING
— Always blocks are used to model synchronous & combinational Logic.
- Sensitivity list provides event control for always block.
- All signals feeding into [being read] the always block must be listed in the sensitivity List.

input d, clk;
output q;
reg q;
always @ (posedge clk)
begin
q = d;
end

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Two-Input NAND gate based on the always keyword

• All inputs used in the procedure must appear in the
sensitivity list (event/trigger list).
• The “always” keyword means that the circuit always
module example2 (a,b,c);
(continuously) watches the signals in the input list (the
// Port modes @ (a or b) part) and responds to changes in those
input a,b; signals by immediately updating the output. This is
output c; procedural assignment.
// Registered identifiers • Combinational circuit outputs must also be declared as
reg c; registered identifiers when the “always” method
Sensitivity list
(“procedural assignment”) is used. In Verilog code
reg variables can be used to model either
// Functionality combinational or sequential parts of the circuit.
always @ (a or b) a
c = ~(a & b); c
b • The ‘=‘ blocking assignment was used in this example
endmodule (inside the always block).
• Verilog compiler evaluates the statements in an always
block in the order in which they are written i.e. in
sequential order. If a variable is given a value by a
blocking assignment, then this new value is used in
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evaluating all subsequent statements in the block .
 BEHAVIORAL MODELING
• INITIAL BLOCKS are used for initialization of variables ( registers ) at beginning of simulation.
• ALWAYS BLOCKS represent the behavior of digital circuits as long as they are powered

— Procedural block updates value of REGISTER ( REG ) only.

i.e all signals being assigned in the always block have to be re-declared as type reg.
— Each procedural block may have
— Procedural assignment
— Programming statements
— Timing controls (Delayed assignment)
— All procedural blocks in a module execute concurrently.

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BEHAVIORAL MODELING
reg x, y; — Statements in procedural blocks
initial can be grouped to execute either
begin sequentially or parallel.
x = 1’b0; // executes at time = 0 1. Sequential block :
y = 1’b1; // executes at time = 0 — Statements are enclosed within
#10 x= 1’b1; // executes at time = 10 the keywords begin & end.
— Statements are processed in
#15 y = 1’b0; // executes at time = 25 the order they are specified.
#10 x = 1’b0; // executes at time = 35 — Delays specified are additive.
end

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 BEHAVIORAL MODELING
reg x,y; 2. Parallel block :
initial — Statements are enclosed within the
fork
keyword fork and join
x= 1’b0;
y= 1’b1; — All the statements are executed
#10 x= 1’b1; //executes at time = 10. concurrently. Order in which
#20 y= 1’b0; //executes at time = 20. statements are written is not
#20 x= 1’b0; //executes at time = 20. important.
#40 y= 1’b1; //executes at time = 40. — If the delay is specified, it is relative
join to the time the block was entered.
fork- join not supported for synthesis !!

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initial block in Verilog Multiple initial blocks

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 always block in Verilog Always block with a sensitivity list
Clock Generator

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Example: Sequential blocks and Parallel blocks

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 Named block example: Disable named block example:

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PROCEDURAL ASSIGNMENT
— There are two kinds of procedural assignments
— Blocking assignment
— Specified by the operator =
— All the statements within the sequential block are executed sequentially.
— Blocks the execution of operations after it till it is executed -» sequential
operation (don't use it unless really necessary)
— Non blocking assignment
— Specified by the operator <=
— All the statements within the sequential block are executed concurrently
…hardware-like operation
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 BLOCKING ASSIGNMENT
— Blocks the subsequent assignments in the same always block from
occurring until after the current assignment has completed.
reg x, y, z;
always @ (posedge clk) integer a, b;
begin initial
word [15:8] = word [7:0]; begin
word [7:0] = word[15:8]; x = 0; y = 1; //executed at time = 0
end #15 a = 22; //executed at time = 15
#10 b= 33; //executed at time = 15 +10 = 25
end
Dose this perform
a swap ? Similar to Variables hence update immediately.

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Blocking Assignments

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 RACE AROUND CONDITION !!
— When blocking assignments in two or more always blocks are scheduled to execute
in the same time step, the order of execution is indeterminate & can cause a race
around condition
always @ (posedge clk)
a = b;

always @ (posedge clk)

b = c;
Race around condition
whether a =b or a = c ??

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Race around condition: A problem with blocking assignment

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 NON BLOCKING ASSIGNMENT
— All the statements within the sequential block are executed concurrently.
reg x, y, z;
integer a, b; always @ (posedge clk)
begin
initial
word[15:8]<=word[7:0];
begin
word[7:0] <=word[15:8];
x = 0; y = 1; //executed at time = 0
end
a <= #15 22; //executed at time = 15
b <= #10 33; //executed at time = 10; does not wait for above statement
end

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NON BLOCKING ASSIGNMENT

— Used whenever several register assignments are made in the same time step
without regard to order or dependence of assignment statements

always @ (posedge clk)

a <= b;
b <= c;
Race solved !!

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39

Two-input NAND and Exclusive OR using non-blocking assignments

• Enclose multiple output signal assignments inside a “begin” -
“end” block;
module example(a,b,c,d);
• The “<=“ non-blocking assignment was used in this example.
// Port modes
input a, b; • Inside an always block, non-blocking and blocking assignments
output c; cannot be mixed.
output d; • All non-blocking assignments are evaluated using the values
that the variables have when the always block is entered.
// Registered identifiers Thus a given variable has the same value for all the
reg c,d; statements in the block. The meaning of non-blocking is that
the result of each assignment is not seen until the end of an
// Functionality always block. All non-blocking assignments are evaluated in
always @ (a or b) parallel.
begin Example :
c <= ~(a & b); always @(a or b or c)
d <= a ^ b; b<= a
a
end c if (b) // “b” will be the old “b”
b
endmodule • When there are multiple assignments to the same variable
d
inside an always block, the result of the last assignment is
maintained.
• Blocking assignments are recommended for combinational
circuits.
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 Two-input MUX
module Mux2 (A, B, Sel, Y); 2-to-1 MUX: an alternate method

input A, B, Sel; module Mux2(A, B, Sel, Y);

output Y; B
reg Y; SEL input A, B, Sel;
Y
output Y;
always @ (A or B or Sel) reg Y;
if (Sel==0)
A
Y = A; always @ (A or B or Sel)
else Y = (Sel) ? B : A;
Y = B; endmodule
endmodule

• Use “if-else” to connect output “Y” to Here the conditional (ternary) operator is used.
one of the two data inputs based on the Read statement like this: “Is the control signal
value of the data selector “Sel”. ‘Sel’ equal to 1? If yes, Y is assigned the value B
• The expression inside the parentheses else A.”
after “if” must evaluate to either “1”
(true) or “0” (false).

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always Flip Flop

• Flip Flop: edge sensitive storage element
always @ (posedge clk)
c <= a & b,
D[0] Q[0]

• Synchronous reset
always @ (posedge clk)
if (rst)
D[0] Q[0]
c <= 1’b0,
else
c <= a & b,

• Asynchronous reset
always @ (posedge clk, posedge rst)
if (rst)
c <= 1’b0,
else
42 c <= a & b,
 Blocking & Non-Blocking – Hardware inferred

always @ (posedge CLK)

begin
M = A & B;
Y = M | C;
end

always @ (posedge CLK)

begin
M <= A & B;
Y <= M | C;
end

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D flip-flop, positive-edge triggered

§The sensitivity list contains only the signal that is
module D_FF (D, Clock, Q); responsible for triggering the flip flop, i.e., the ‘Clock’ signal;
input D, Clock; It is possible to specify that the response should take place
output Q;
only at a particular edge of the signal, using the keywords
reg Q; “posedge” and “negedge”.
always @ (posedge Clock)
Q <= D; §The keyword “….edge” specifies that a change may occur
only on the edge of the Clock. At this time the output Q is set
endmodule
to the value of input D. Since Q is reg type it will maintain
the value between the edges of the clock.
1 D
0
Q §Other inputs such as ‘D’ may be used inside the ‘always’
D Q
20,20 block, but they must not appear in the sensitivity list.
CLK
C
§ Use non-blocking assignments to describe sequential
circuits.

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 D flip-flop, positive-edge triggered, with Q_bar
•In this example the ‘assign’ statement is used.
module D_FF (D, Clock, Q); •The ‘always’ block implements most of the desired behavior,
input D, Clock;
output Q; namely, a single-bit storage device with appropriate behavior
reg Q;
and clocking.
wire Q_bar;
•The ‘assign’ statement simply copies the Q signal to an
assign Q_bar = ~Q; additional output while performing the necessary inversion
always @ (posedge Clock)
Q <= D; along the way.
endmodule
•A variable on the left side of the equal sign must not be in the
trigger list or the machine may go into an infinite loop.
always@(state or A or B or C….)
begin
A<=B+C; //A will immediately retrigger the always procedure

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D flip-flop, positive-edge triggered, with inverted and non-

inverted outputs, and asynchronous reset (active high)
•“Asynchronous Reset” means that asserting
module D_FF (D, Clock, Q, Q_bar, Reset);
input D, Clock, Reset;
the reset will instantly set the Q output to zero,
output Q, Q_bar; regardless of the activity of D or Clock. Q will
reg Q; remain zero as long as Reset is asserted.
always @ (posedge Clock or posedge Reset)
if (Reset == 1) •The ‘always’ block needs to be “triggered”
Q <= 0;
else
either by the Clock or the Reset, so the Reset
Q <= D; signal is added to the sensitivity list. Note that
the sensitivity list specifies the posedge or
assign Q_bar = ~Q;
endmodule negedge of reset as an event trigger along with
the positive edge of the clock.

•We cannot omit the keyword “....edge”

because the sensitivity list cannot have both
46 edge triggered and level sensitivity signals
 D flip-flop, positive-edge triggered, and asynchronous
preset, active low
module D_FF (D,Clock,Q,_Preset); “Asynchronous preset” behaves similar to
input D, Clock, _Preset;
output Q; “reset”, except that the Q output is set to 1
instead of 0.
reg Q;

always @ (posedge Clock or negedge _Preset) Avoid the temptation to design arbitrary
if (_Preset == 0) flip-flop behavior, e.g., ability to trigger on
Q <= 1;
else both edges of the same clock, ability to
Q <= D; trigger on multiple clock signals, etc. The
endmodule
hardware synthesis tool does not
“magically” create new hardware from thin
air! You have to write circuit descriptions
that are physically possible, that is, can be
mapped onto existing (known) hardware
47
elements such as standard D flip-flops.

D flip-flop, positive-edge triggered, with synchronous reset

(active low)
module D_FF (D, Clock, Q, Reset); “Synchronous reset” means that the reset action does
input D, Clock, Reset;
output Q; not occur until the next clock edge. Reset’ does not
reg Q; appear in the input list now, but it appears inside the
always @ (posedge Clock) ‘always’ block.
if (Reset==0)
Q <=0;
else Another way to write the code:
Q<= D;
Q <= (!Reset)? 0 : D;
endmodule

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 Non Blocking Procedural assignments

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How race around condition is resolved in a nonblocking assignment?

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 TIMING CONTROLS
— Timing controls are associated with procedural assignment.
i.e. They are to be used in Procedural Blocks only.

— They specify the simulation time at which statements will execute.

— There are two types of timing controls,

— Delay control
— Event control

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DELAY CONTROL
REGULAR DELAY CONTROL :
— It is of the form
#delay procedural_statement.
— It means “wait for delay” before executing the statement.

initial parameter on_delay = 5;

begin parameter off_delay = 10;
#3 data = 4’b0111; always
#7 data = 4’b1101; begin
#7 data = 4’b0000; #on- delay clk = 0;
end #off_delay clk = 1;
end

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 DELAY CONTROL
— INTRA ASSIGNMENT DELAY CONTROL :
A delay appearing on the R.H.S of an assignment operator.
— Simulates Transport Delay.
initial
begin Takes value of x & y at time 0, evaluates x+y
x = 0, y = 1 & assigns this value after 5 time units.
z = #5 x+y;
end

Ø Intra-assignment computes R.H.S of expression at current time &

performs assignment to the L.H.S after specified delay.

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EVENT CONTROL
@<posedge,negedge><signal>
— Symbol @ is used to specify an event control.
posedge 1 negedge — Execution is delayed until the transition occurs
on the signal
0

Ø There are four types of event based timing control

Ø Regular event control
Ø Event OR control

Ø Named event control

Ø Level-sensitive control

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 REGULAR EVENT CONTROL
input d,clk; input x,y,z;
output q; output q;
reg q; reg q;
always @ (posedge clk) always @ ( x or y or z )
begin begin
q = d; q = x ^ y ^z;
end end

Infers Synchronous logic since Infers Combinational logic since edge

edge is specified is not specified.

— All the signals feeding into the always block must be listed in the sensitivity list.

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EVENT OR CONTROL
— Events can also be Or’ed to indicate “ if any of the events occur” then procedural block
will be executed.

input d, clk, clr;

output q ; Models a +ve edge triggered FF with
reg q ; asynchronous clear.
always @(posedge clk or posedge clr)
begin Note : The inference of both Edge Sensitive and
if (clr) Level Sensitive Logic.
q = 1’b0 ;
else
q=d;
end

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 NAMED EVENT CONTROL
— Verilog provides capability to declare an event, then trigger & then recognize the
occurrence of that event.
— Named event is declared by keyword event.
— Symbol –> is use to trigger the event

event received_data // define an event called received data

always @ (posedge clock )
begin
if ( last_packet) –> received-data
end

always @ (received-data)
data-buf = { data_pkt[0], data_pkt[1], data_pkt[2]}
//when there is event on received data, packets of received data are stored in data buffer.

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LEVEL SENSITIVE CONTROL

— Provides Level Sensitive Timing Control.
syntax : wait ( condition )
procedural-statements;
— Procedural statements executes only if the condition is true else waits until condition
becomes TRUE [i.e. Logic-1].
Note the missing sensitivity list.
always
wait (count_enable)
#20 count = count + 1;
— Count will be incremented only when count enable is high.

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 Regular event control

59

Event OR control

60
 Named event control

61

Level sensitive timing control

62
 CONDITIONAL STATEMENTS – if
if (condition 1) always @ (a or b )
procedural-statement 1 begin
if (a==1’b1)
else if (condition 2)
q = r;
procedural-statement 2 else if (b==1’b1)
else q = s;
procedural-statement 3 else
end q = t;
end

Will infer a Prioritised Multiplexer.

63

if statement in Verilog

64
 CONDITIONAL STATEMENT - case
— Case statement does an identity comparison (including x & z).
— Expression is compared with each case alternative beginning with first & only
the first match is executed.
— If no match is found default clause is executed.

syntax : always@(a or b or c or d or sel)

case ( expression ) begin
alternative1 : statement1; case (sel)
alternative2 : statement2; a
2'b00 : q=a;
alternative3 : statement3; b
2'b01 : q=b; q
c
.
2'b10 : q=c; d
default : default statement;
endcase 2'b11 : q=d; sel
endcase
65
end

CONDITIONAL STATEMENT - case

if (op = ADD) case ( OP )
ACC = ACC + D; ADD : ACC + D;
else if ( op = LDA ) LDA : begin
begin ACC = MEM [ ADDR ];
ACC = MEM [ ADDR ]; end
end JMP : PC = ADDR;
endcase
else if ( OP = JMP)
PC = ADDR;

— When the same input is checked under each conditions case is an simpler
alternative to an if.
— Note: Case statement inVerilog also generates a Prioritised hardware

66
 DEFAULT IN A case
— Output must be explicitly or implicitly defined for all possible
values of the case expression to avoid inferring of latches.
— Default output can be described
— Before the case statement with a variable assignment
— In case statement with a default clause.
always@(a or b or d or sel) always@(a or b or d or sel)
begin begin
q=1'b0; case (sel)
case (sel) 2'b00 : q=a;
2'b00 : q=a; 2'b01 : q=b;
2'b01 : q=b; 2'b11 : q=d;
2'b11 : q=d; default : q=1'b0;
endcase endcase
end end
67

CASE VARIATION - casex, casez

— casex : Special version of case in which z or x or ? always @ (a or b or c or d or e or f)
logic values in the case item or case expression begin
are considered to be don’t cares. {x,y,z} = 3’b000;
casex ({a,b,c,d,e,f})
— casez : Special version of case in which z or ? 6’b 11xxxx: z = 1;
values in the case item are treated as don’t cares. 6’b xx11xx: y = 1;
— A priority mux is built if cases are not mutually 6’b xxxx11: z = 1;
endcase
exclusive.
— Generates a priority encoded logic
— Application of casex, casez –
— Let a 8 bit instruction decoder specifies the
operation to be performed for a
microprocessor
68
 HANDLING DON’T CARES IN
casex, casez
OP-CODE OPERATION
always @ (fetch complete)
casez ( IW )
I7 I6 I5 I4 I3 I2 I1 I0 no operation
8’b000?????;
0 0 0 NOT DEFINED 8’b0010????: acc = acc + IW [3:0]
8’b0101????: acc = {acc[3:0] , acc[7:4]}
I7 I6 I5 I4 I3 I2 I1 I0 Add Instruction
Word nibble to
default
0 0 1 0 DATA accumulator begin
$ display (“UNKNOWN IW”); $ stop;
Swap end
I7 I6 I5 I4 I3 I2 I1 I0 accumulator
0 1 0 1 NOT DEFINED Nibbles.
endcase

69

Case statement in Verilog

70
 4:1 Mux Verilog implementation

71

Ambiguous inputs to the case statement casez statement example

72
 casex statement example

73

LOOP STATEMENTS – for

Syntax for ( initial assignment; expression; step assignment )
begin
procedural assignment
end
Ø Useful when the range of iterations is known.
Ø initial assignment – specifies initial value of loop index.
Ø expression – specifies the condition when loop execution must stop.
Ø step assignment – changes the value of loop index.

parameter index = 3’b111

for (I= 0; I <= index; I = I + 1)
if (data[ I ] = 1’b1)
count = count + 1;

74
 For loop

75

LOOP STATEMENTS – while

— Procedural statements are continuously executed as long as expression evaluates true.

Syntax: while ( condition )

procedural assignment
while (count < 1024)
@ (posedge clk)
if (! fifo-full)
begin
#5 add_to_fifo // task to add data to fifo
count = count + 1;
end
76
 While loop

77

LOOP STATEMENTS – forever

— Continuously executes the procedural statements
— Hence some form of timing control must be used, to get out of the loop.

Syntax: forever
procedural assignment

// generates free running clock

initial
begin
clock = 0;
forever #50 clock = ~clock
end
78
 Example of always block:
Forever loop Both always and forever block the same effect. The always block is a
procedural block and it can not be placed inside other procedural blocks.

A always block inside another procedural block

A compilation error is expected when always

block is used inside another procedural block
i.e. initial begin .. end block. In such a case, a
forever block can be used.

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LOOP STATEMENTS – repeat

— Executes the loop for fixed number of times.
— If the loop count expression is an x or a z, loop count is treated as 0.

Syntax: repeat (loop count)

procedural assignment
repeat ( 128 ) // repeat the following block 128 times
begin
$display (“count = %d\n”, count);
end

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 Repeat loop

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PROCEDURAL CONTINUOUS ASSIGNMENT

— Procedural continuous assignment can appear within an always
statement or initial statement.
— It allows values of expressions to be driven continuously onto
registers or nets for limited period.
— Two types of procedural continuous assignments
— assign & deassign : Assignment within these keywords assigns value only to register.
— force & release : Assignment within these keywords assigns values to both registers
and nets.

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 assign and deassign
always @ ( negedge clk )
begin
ØWhen reset goes high procedural continuous assignment
q = d; overrides the effect of regular procedural assignment.
qb = ~d;
always @ ( reset ) ØThe register variable retains the continuously assigned
if (reset) value after the deassign until they are changed by future
begin
assign q = 1’b0;
procedural assignment.
assign qb = 1’b1;
end Application: Using this a single always can be written to
else initialize a system on RESET, instead of having if rst =1’b1
begin kind of statement in every always block.
deassign q;
deassign qb;
end

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force and release on registers

— Used for simulation and debugging, are not synthesizable.

u1 dff(q,qb,d,clk,reset);
initial
begin
#50 force dff.q = 1’b1;
#50 release dff.q;
end
— These statements force a Logic 1 on ‘q’ between time 50 & 100.
— The value in register q will remain ‘1’ after release but can be changed by
future procedural assignment
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 force and release on nets

— Forced value on net overrides any continuous assignments until the net is released.

assign y = a & b ^ c; // continuous assignment on net y.

initial
# 50 force out = a | b & c;
# 50 release y;
end
— Between time 50 to 100: expression a | b & c will be evaluated and assigned to y.
— At all other times: expression a & b ^ c will be assigned to y.

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assign and deassign force and release

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 STRUCTURAL MODELING

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STRUCTURAL MODELING FEATURES

Structure can be described in Verilog using:
— Module instantiation ( to create hierarchy )

— Built in gate primitives ( gate level modeling )

— Gate Delays

— Switch-level primitives ( at transistor-level )

— User Defined primitives

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 MODULE INSTANTIATION
— Instantiation is a way to include sub designs in a top level module.

— Sub design is invoked by it’s module name.

module mymod(y, a, b);

— Module instantiation may be
— Named instantiation //Lets instantiate the module
mymod mm1(y1, a1, b1); // Connect-by-position
— Positional instantiation
mymod mm2(.a(a2), .b(b2), .y(c2)); // Connect-by-name

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MODULE INSTANTIATION
—Named instantiation - Syntax
<module name> <instance name>(.<port1>(signal1),.<port2>(signal2));
eg: and1 u1 ( .a( in1),.b( in2),.y(out1) );
—Positional instantiation - Syntax
<module name> <instance name>(<signal1>,<signal2>);
eg: and1 u1 (in1,in2,out1);
— Unconnected signals are designated by two comma’s with no signal listed.

In both examples a two input AND gate is instantiated with input ports a, b
(connected to in1, in2) & output port y (connected to out1).

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 MODULE INSTANTIATION
— module add4 is a 4 bit full adder designed by instantiating a single bit full adder.
module add4 (result, carry, r1, r2, ci);
output [3:0] result;
output carry;
input [3:0] r1,r2;
input ci;
wire [3:0] r1,r2,result;
wire ci,carry,c1,c2,c3;
addbit u1 (r1[0], r2[0], ci, result[0], c1);
addbit u2 (r1[1], r2[1], c1, result[1], c2);
addbit u3 (r1[2], r2[2], c2, result[2], c3);
addbit u4 (r1[3], r2[3], c3, result[3], carry);
endmodule

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GATE LEVEL MODELING

— Verilog supports basic logic gates as built-in primitives.
— Since they are predefined, they do not need module definition.
— Primitives available in Verilog

i. Multiple input gates : and, nand, or, nor, xor, xnor

ii. Multiple output gates : buf, not

iii. Tristate gates : bufif0, bufif1, notif0, notif1

iv. Pull gates : pullup, pulldown

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 MULTIPLE INPUT GATES
nand U1 ( y, a, b); xor U2 (z,a,b,c,d);
// instantiates two input nand //instantiates 4-input gate
gate with instance name U1 with instance name U2

— Truth tables for these gates define how outputs for the gates are computed from inputs

nand 0 1 x z
0 1 1 1 1
1 1 0 x x
x 1 x x x
z 1 x x x
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MULTIPLE OUTPUT GATES

— These gates have only one input & one or more outputs.

buf B1 ( WR1, WR2, WR3, WR ); //instantiates buffer with three outputs

buf 0 1 x z
output 0 1 x x

— Useful to increase Fanout of Signals.

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 TRISTATE GATES
— tri-state gates are used when multiple drivers drive the signal.

bufif0 ( active low control ) notif0( active low control )

bufif1( active high control ) notif1 ( active high control )

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PULL GATES
— These model Pull Ups and Pull downs. Hence have only one output
and no input.
— Generally used on unconnected signals and tristate outputs.

Syntax Usage
— pullup p1 (data) // data is connected to ‘ logic 1 ’.
— pulldown p1 (data) // data is connected to ‘ logic 0 ’.

— Model a 2:1 mux using tristate gate primitives

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 GATE DELAYS
— Verilog primitives can be modeled according to the functionality as well as
required timing.
— Three types of delays can be modeled
— Rise delay : Delay associated with gate when output changes to 1.
1
0, x or z
— Fall delay : Delay associated with gate when output changes to 0.
1, x or z
0
— Turn-off delay : Delay associated with gate when output changes from “1, 0, x” to high
impedance value.

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GATE DELAYS
— Types of delay specification

// zero delay specification

and (y,a,b); // no delay expression.

// Delay specification for all transition

and #3 (y,a,b); // rise = 3, fall = 3.

//rise fall & turnoff delay specification

notif1 #( 3,4,5 ) (y,a,b); // rise = 3, fall =4, turnoff = 5

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 GATE DELAYS
— For each delay it’s minimum, maximum & typical value also can be specified.

Min/typ/max values are used to model devices whose delays vary within
minimum to maximum range due to variation in IC fabrication process

and # (2:3:4,3:4:5); // min:typ:max rise & fall.

bufif0 #(2:3:4,3:4:5,4:5:6) // min:typ:max rise fall & turnoff delay
— Min, typ & max values can be chosen at Verilog run time.
— Method of choosing min or typ or max value may vary for different simulators or
operating systems.

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Example for Gate level Modeling

100
 Gate delays

101

Additional controls min/ typ/ max values in delays

102
 SWITCH LEVEL MODELING

103

SWITCH LEVEL MODELING

— Verilog provides the ability to design the digital circuits at
MOS-transistor level.

— Various constructs provided are :

— MOS switches
— CMOS switches
— Bi-directional switches

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 MOS SWITCHES
— Two types of MOS switches: nmos and pmos
— NMOS switch
— PMOS switch

nmos control pmos control

data 0 1 x z data 0 1 x z
0 z 0 L L 0 0 z L L
1 z 1 H H 1 1 z H H

x z x x x x x z x x

z z z z z z z z z z

— Note : NMOS conducts when its control is high while PMOS conducts when its control is low.
— nmos (O,I,G) // instantiates NMOS switch, no instance name
O = output, I = input , G = control

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module inv_sw (out, in);

output out; // inverter output
input in; // inverter input
supply1 power; // "power" connected to Vdd
supply0 ground; // "ground" connected to Gnd
pmos (out, power, in); // instantiate pmos switch
nmos (out, ground, in); // instantiate nmos switch
endmodule
106
 CMOS SWITCH
— A CMOS switch has pmos & nmos switch in parallel.

— The output of switch is in high-impedance state if ncontrol is 0 & pcontrol is 1.

107

BIDIRECTIONAL SWITCHES
— MOS & CMOS switches are unidirectional, conduct from drain to source.
— Bidirectional switches conduct in both directions.
— Used to provides isolation between input & output.

switches Symbol Characteristics

tran inout1 inout2 Acts as buffer

Either inout1 or inout2 can be driver signal

tranif0 control Connects inout1 & inout2, if control is low.

inout1 inout2 If control is high, output is ‘z’

tranif1 control Connects inout1 & inout2, if control is high.

inout1 inout2 If control is low, output is ‘z’.

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 RESISTIVE SWITCHES
— MOS, CMOS & Bidirectional [tran] switches are modeled with Zero ON_Resistance.
To model them with ON-Resistance primitives rnmos, rpmos, rcmos, rtran, rtranif0,
rtranif1 are provided.
input output
— Features of resistive switches strength strength
— High source to drain impedance. supply pull
Regular switches have a low source to drain impedance. strong pull
pull weak
— Hence when a signal passes through a resistive switch its
strength reduces. weak medium
Regular switches retains the signal strength. large medium
medium small
small small
high high
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NMOS and PMOS switches

CMOS switch

110
 Power and ground Bidirectional switches

111

Resistive switches

112
 Summary……

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115

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117

Conclusion : Write codes which can be

translated into hardware !

The following cannot be translated into hardware( non - synthesizable):

• Initial blocks
– Used to set up initial state or describe finite testbench stimuli
– Don’t have obvious hardware component
• Delays
– May be in the Verilog source, but are simply ignored
• In short, write codes with a hardware in your mind. In other words do not
depend too much upon the tool to decide upon the resultant hardware.
• Finally, remember that you are a better designer than the tool.

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