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Digital Systems Design (Ecen 2002)

The document is an exam for the course Digital Systems Design. It contains 9 questions with multiple parts each. The questions cover topics like Boolean algebra, logic gates, flip flops, counters, encoders, multiplexers, analog to digital converters, and integrated circuit design. Students are required to answer 5 out of the 7 groups of questions. The time allotted for the exam is 3 hours and it is out of 70 total marks.

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Vikash Kumar
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0% found this document useful (0 votes)
54 views2 pages

Digital Systems Design (Ecen 2002)

The document is an exam for the course Digital Systems Design. It contains 9 questions with multiple parts each. The questions cover topics like Boolean algebra, logic gates, flip flops, counters, encoders, multiplexers, analog to digital converters, and integrated circuit design. Students are required to answer 5 out of the 7 groups of questions. The time allotted for the exam is 3 hours and it is out of 70 total marks.

Uploaded by

Vikash Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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B.TECH/IT/3RD SEM/ECEN 2002/2019 B.

TECH/IT/3RD SEM/ECEN 2002/2019


B.TECH/IT/3RD SEM/ECEN 2002/2019 (ix) A 4-stage ripple counter counts up to
(a) 12 (b) 15
DIGITAL SYSTEMS DESIGN (c) 11 (d) 4.
(ECEN 2002)
(x) The slowest ADC is
Time Allotted : 3 hrs Full Marks : 70 (a) counter type (b) flash type
Figures out of the right margin indicate full marks. (c) successive approximation type (d) dual slope type.

Candidates are required to answer Group A and Group – B


any 5 (five) from Group B to E, taking at least one from each group.
2. (a) Simplify the Boolean function by using K-map:
Candidates are required to give answer in their own words as far as practicable. F= ∑m(0, 1, 2, 8, 10, 11, 14, 15)+ ∑d(3,13).
Group – A (b) Prove that F=∑m(1,2,3,4)= ∏M(0,5,6,7).
(Multiple Choice Type Questions) (c) (i) Convert 756.6038 to hex.
1. Choose the correct alternative for the following: 10 × 1 = 10 (ii) Convert B9F.AE16 to octal.
4 + 4 + (2 + 2) = 12
(i) A decoder with enable input can be used as
(a) Encoder (b) Parity Generator 3. (a) Simplify the following function in SOP form using Quine MC-Cluskey
(c) Multiplexer (d) Demultiplexer. method:
F(A, B, C, D)=∑m(0,1,4,7,9,11,13,15) + ∑d(3,5).
(ii) (1 AF)16 =
(a) (567)8 (b) (576)8 (b) Realize the X-OR function using (i) AOI logic (ii) NAND logic.
(c) (657)8 (d) (557)8. 8 + 4 = 12
(iii) The number of full adders required to construct an m-bit parallel adder is Group – C
(a) m/2 (b) m-2
(c) m (d) m+1. 4. (a) Design 16 : 1 MUX using five 4 : 1 MUX.
(iv) Excess 3 code representation of (19)10 is (b) Design full substractor circuit using 4 : 1 MUX and necessary logic gates.
(a) 10011 (b) 00011001 (c) What are the difference between Decoder and Demultiplexer?
(c) 01001100 (d) 11000100. 5 + 5 + 2 = 12
(v) The simplified form of the Boolean expression (X+Y+XY)(X+Z) is
(a) X+Y+Z (b) XY+YZ 5. (a) Implement the function F(a,b,c) = ab  bc using 4 : 1 MUX.
(c) X+YZ (d) XZ+Y. (b) Construct two bit comparator using basic logic gates.
(vi) Which of the following flip-flop is used as a latch? (c) Give the logic implementation of a 8 × 4 bit ROM using a decoder of a suitable size.
(a) J-K flip-flop (b) Master-Slave flip-flop 5 + 4 + 3 = 12
(c) T flip-flop (d) D flip-flop.
Group – D
(vii) A (32×10) ROM contain a decoder of size
(a) 32×32 (b) 5×32 6. (a) What do you mean by Race-around condition of a flip-flop? How can it be
(c) 32×10 (d) 10×32. overcome?
(viii) Resolution of n-bit DAC is given by (b) What is the main difference between a latch and a flip-flop?
(a) 1/(2n-1) (b) 1/2n
(c) 1/(2 +1)
n (d) 1/2-n. (c) Convert D flip-flop to SR flip-flop.
(2 + 1) + 3 + 6 = 12
ECEN 2002 1 ECEN 2002 2
B.TECH/IT/3RD SEM/ECEN 2002/2019

7. (a) Design a counter that goes through states 3, 4, 6,7and 3 states using JK
flip-flops.
(b) A binary ripple counter is required to count up to 1638310 .How many FFs
are required? If the clock frequency is 8.192 MHz, what is the frequency at
the output of the MSB?
8 + 4 = 12

Group – E

8. (a) With the help of necessary circuit diagram, explain the operation of dual slope ADC.
(b) What are the advantages and disadvantages of the Flash Type A/D converter?
(c) Design a 2-input NAND gate using CMOS inverter.
6 + 2 + 4 = 12

9. Write short notes on any three of the following. (4 × 3) =12


(i) Parallel In Serial Out shift register
(ii) CMOS
(iii) TTL
(iv) Priority Encoder
(v) Master Slave flip flop.

ECEN 2002 3

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