PCBFABRICATION

BGA Breakout Challenges

by Charles Pfeil,
Mentor Graphics

The routing of large pin-count and

dense BGAs has a significant im-
pact on the cost of the PCB, prima-
rily in terms of layer count and via
technology. Considerable research
has been done with the intent of
providing a general flow solution
to the BGA breakout problem. The
results indicate the need for col-
laboration between chip, package
and PCB designers - emphasising
the dependencies that need to be
managed to reduce board costs.
The number of variables confront-
ed in large BGA routing is signifi-
cant. We take a look at solutions
based on a logical analysis of ASIC
and FPGA BGA pin density, array
patterns, packaging requirements,
pin swap constraints, layers, via
technology, topology planning and
P R O T O T Y P E S

routing methods.

Using a BGA is the most common Figure 1 – Example of a ball grid array breakout
method today for packaging a high
pin-count or very dense ASICs and than 0.8mm, do not present a sig- ture will bring over 2000 pins and
FPGAs. BGAs have been proven to nificant breakout problem and are a 0.8mm pin-pitch.
be a reliable, cost effective package usually routed without a “break-
while at the same time providing out” method. During the past year, a team at
flexibility to address miniaturisa- Mentor Graphics researched the
tion and functional requirements. The BGA breakout challenge starts existing methods for routing large
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However, the increasing pin-count with over 1000 pins and 1mm pin- BGAs with the intent of finding
and decreasing pin-pitch creates pitch. The largest FPGA in produc- both interactive and automatic
S I M U L A T I O N

a significant problem for PCB de- tion today is the Xilinx Virtex-4 and routing solutions for the short-
signers who must minimise layer Virtex-5 FF1760 series with 1760 term and long-term. The methods
count (to reduce fabrication costs) pins and a 1mm pin-pitch. The fu- presented below address the 1760
and fulfil signal integrity require-
ments (to meet the high perform- Figure 2 – Stackup and via model use
ance goals). Most PCB designers
who are using leading edge BGAs
claim that the breakout of the de-
vice is the greatest contributor to
the number of PCB layers. The
term “BGA breakout” means apply-
D E S I G N ,

ing a fanout solution and routing

traces from those fanouts to the
perimeter of the device prior to
general routing of the PCB. Low
pin-count devices (less than 500
pins), even with a pin-pitch of less

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 PCBFABRICATION
pin / 1mm pitch devices well and

1-2 µVia 0.25mm Pad

touch upon methods for the future

1-3 µVia 0.3mm Pad

devices.

Ball Pad 0.6mm

Reality strikes

Initial research on the subject of

BGA breakouts took the team into
the realm of theoretical solutions.
It wasn’t long before it became ap-
parent that most of the theory in
this area breaks down when con-
fronted with the reality of attaining
reasonable manufacturing costs 11-12 µVia 0.25mm Pad

10-12 µVia 0.3mm Pad

2-11 Blind Via 0.4mm Pad

and fulfilling the signal integrity
requirements.

There are numerous papers offer-

ing mathematical solutions to high
pin-count devices in which the Figure 3 – HDI stackup
minimum number of layers can be
calculated and various patterns for • Layer Stackup there will be exceptions to the rec-
the traces are shown. Unfortunate- • Via Models ommendations in Figure 2 and the
ly, these proposals do not account • Design Rules data in the chart should be consid-
for the impact of power and ground • Signal Integrity. ered as guidelines. What happens
pins, the distribution FPGA banks if one tries to use a borderline via
in various arrangements (with the By making initial decisions in model and stackup? Design rules
requirement that all signals in the these areas, the task of finding a (smaller feature sizes and clear-
bank need to have the same ref- breakout solution becomes feasible ances) will have to be compro-

P R O T O T Y P E S
erence plane), reasonable design as opposed to overwhelming. For mised, resulting in lower fabrica-
rules to reduce crosstalk, and nets purposes of this paper, a specific set tion yields and potential crosstalk
that should be routed as differential of values that work well together problems.
pairs - or worse yet, nets that can for large pin-count BGAs has been
be routed either as single-ended or chosen for these variables.
differential pairs depending on the Laminated versus buildup
performance goals of the circuit.
Stackup and via models Buildup technology, also known as
Along with mathematical solu- High Density Interconnect (HDI),
tions, there are a plethora of pro- The choice of stackup and via mod- has taken over the handheld indus-
posals for spacing and aligning els will have the greatest impact try and is the preferred stackup for
fanout vias. While it is true that the on reducing layer count. Of course all PCBs in the PAC Rim. However,
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fanout method is the key to a suc-

cessful breakout; it is not true that Figure 4 – Use of 1-3 fanout vias Figure 6 – Micro-vias and buried-
S I M U L A T I O N

any one method can be applied to vias

all situations especially when the
stackup and via models are usually
chosen on a fabrication cost basis.

Compromise
Figure 5 – Layer 3 with 1-3 fanout
The art of engineering is to appro- micro-vias aligned
priately compromise the myriad of
variables and still have the project
D E S I G N ,

fulfil the time, cost and perform-

ance goals. In the context of BGA
breakouts, there are indeed a myr-
iad of variables; however, these are
the ones that have the greatest im-
pact on cost and performance:

www.Onboard-Technology.com OnBoard Technology October 2007 - page 11

PCBFABRICATION

Figure 7 – Staggered buried-vias

Figure 8 – Staggered buried-vias routed

planes between the routing method used, it may be

layers eliminates the necessary to compromise these
crosstalk potential. design rules inside the BGA. For
example, to enable routing from
the fanout vias to the perimeter of
Design rules the device, it may be necessary for
Figure 9 – Contortion of differential pairing the single-ended routes to have a
Only two criteria 0.1mm width and clearance. The
it still lags behind FR-4 laminated drive design rules; obtaining high consequence of this compromise is
in the US and Europe for computer, fabrication yields (cost) and fulfill- that you will have a small imped-
network and larger designs in gen- ing signal integrity requirements ance discontinuity when the trace
eral. High pin-count and less than (performance). Of course a third changes to 0.13mm – this may or
1mm pin-pitch BGA will force the could be “what we have done in the may not be a significant problem in
adoption of HDI for all PCBs. The past” as a justification to ignore the the context of all the other signal
good news is that HDI is now low first two; fortunately, the number integrity effects being managed in
cost and for the same pin density of companies wrapped up in that the design.
actually lower cost than laminated. praxis are few.
P R O T O T Y P E S

The stackup in Figure 3 is one that For signal integrity purposes, it Signal integrity
worked best with the Mentor team’s is generally desirable to have 50
breakout attempts for the Virtex-4 ohm traces for single-ended nets While creating the breakouts for
and Virtex-5 series with 1760 pins. and 100 ohm traces for differen- the Xilinx Virtex-4 and Virtex-5 se-
In the world of HDI, this stackup is tial pairs. Using the HDI stackup ries FPGAs, the following signal in-
common and cost effective: shown in Figure 3, this can be at- tegrity considerations were made:
tained by using the following de-
• GND is on the outer layers and sign rules (values for English units • Reference planes - Common ref-
each signal layer has a good refer- are rounded off): erence plane for all signals in the
ence plane next to it. Having the same bank. This was addressed by
GND on the outer layers also pro- • Single-ended – width 0.13mm routing all the signals in the same
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vides excellent control of EMI. (5th), clearance 0.13mm (5th) bank on the same layer and by pro-
• There are 4 signal layers, which • Differential pairs – width 0.1mm viding a good reference plane for
S I M U L A T I O N

is enough for the breakout. More (4th), clearance 0.15mm (6th), pair each layer.
signal layers can be added in the to pair clearance 0.3mm (12th) • Differential pairs - Routing the
centre of the stackup if required. • Layer 1-2 micro-via pad 0.25mm pairs as 100 ohm transmission
• The 11-12 and 10-12 vias are not (10th), hole 0.1mm (4th) lines, with similar length, appro-
used for the signal breakouts, but • Layer 1-3 micro-via pad 0.3mm priate compliment spacing, and
may be used for power and ground (12th), hole 0.15mm (6th) sufficient clearance from other dif-
if bypass capacitors are needed. • Layer 2-11 buried-via pad 0.4mm ferential pairs to minimise cross-
Some FPGAs like the Virtex-4 and (16th), hole 0.2mm (8th) talk.
Virtex-5 series have bypass capaci- • Ball pad 0.6mm (24th). • Single-ended nets - Routing
tors in the BGA package, minimis- these nets as 50 ohm transmis-
ing the need for them on the PCB These design rules are also quite sion lines, and providing sufficient
D E S I G N ,

under the device. good for low fabrication cost since clearance to other traces to mini-
• The signal layers are not paired; most PCB fabricators routinely mise crosstalk.
rather they are separated by GND produce boards with 0.1mm width • Buried via crosstalk - Some con-
planes. The breakout traces on a and clearance. cern has been expressed over the
large BGA usually result in layer- potential for crosstalk between the
to-layer parallelism. Using GND Depending on the fanout and buried vias in the HDI stackup and

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 PCBFABRICATION
that the clearance between them Micro-vias - Using micro-vias in that a different fanout pattern will
should be more than 0.1mm. In- an HDI stackup is essential to re- be required. The following factors
vestigation on this showed varied duce layer count. In the context of and their combinations may cause
opinions and the question won’t the Figure 3 stackup, the number unique fanout patterns to be used:
be resolved until the appropriate of breakouts created with the 1-3
simulations are run. One version via should be maximised. Doing • Arrangement of power and
of the breakout includes increased this opens up considerable routing ground pins - Sometimes they are
clearances between the buried space on the other 3 routing layers grouped in the centre, other times
vias of different differential pairs. because the 1-3 via doesn’t exist as sprinkled around the device in
However, this method forces the shown in Figure 4. regular or irregular patterns that
number of signal layers to be 6 in- could interrupt the ability to use
stead of 4 because the fanout vias If the 1-3 fanout vias are aligned the same fanout pattern for the I/O
need to be staggered as opposed to in a pattern as shown in Figure 5, pins.
aligned. additional routing space is created • Arrangement of the banks on an
compared to just having a matrix FPGA - The banks may be grouped
of vias on 1mm spacing. together nicely or sometimes
Fanout via patterns split up. The arrangement of the
Micro-vias plus buried-vias – To pins in the bank may or may not
After setting up the design to prop- get to the routing layers 5, 8 & 10 be convenient for differential pair
erly minimise fabrication costs and requires the use of a 1-2 fanout routing, especially since the use
manage signal integrity, the fanout micro-via and a layer 2-10 buried- of aligned or staggered micro-vias
via patterns have the most signifi- via. Again, a good fanout pattern and buried-vias tend to warp the
cant effect on the number of layers is needed to maximise the routing nice symmetry that is often pro-
for the breakout. space. In Figure 6, an effective pat- vided at the ball pad level as shown
tern is shown. in Figure 9.
Thru-vias - If thru-vias in a lami- • Extremely dense BGAs - In Fig-
nate structure must be used, then If it is necessary to increase the ure 10, you can see the areas that
there really are only two options clearance between the buried-vias are easy to breakout (green) and
when the pin-pitch is 0.1mm. The to minimise crosstalk between dif- the difficult areas (red). To break-
vias must be placed either in the ferential pairs, the vias can be stag- out the red areas using minimum

P R O T O T Y P E S
centre between the ball pads or in gered as shown in Figures 7 and 8. layers on a very dense BGA will re-
the pad (which increases the fabri- quire contortion of the fanout via
cation costs because the via must Each large pin-count BGA presents patterns simply because there is
be filled and the ball pad smoothed different problems for fanout pat- so little available space and each
prior to assembly). terns and because of this, it is likely area needs to be customised as is
the case with any very dense PCB
Figure 10 – Red = difficult, green = Figure 11 – Alternating via patterns, routing. This is illustrated in the
easy 1-3 versus 1-2 & 2-10 alternating via patterns shown in
Figures 11 thru 12.

The tipping point

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BGAs will continue to grow in

S I M U L A T I O N

pin-count and density. At 1mm

pin-pitch it is still feasible to use
laminated PCB technology with
thru-vias and/or blind and buried
vias. However, if it is necessary to
Figure 12 - Routing of 1st signal layer Figure 13 - Routing of 2nd signal layer minimise layers, using HDI with
micro-vias is the best method.
Once the BGA packages have more
than 2000 pins and a pin-pitch of
0.8mm, HDI will be required. Now
is a good time to get ready for this
D E S I G N ,

change.

This article is based on a paper originally

presented at the IPC Printed Circuits Expo,
APEX, and the Designers Summit 2007

www.Onboard-Technology.com OnBoard Technology October 2007 - page 13