Challenges of Implementing

High-Speed PCB Design Flow

at CERN

(www.cern.ch)
Jean-Michel Sainson & John Evans CERN IT-PS/EAS
(Electronic Applications Support)
J-M.Sainson@cern.ch

1 Challenges of Implementing a High-Speed PCB Design Flow at CERN - European Cadence® User Group Meeting 2004 -
 Overview
‹ High-Speed Board Design Issues
„ High-Speed Board for CERN Physics Experiment
„ High-Speed Boards Development Concerns
‹ Cadence® PSD 14.2 High-Speed Design Flow
„ PSD 14.2 High-Speed PCB Design Flow
„ Exploration: SigXplorer Example
„ Implementation: Constraint Manager // Allegro-Expert
‹ Design Flow Splitting
„ PCB Design Phases
„ PCB Implementation Phase
„ Design Workflows
‹ DDR SDRAM Interface Demonstrator
(Workflow Evaluation)
„ Demonstrator Goals
„ Demonstrator Workflow
„ Tasks for Board Designer
„ Tasks for Layout Designer
„ Workflow Evaluation Results
‹ Challenges or ….
„ …. Difference Between Theory and Practice

2 Challenges of Implementing a High-Speed PCB Design Flow at CERN - European Cadence® User Group Meeting 2004 -
 High-Speed Board Design Issues

3 Challenges of Implementing a High-Speed PCB Design Flow at CERN - European Cadence® User Group Meeting 2004 -
 High-Speed Board for CERN Physics Experiment
‹ NP4GS3 Network Processor mezzanine board
„ Fast technologies switching time (tr, tf < 500ps min), is the main source of signal
integrity/timing degradation on a wide number of mezzanine lines
DATA-ALIGNED SYNCHRONOUS LINKS (DASL)
14 layers 1088-Pin 2 x 8 EIA/JEDEC JESD8-6 standard
± 10% (CCGA) Package channel for differential HSTL
Controlled Impedance Fine Pitch 1.27 mm
Board (tr, tf = 300ps min)
815 I/O (Up to 625 Mbps per channel)

DRAM Control
DASL
A&B

2x PCI 2x
3.3V 8Mx16 8Mx16 8Mx16 8Mx16 32bits 512kx18 512kx18
DDR DDR DDR DDR SRAM SRAM
33/66MHz
(D3) (D2) (D1) (D0) (LU) (SCH)
2.5V

1.8V DRAM Control

DRAM NP4GS3
Control
53.3 MHZ 2x 2x 2x
2x 2x 2x
32Mx4 32Mx4 32Mx4
8Mx16 8Mx16 8Mx16
DDR DDR DDR
PARITY DDR DDR
125 MHZ PARITY DATA DATA
DATA DATA
(D4) (DS0) (DS1)
(D6) (D6) (D6)
JTAG DMUs
DRAM Data
DRAM Data

A B C D
Double Data Rate SDRAM INTERFACE
JEDS8-9A SSTL2 Standard 2 x 4 GIGABIT MEDIA INDEPENDENT INTEFACE UNITS (GMII)
Stub Series Terminated Logic for 2.5V (4 GIGABIT ETHERNET)
(tr, tf = 500ps min) Full Duplex 8 bit data Bus 125 MHz Clock
CLK 133 MHZ LVTTL (tr, tf = 400ps min)

4 Challenges of Implementing a High-Speed PCB Design Flow at CERN - High-Speed Board Design Issues –
 High-Speed Boards Development
Concerns

‹ Some typical High-Speed boards issues

„ Logic families with fast switching time respective to line lengths
„ Via count reduction
„ Single ended and differential Zo controlled impedance
„ Cross-talk between lines
„ Mandatory terminations types; Tthevenin, serie, rc, etc.
„ Min max and relative propagation delays
„ Total “etch” length
„ Very high package pins number and density
„ Packages and connectors parasitic effects
„ Narrow setup & hold times
„ Multiple constraints on the same net
„ Large % of constrained NETS

‹ Cadence “Silicon-Package-Board” Division have improved their traditional

design flow to take into account these “High-Speed” issues

5 Challenges of Implementing a High-Speed PCB Design Flow at CERN - High-Speed Board Design Issues –
 ®
Cadence

PSD 14.2 High-Speed Design Flow

6 Challenges of Implementing a High-Speed PCB Design Flow at CERN - European Cadence® User Group Meeting 2004 -
 PSD 14.2
High-Speed PCB Design Flow
‹ Based around the "Constraint Manager“
„ Signal Explorer-Expert (SigXplorer) physical topologies exploration tool
„ Concept-HDL schematic capture tool
„ SPECCTRAQuest SI Expert (SPECCTRAQuest) pre and post-layout signal integrity
analysis platform
„ ALLEGRO-Expert (ALLEGRO) interactive placement and routing tool
„ SPECCTRA optional automatic router
High-Speed PCB Design Flow

Implementation
Exploration Capture Setup & Analyses
Checking

Concept-HDL SPECCTRAQuest Allegro SPECCTRAQuest

SPECCTRA

Constraint Manager
Constraint Manager

SigXplorer SigXplorer SigXplorer SigXplorer SigXplorer

7 Challenges of Implementing a High-Speed PCB Design Flow at CERN - Cadence® PSD 14.2 High-Speed Design Flow -
 Exploration: SigXplorer Example
‹ Multidrop BUS topology capture and simulation under SigXplorer

IBIS Models
Stubs

Controlled 55 Ω
Derivation Transmission
Point Line
"T Points"

Multidrop BUS
Simulations

8 Challenges of Implementing a High-Speed PCB Design Flow at CERN - Cadence® PSD 14.2 High-Speed Design Flow -
 Implementation:
Constraint Manager // Allegro-Expert
‹ Constraints Driven placement

Serial termination R21 placed too far

(1340 MIL) from driver. Maximum
length constraint allowed from driver
to left pin resistor = 800 MIL

9 Challenges of Implementing a High-Speed PCB Design Flow at CERN - Cadence® PSD 14.2 High-Speed Design Flow -
 Design Flow Splitting

10 Challenges of Implementing a High-Speed PCB Design Flow at CERN - European Cadence® User Group Meeting 2004 -
 PCB Design Phases

„ Exploration and Topologies Analysis Phase with SigXplorer

„ Schematic Capture Phase with Concept-HDL and associated constraints under Constraint
Manager connected to Concept (CM2C)
„ Board DTB Setup Phase under SPECCTRAQuest and constraints assignment under
Constraint Manager connected to SPECCTRAQuest (CM2SQ)
„ Checking & Analysis Phase of final board layout with Constraint Manager connected to
SPECCTRAQuest (CM2SQ)
„ Exploration under SigXplorer and final Analysis Phases under SPECCTRAQuest are
optional workflow dependent; see slide 13 (Design Workflows)

11 Challenges of Implementing a High-Speed PCB Design Flow at CERN - Design Flow Splitting -
 PCB Implementation Phase

Design Implementation Design

PCB Layout Checking

Exploration Capture
Board DTB (After Board &
Setup DTB Review) Analysis

Concept-HDL SPECCTRAQuest Allegro SPECCTRAQuest

SPECCTRA

Constraint Manager
Constraint Manager

SigXplorer SigXplorer SigXplorer SigXplorer SigXplorer

„ Review of Board Data Base Setup & Constraints

„ Interactive PCB Placement & Routing (Constraints Driven) with Allegro-Expert and
Constraint Manager connected to Allegro-Expert (CM2AE)
„ Automatic Constraints Driven Routing with SPECCTRA (Optional)

12 Challenges of Implementing a High-Speed PCB Design Flow at CERN - Design Flow Spitting -
 Design Workflows
Post-Layout
Signal Integrity Need of IBIS
Design Workflow Type Purpose and/or Timing models
simulations
needed
To implement layout rules
X from IC manufacturer
Rules Based No No

To implement layout rules

Y from IC manufacturer
Rules Based Followed by an analysis Yes Yes
with PCB Simulation phase (simulation) on the final
layout
To develop and implement
Z layout rules, (no rules available
Constraints Development from IC manufacturer) No Yes

To develop and implement

[ layout rules, (no rules available
Constraints Development from IC manufacturer) Yes Yes
with PCB simulations Followed by an analysis
phase (simulation) on the final
layout

13 Challenges of Implementing a High-Speed PCB Design Flow at CERN - Design Flow Spitting -
 DDR SDRAM Interface Demonstrator

(Workflow Evaluation)

14 Challenges of Implementing a High-Speed PCB Design Flow at CERN - European Cadence® User Group Meeting 2004 -
 Demonstrator Goals
‹ Use IC MANUFACTURER GUIDELINES to place and route a subset of NP4GS3
DDR SDRAM (D6) interface on a mezzanine board

DRAM Control
DASL
A&B

2x PCI 2x
3.3V 8Mx16 8Mx16 8Mx16 8Mx16 32bits 512kx18 512kx18
DDR DDR DDR DDR SRAM SRAM
33/66MHz
(D3) (D2) (D1) (D0) (LU) (SCH)
2.5V

1.8V DRAM Control

DRAM NP4GS3
Control
53.3 MHZ 2x 2x 2x
2x 2x 2x
32Mx4 32Mx4 32Mx4
8Mx16 8Mx16 8Mx16
DDR DDR DDR
PARITY DDR DDR
125 MHZ PARITY DATA DATA
DATA DATA
(D4) (DS0) (DS1)
(D6) (D6) (D6)
JTAG DMUs
DRAM Data
DRAM Data

A B C D

64 MB DDR SDRAM D6 INTERFACE ARCHITECTURE

6 Samsung (32X4) K4H280438C-TCA2 18 bits DATA BUS
I/O technologies Stub series Terminated Logic 2.5V (SSTL2) & 13 bits ADDRESS BUS
CMOS Differential Clock
66 pins TSOP II Package Clock Cycle 133 MHZ
Double-data rate architecture; two transfers per clock cycle
I/O technologies Stub series Terminated Logic 2.5V (SSTL2)&
CMOS

15 Challenges of Implementing a High-Speed PCB Design Flow at CERN - DDR SDRAM Interface Demonstrator -
 Demonstrator Workflow
Post-Layout
Signal Integrity Need of IBIS
Design Workflow Type Purpose and/or Timing models
simulations
needed
To implement layout rules
X from IC manufacturer
Rules Based No No

To implement layout rules

Y from IC manufacturer
Rules Based Followed by an analysis Yes Yes
with PCB Simulation phase (simulation) on the final
layout
To develop and implement
Z layout rules, (no rules available
Constraints Development from IC manufacturer) No Yes

To develop and implement

[ layout rules, (no rules available
Constraints Development from IC manufacturer) Yes Yes
with PCB simulations Followed by an analysis
phase (simulation) on the final
layout

16 Challenges of Implementing a High-Speed PCB Design Flow at CERN - DDR SDRAM Interface Demonstrator -
 Tasks for Board Designer

Workflow
Type Y

„ C Æ Concept-HDL: exportation to physical DTB

(Packager-XL +NETREV)
„ D Æ SPECCTRAQuest-Expert: Basic layout DTB
setup; cross section, DC nets identification,
„ A Æ Concept-HDL: schematic capture discrete (R, L, C) Autosetup models assignment
„ B Æ CM2C: ECSets capture „ D1Æ SPECCTRAQuest-Expert:
„ B1Æ SigXp: Ibis/Dml libraries declaration Ibis/Dml models assignment
(before topology capture) „ E Æ CM2SQ:
„ B2Æ SigXp: constrained topology capture ECSets mapping to physical NETs
„ B3Æ Concept-HDL : constrained topology „ F Æ CM2SQ: Post-layout constraints violation check
importation from SigXp „ G Æ CM2SQ: Post-layout simulation check

17 Challenges of Implementing a High-Speed PCB Design Flow at CERN - DDR SDRAM Interface Demonstrator -
 Tasks for Layout Designer
SPECCTRAQuest Implementation
Expert
or
ALLEGRO-Expert
SPECCTRA
(OPTION)

From / To Constrained
Board (.BRD)
Design Database

It is recommended to REVIEW
with BOARD DESIGNER setup Constraint Manager
parameters 1 to 5 Connected to
ALLEGRO ( CM2A )

Physical
NETs

ECSets

Board Data Base Setup Review under ALLEGRO-Expert

n Layout cross section stack-up and impedance
o DC Nets assignment
p Discrete (R, L, C) models assignment
[ Active (Ibis/Dml) models assignment
\ ECSets mapping to physical NETs with Constraint Manager connected to ALLEGRO-Expert (CM2AE)
] Constraints driven placement and routing with CM2AE // (ALLEGRO-Expert + SPECCTRA)

18 Challenges of Implementing a High-Speed PCB Design Flow at CERN - DDR SDRAM Interface Demonstrator -
 Workflow Evaluation Results
‹ We have found PSD 14.2 High-Speed design flow can:
„ Provide a consistent way to create, manage and validate Designer’s intent
„ Drive design through chip-vendor or user-defined constraints
„ Take into account high-speed design constraints early in the design flow up to layout
minimising prototype iteration and cost
„ Help to master production dispersion through combined silicon package and PCB
technology parametric simulations
„ Formalise highly constrained boards design avoiding misunderstanding between
board designers and layout experts (could help outsourcing)
„ Facilitate documentation and maintenance under Engineering Data Management
System (EDMS) for long duration projects such as the one we have at Cern

‹ Limitations on CM2C (PE 14.2)

„ Does not support Pin Pairs, XNets and Differential Lines
„ Differential lines supported from release 15.0 (autumn 2003)
‹ Limitations on CM2SQ (PE 14.2)
„ Does not support Differential Lines
„ Differential lines supported from release 15.0 (autumn 2003)
„ Remaining problems to update CM2SQ simulated spreadsheets

19 Challenges of Implementing a High-Speed PCB Design Flow at CERN - DDR SDRAM Interface Demonstrator -
 Challenges
or ….

20 Challenges of Implementing a High-Speed PCB Design Flow at CERN - European Cadence® User Group Meeting 2004 -
 …. Difference Between Theory and Practice
‹ We have had more than 20 “success stories” in stand alone usage of SigXplorer
and SPECCTRAQuest. However, the majority of Designers continue to use the
“trial and error” design method based on prototype iteration, taking the risk of poor
production yield and, worse, unreliable operation. Why?
„ Mainstream CLK frequency of 40MHz for our main project (LHC) is not seen so critical by
Designers, despite tr,tf frequently < 500ps
„ Board Designers are under pressure, they do not yet appreciate signal integrity analysis as a
priority
‹ Also, on the PCB side:
„ Layout experts must be able to use these tools
„ “Standard” libraries following Cadence specifications are mandatory in order to support specific
signal integrity attributes

‹ How we intend to develop this workflow at CERN

„ Continue our efforts to broadcast high-speed design discipline methods
to board Designers
„ Provide “hands-on” trainings based on design examples showing that the tools are able
to identify and simply solve simply signal integrity problems early in the design flow

‹ Yet more expertise will be needed with the introduction of MULTI-GIGABIT

technologies and POWER INTEGRITY analysis.
Can these tools be mastered without the aid of a specific “co-design” team?

21 Challenges of Implementing a High-Speed PCB Design Flow at CERN - Challenges or …. -

 “Getting an OK answer NOW is
often more important than
getting a BETTER answer latter”

Eric Bogatin

22 Challenges of Implementing a High-Speed PCB Design Flow at CERN - European Cadence® User Group Meeting 2004 -
 Annexe

23 Challenges of Implementing a High-Speed PCB Design Flow at CERN - European Cadence® User Group Meeting 2004 -
 DDR SDRAM Manufacturer Guidelines 1
‹ CNTRL_ADDR Lines Constraints
„ Control and address lines are six-drop lines terminated into a 50 Ω equivalent circuit
„ Board Stackup controlled impedance = 55 Ω ± 10 %
„ The distance from NP4GS3 to the furthest SDRAM must not exceed 3.25 inches
„ The stub to the SDRAM pin should not be more than 0.25 inches

DDR SDRAM
DDR SDRAM (32M x 4)
DDR SDRAM (32M x 4)
DDR SDRAM (32M x 4)
50 Ω Thevenin DDR SDRAM (32M x 4)
DDR SDRAM (32M x 4) SAMSUNG
SAMSUNG
K4H280438C
SAMSUNG
Equivalent (32M x 4)
K4H280438C

Stub ≤ 0.25 inches

SAMSUNG K4H280438C
SAMSUNG K4H280438C
Terminations SAMSUNG K4H280438C
K4H280438C

2.5V

2.5V
100 Ohms
2.5V

100 Ohms
2.5V
100 Ohms
13 ADDRESS LINES
100 Ohms
100 Ohms NP4GS3
10 CONTROL LINES
100 Ohms

100 Ohms

100 Ohms Zo = 55 Ω ± 10%

L ≤ 3.25 inches

24 Challenges of Implementing a High-Speed PCB Design Flow at CERN - Annexe -

 DDR SDRAM Manufacturer Guidelines 2
‹ DA_DQS Lines Constraints
„ All DATA and DQS nets must be terminated with a 22-29 Ω series resistor placed no
more than one inch from the NP4GS3
„ No more than 25 % of the trace should be on the NP4GS3 side of the terminating resistor
„ Each set of DATA and DQS lines must be no shorter than one inch and no longer than
3.25 inches
„ For each set of four DATA lines and its respective DQS line, there can be no more
than ± 70 ps of flight time difference from the NP4GS3 to the RAM. Use IBIS simulation to
be sure that there no more than ± 70 ps difference between DQS and its corresponding
DATA lines
DDR
DDR SDRAM
DDR SDRAM
DDR SDRAM (32M x 4) (32M x 4)
DDR
DDR SDRAM
SDRAM (32M x 4) SAMSUNG 1 inch ≤ L ≤ 3.25 inches
SDRAM (32M x 4) (32M x 4) SAMSUNG K4H280438C
SAMSUNG K4H280438C
(32M x 4) SAMSUNG K4H280438C

≤ 1 inch
SAMSUNG K4H280438C
SAMSUNG K4H280438C
K4H280438C

4 DATA LINES
22-29
DQS0
Ohms

4 DATA LINES
DQS (Vs) 4 DATA 22-29
Ohms DQS1

Lines flight time 4 DATA

4 DATA
LINES
LINES
22-29
Skew Ohms DQS2
NP4GS3
± 70 ps 4 DATA LINES
22-29
Ohms DQS3

Zo = 55 Ω ± 10% 1 DATA LINES 22-29

Ohms DQS4

1 DATA LINES
22-29
Ohms DQS5

25 Challenges of Implementing a High-Speed PCB Design Flow at CERN - Annexe -