26 October - 20 November, 2009: FPGA Architectures & VHDL Introduction To Synthesis

2065-15
Advanced Training Course on FPGA Design and VHDL for Hardware

Simulation and Synthesis
26 October - 20 November, 2009
FPGA Architectures & VHDL

Introduction to Synthesis
Nizar Abdallah
ACTEL Corp.2061 Stierlin Court Mountain View
CA 94043-4655
U.S.A.
Nizar Abdallah
nizar@ieee.org
October 2009
Introduction to FPGAs & FPGA design flows
Introduction to Synthesis
The VHDL hardware description language
Design verification, validation, and testing
Programmable logic & FPGA architectures

Actel’s SoC Flash FPGA architectures
Co-design & co-verification of HW/SW embedded systems
Emerging technologies and future opportunities.
Actel Corporation Confidential © 2009 2

Why HDL? Why VHDL?
HDL is a software solution due to limits in hardware
solutions and to:
Increasing design complexity
Increasing cost in time and investment
Increasing knowledge requirement
Inadequacy of other existing languages
VHDL is a response to problems for system manufacturers
in verifying their system fully
Vendor dependency
Different vendors with different incompatible HDLs
Problems in design documentation exchange
A standard HDL from the System

Manufacturer’s Point of View: V H D L

VHDL History
1981: Extensive Public Review (DOD): VHSIC Program for
modeling digital systems
1983: Request for Proposal
(Intermetrics, IBM, and Texas Instruments)
1986: VHDL in the Public Domain
1987: Standard VHDL'87 (IEEE-1076-1987)
1993: New Standard VHDL'93 (IEEE-1076-1993)
1994: VITAL (VHDL Initiative Toward ASIC Libs)
2000: Revised standard (VHDL 1076 2000, Edition)
2002: Revised std (named VHDL 1076-2002)
2007: VHDL Procedural Language Application Interface
standard (VHDL 1076c-2007)

VHDL Advantages & Drawbacks
Philosophy: readable, docs-based on a clear and
predictable simulation behavior
Advantages
Standard format for design exchange
Technology independent
Multiple vendor support
Support for large as well as small designs
Support for wide range of abstraction in modeling
Simulation oriented (including for writing testbench)
User defined value abstractions
Timing constructs
Drawbacks
Complex tools
Slow tools

VHDL Main Features
Behavior
Dataflow Timing
Structure

VHDL Architectures
Does not allow a layout description
Abstraction Levels VHDL Architectures

Algorithmic
Behavioral How it works

FSM
RTL
Gate Structural How it is connected
Layout

A Dataflow Language
CONTROLFLOW ≠ DATAFLOW
EX: C language assignment EX: VHDL signal assignment
X = A & B; X <= A and B;
X is computed out of A and A PERMANENT link is created

B ONLY each time this between A, B, and X
assignment is executed
X is computed out of A and B
WHENEVER A or B changes

A Dataflow Language (cont’d)
CONTROLFLOW ≠ DATAFLOW
EX: C language assignment EX: VHDL signal assignment
X = A & B; X <= A and B;

------ ------
X = C & D; X <= C and D;
9 YES 8 NO

Behavioral vs. Structural
D-FF with asynch low reset & pos-edge clock
process
process (CLK,
(CLK, RESET)
RESET) Behavioral
begin
begin
if
if (RESET
(RESET == '0')
'0') then
then
QQ <=
<= '0';
'0';
elsif
elsif (CLK'event
(CLK'event and
and CLK='1')
CLK='1') then
then
QQ <=
<= DATA;
DATA;
end
end ifif ;;
end
end process;
process;
--
-- component
component declaration
declaration Structural
component
component DFFDFF
port
port (( D,
D, CLR,
CLR, CLK
CLK :: in
in std_logic;
std_logic;
QQ :: out
out std_logic);
std_logic);
end
end component;
component;
--
-- component
component instantiation
instantiation
U1:
U1: DFF
DFF
port
port map
map (D
(D =>=> DATA,
DATA, CLR
CLR =>
=> RESET,
RESET, CLK
CLK =>
=> CLK,
CLK, QQ =>
=> OUT);
OUT);

VHDL Building Blocks: Entity
Entity
Architecture
Configuration
Package
Library

Entity Overview
The External Aspect of a Design Unit
Required entity entity_name is

Optional [generic_declaration]
[port_clause]
[entity_declarative_item]
Required end [entity_name];

(NAME
optional)

Entity Example: 2-to-1 Mux
MUX2
AIN
YOUT
BIN
SIN
entity MUX2 is
port (AIN, BIN, SIN : in std_logic;
YOUT : out std_logic);
end MUX2;
Port Port
mode type

Entity Example: Full Adder
Cin A B
entity FULL_ADDER is
port (A, B, Cin : in BIT
BIT;; FULL
S, Cout : out BIT );
BIT); ADDER
end FULL_ADDER;
Port
mode Port
type S Cout

Ports
Provide communication with other components
Must have signal name, type and mode
Port Modes:
in (data goes into entity only)
out (data goes out of entity only and not used internally)
inout (data is bi-directional)
buffer (data goes out of entity and used internally)

VHDL Building Blocks: Architecture
Entity
Architecture
Configuration
Package
Library

Architecture Overview
The Internal Aspect of a Design Unit
Can be behavioral (RTL) or structural
Always associated with single entity
Single entity can have multiple architectures
architecture architecture_name of entity_name is

{ architecture_declarative_part}
{architecture_declarative_part}
begin
{ architecture_descriptive_part}
{architecture_descriptive_part}
end [ architecture_name];
[architecture_name];

Architecture Example: 2-to-1 Mux
Two architecture flavors: Behavioral & Structural
architecture
architecture ONE
ONE of
of MUX2
MUX2 is
is Behavioral
Behavioral
begin
begin
YOUT
YOUT <=
<= (AIN
(AIN and
and not
not SIN)
SIN) or
or (BIN
(BIN and
and SIN);
SIN);
end
end ONE;
ONE;
architecture
architecture TWOTWO of
of MUX2
MUX2 is
is Structural
Structural
component
component MX2
MX2 --
-- aa macro
macro from
from aa library
library
port
port (A,
(A, B,
B, S:in
S:in std_logic;
std_logic; Declarative
YY :out
:out std_logic);
std_logic); part
end
end component;
component;
begin
begin
--
-- instantiate
instantiate MX2
MX2
U1:
U1: MX2
MX2 Descriptive
port
port map(A=>AIN,
map(A=>AIN, B=>BIN,
B=>BIN, S=>SIN, Y=>YOUT); part
S=>SIN, Y=>YOUT);
end
end TWO;
TWO;

Architecture Example: Full Adder
Behavioral
Behavioral
entity
entity FULL_ADDER
FULL_ADDER is is
port
port (A,
(A, B,
B, Cin
Cin :: in
in BIT
BIT;;
S,
S, Cout
Cout :: out
out BIT );
BIT);
end
end FULL_ADDER;
FULL_ADDER;
architecture
architecture DATAFLOW
DATAFLOW ofof FULL_ADDER
FULL_ADDER is
is
signal
signal XX :: BIT ;
BIT;
begin
begin
XX <=
<= AA xor
xor B;
B;
SS <=
<= XX xor
xor Cin
Cin after
after 10ns;
10ns;
Cout
Cout <=<= (A
(A and
and B)
B) or
or (X
(X and
and Cin)
Cin) after
after 5ns;
5ns;
end
end DATAFLOW;
DATAFLOW;

Architecture Example: Full Adder (cont’d)
Structural:
Structural:
Declarative
Declarative part
part
architecture
architecture STRUCTURE
STRUCTURE ofof FULL_ADDER
FULL_ADDER is
is
component
component HALF_ADDER
HALF_ADDER
port
port (( I1,
I1, I2
I2 :: in in BIT
BIT;;
Carry,
Carry, SS :: out
out BIT );
BIT);
end
end component
component; ;
component
component OR_GATE
OR_GATE
port
port (( I1,
I1, I2
I2 :: in
in BIT
BIT;;
OO :: out
out BIT );
BIT);
end
end component
component; ;
signal
signal X1,
X1, X2,
X2, X3X3 :: BIT
BIT;;

Architecture Example: Full Adder (cont’d)
Structural:
Structural:
Descriptive
Descriptive part
part
begin
begin
HA1:
HA1: HALF_ADDER
HALF_ADDER port
port map
map ((
I1
I1 =>
=> A,
A, I2
I2 =>
=> B,
B, Carry
Carry =>=> X1,
X1, SS =>
=> X2);
X2);
HA2:
HA2: HALF_ADDER
HALF_ADDER port
port map
map ((
I1
I1 =>
=> X2,
X2, I2
I2 =>
=> Cin
Cin,, Carry
Carry =>
=> X3,
X3, SS =>
=> S);
S);
OR1:
OR1: OR_GATE
OR_GATE port
port map
map ((
I1
I1 =>
=> X1,
X1, I2
I2 =>
=> X3,
X3, OO =>
=> Cout );
Cout);
end
end STRUCTURE
STRUCTURE ;;

Structural & Hierarchy
Structural Style to represent Hierarchy
entity-architecture
OR1
A HA1 Cout
HA2
B S
Cin
entity-architecture
entity-architecture

Architecture in a Design Tree
Structure & Behavior in a Design Tree
Structural
Behavioral

Entity/Architecture
entity/architecture: a One-to-Many relationship
CIN A B
FULL
ADDER
XX <=
<= AA xor
xor B;
B;
SS <=
<= XX xor
xor CIN;
CIN;
COUT
COUT <=
<= (A(A and
and B)
B) or
or
(X
(X and
and CIN);
CIN);
S COUT

VHDL Building Blocks: Packages & Libraries
Entity
Architecture
Configuration
Package
Library

Packages & Libraries
Libraries contain packages
Packages contain commonly used types, operators,
constants, functions, etc.
Both must be “opened” before their contents can be used in
an entity or architecture
library ieee;
use ieee.std_logic_1164.all;

Commonly Used Libraries & Packages
STD Library Always visible! - no

LIBRARY or USE
standard statement required
IEEE Library
std_logic_1164
Requires LIBRARY and
USE statements
std_logic_arith
std_logic_unsigned

Design Libraries
A STD
N
IEEE SIMULATOR
A
VHDL L PROJECT_LIB
files Y WORK
Z SYNTHESIZER
E
R
library library_name ;
use library_name.package_name.all;

Complete Design Example: Multiplier
library ieee;
use ieee.std_logic_1164.all; Declare the library
use ieee.std_logic_unsigned.all; and packages
entity
entity MULT
MULT is
is
port(A:
port(A: in
in std_logic_vector(3
std_logic_vector(3 downto
downto 0);
0); Now we can use
B:
B: in
downto 0);
0); std_logic_vector
Y:
Y: out
out std_logic_vector(7
downto 0));
0)); types and unsigned
end
end MULT;
MULT;
arithmetic
architecture
architecture TESTTEST of
of MULT
MULT is
is
begin
begin
YY <=
<= AA ** B;
B;
end
end TEST;
TEST;
Is this a structural or behavioral description ?

Data Objects
Constants
Variables
syntax: var:= expression
can be declared in body (inside process) or subprogram (outside
process)
a body-declared variable is never reinitialized
a sub-program declared variable is initialized for each call to the
subprogram
value assignment has immediate effect
Signals
syntax: signal <= value
delayed value assignment
optional propagation delay attribute
no global variables to avoid synchronization problems
value resolution for multiple assignments

Signals
Used for connections internal to the design
Must be declared before use
A SIG1
Must have a type B OUT1
Assignment is done with <= C
Type
.. .. ..
architecture
architecture TEST
TEST of
of EXAMPLE
EXAMPLE is
is
signal
signal SIG1:
SIG1: std_logic
std_logic ;; Declaration
begin
begin
SIG1
SIG1 <=<= AA and
and B;
B; Notice: A, B, C, and OUT1
OUT1
OUT1 <=<= SIG1
SIG1 xor
xor C;
C; are not Signals; They are
end
end TEST;
TEST; Ports declared in the Entity.

Signal Vector
Bit order may be ascending (0 to 7) or descending (7
downto 0)
Q
Q is
is an
an 8-bit
8-bit vector
vector
entity
entity COUNTER
COUNTER is
is
port(CLK:
port(CLK: in
in std_logic;
std_logic;
RST:
RST: in
in std_logic;
std_logic;
QQ :: out
downto 0));
0));
end
end COUNTER;
COUNTER;
S2
S2 is
is aa 3-bit
3-bit vector
vector
……
architecture
architecture BEHAVE
BEHAVE of
of COUNTER
COUNTER is
is
signal
signal S1:
S1: std_logic_vector(7
downto 0);
0);
signal
signal S2:
downto 0);
0);
signal
signal S3:
S3: std_logic;
std_logic;

Vector Slicing
Vector slicing can be used on either side of a signal or
variable assignment statement
Extracts subset of Vector for Reading or Writing
port
port (P:
(P: inin std_logic_vector(0
std_logic_vector(0 to
to 3);
3);
R:
R: out
downto 0);
0);
……
Declaration Direction and
architecture
architecture BEHAVE
BEHAVE of
of EXAMPLE
EXAMPLE is
is
Slice Direction must be the
……
same. (P is up; R is down)
R(5
R(5 downto
downto 3)
3) <=
<= P(0
P(0 to
to 2);
2);
R(5) P(0)
R(4) P(1)
Size of slices must match R(3) P(2)

Data Types
All VHDL data objects must have a type
Port types are declared in the entity
Signal, variable, and constant types are declared in the architecture.
Types we will cover:
STANDARD package types
User-defined enumeration types
IEEE std_logic_1164 package types

IEEE 1076-1987 Standard Package
Predefined VHDL Data Types
Is always visible
No declaration is needed
Types available
BOOLEAN : (false , true)
BIT : ( '0', '1' )
BIT_VECTOR : array of BIT values
INTEGER : range -2 147 483 647 to +2 147 483 647
CHARACTER
NATURAL : Subtype of INTEGER (Non Negative)
POSITIVE : Subtype of INTEGER (positive)
STRING : array of CHARACTERS
REAL : range -1.0E+38 to +1.0E+38
TIME : Physical type used for simulation

IEEE 1076-1987: integer Type
Allowed values are mathematical integers
Minimum range: 231 to -231 (32 bits minimum) if no range
is specified
Useful as index holders for loops or generics
Supported operations are add, subtract, multiply, and divide
architecture
architecture BEHAVE
BEHAVE of
of COUNTER
COUNTER is
is
begin
begin
process(clk)
process(clk)
variable
variable cntr:
cntr: integer
integer range
range 00 to
to 63
63 :=
:= 0;
0;
begin
begin

IEEE 1076-1987: bit / bit_vector Type
Allowed values are ‘0’ and ‘1’
Default initialization to ‘0’
entity
entity MUX
MUX is
is
port
port (A,
(A, B,
B, S:
S: in
in bit;
bit;
Y:
Y: out
out bit);
bit);
end
end MUX;
MUX;
bit_vector is an array of bits
architecture
architecture BEHAVE
BEHAVE of
of MUX
MUX is
is
constant
constant LOW:
LOW: bit_vector(1
bit_vector(1 downto
downto 0)
0) :=
:= “00”;
“00”;
begin
begin

IEEE 1076-1987: boolean Type
Allowed values are library
library ieee;
ieee;
use
ieee.std_logic_1164.all;
true and false
Not a bit literal – entity
entity CONTROLLER
CONTROLLER is is
port
port (SEL
(SEL :: in in boolean;
boolean;
has no relationship X,
X, YY :: in
in std_logic;
std_logic;
to a bit ZZ :: out
out std_logic);
std_logic);
end
end CONTROLLER;
CONTROLLER;
Operations only
allowed in IF-ELSE architecture
architecture BEHAVE
BEHAVE of
of CONTROLLER
CONTROLLER is
is
statements, in begin
begin
process
process (X,
(X, Y,
Y, SEL)
SEL)
processes and begin
begin
always produce a if
if (SEL)
(SEL) then
then
Boolean result ZZ <=
<= X;
X;
else
else
ZZ <=
<= Y;
Y;
end
end if
if ;;
end
end process;
process;
end
end BEHAVE;
BEHAVE;

User-Defined Enumeration Types
Allow designers to specify exact values for operation
Useful for state machine designs
architecture
architecture MACHINE
MACHINE of
of TRAFFIC_LIGHT
TRAFFIC_LIGHT is
is
type
type STATE
STATE is
is (RED,
(RED, YELLOW,
YELLOW, GREEN);
GREEN);
signal
signal CURRENT_STATE,
CURRENT_STATE, NEXT_STATE:
NEXT_STATE: STATE;
STATE;
begin
begin
The data type of two signals (current_state and

next_state) is the user-defined type called state

IEEE 1164-1993 Standard Logic Package
std_logic_1164 must be declared
library
library ieee;
ieee;
use
Supported by most VHDL simulators and synthesis tools

Includes a multi-value logic system
Nine signal strengths defined
Can resolve multiple signal drivers
Generally used instead of bit/bit_vector

std_logic_1164 Types
std_ulogic, std_ulogic_vector
Unresolved type
Only one signal driver allowed
std_logic, std_logic_vector
Resolved type - multiple drivers allowed
Used when tri-state logic required
std_logic is best choice for behavioral

“Legal” Values for std_logic Type
Unresolved data type
type STD_ULOGIC is (
'U' -- Uninitialized
'X' -- Forcing Unknown
'0' -- Forcing Low (driven)
'1' -- Forcing High (driven)
'Z' -- High Impedance
Synthesizable
'W' -- Weak Unknown for
'L' -- Weak Low (read) FPGA
'H' -- Weak High (read)
'-' -- Don't Care
);

Operators
Six classes
LOGIC OPERATOR and , or , nand , nor , xor

RELATIONAL OPERATOR = , /= , < , <= , > , >=
ADDING OPERATOR +,-,&
SIGN +,-
MULTIPLYING OPERATOR * , / , mod , rem
MISCELLANEOUS OPERATOR ** , abs , not
PRECEDENCE ORDER

Arithmetic Operators
Require opening the following packages:
library
library ieee;
ieee;
use
use
use ieee.std_logic_arith.all;
ieee.std_logic_arith.all;
use
use ieee.std_logic_signed.all;
ieee.std_logic_signed.all; Depending on
--OR
--OR whether signed or
use
use ieee.std_logic_unsigned.all;
ieee.std_logic_unsigned.all; unsigned arithmetic
is used.
May be used on real, integer, bit or std_logic types.

Operators: Example
library
library ieee;
ieee;
use
entity
entity LOGIC
LOGIC isis
port
port (A,
(A, B,
B, C:
C: inin std_logic;
std_logic;
Y,
Y, ZZ :: out
out std_logic);
std_logic);
end
end LOGIC;
LOGIC;
architecture
architecture BEHAVE
BEHAVE of
of LOGIC
LOGIC is
is
begin
begin
ZZ <=
<= AA and
and B;
B;
YY <=
<= (A
(A and
and B)
B) or
or not
not C;
C; A
B
end
end BEHAVE;
BEHAVE; C Y
( ) prevent ambiguity. Otherwise this could be:

(A and B) or not C A
OR
B
Y
C
A and (B or not C)

Arithmetic Operators: Example
4-bit multiplier
library
library ieee;
ieee;
use
use
use ieee.std_logic_unsigned.all;
ieee.std_logic_unsigned.all;
entity
entity MULT
MULT is
is
A
port(A:
port(A: in
downto 0);
0);
* B:
B: in
downto 0);
0);
B Y:
Y: out
downto 0));
0));
end
end MULT;
MULT;
architecture
architecture BEHAVE
BEHAVE of
of MULT
MULT is
is
begin
begin
YY <=
<= AA ** B;
B;
end
end BEHAVE;
BEHAVE;

Concatenation: Example
8-bit adder with 9-bit result
library
library ieee;
ieee;
use
use
use ieee.std_logic_signed.all;
ieee.std_logic_signed.all;
entity
entity ADDER
ADDER is
is
A port(
port(
A,
A, BB :: in
downto 0);
0);
+ SS :: out
downto 0)
0)
B );
);
end
end adder;
adder;
architecture
architecture BEHAVIORAL
BEHAVIORAL of
of ADDER
ADDER is
is
begin
begin
SS <=
<= (A(7)
(A(7) && A)
A) ++ (B(7)
(B(7) && B);
B);
end
end BEHAVIORAL;
BEHAVIORAL;

Operands: Attribute Names
A Data Attached to VHDL Objects
S'LEFT : Index of the leftmost element of the data type
S'RIGHT : Index of the rightmost element of the data type
S'HIGH : Index of the highest element of the data type
S'LOW : Index of the lowest element of the data type
S'RANGE : Index range of the data type
S'REVERSE_RANGE : Reverse index range
S'LENGTH : Number of elements of an array
S'EVENT : A change value at the current simulation time
S'STABLE : No change value at the current simulation time

VHDL Statements
Concurrent Statements
Concurrent Signal Assignment
Conditional Signal Assignment
Selected Signal Assignment
Block Statement
Concurrent Assertion Statement
Process Statement

Concurrent Statements
Execute at the same time
Signals impacted by an event are resolved in the same
simulation time
Aout
Aout <=
<= A; A; Signal Assignment
Y0
Y0 <=
<= AA and
and B;
B; Boolean equations
Y1
Y1 <=
<= ‘1’
‘1’ when
when AA == ‘1’
‘1’ else
else ‘0’;
‘0’; Conditional assignments
u1:
u1: INV
INV port
port map
map (ina
(ina =>
=> A,
A, outb
outb =>
=> B);
B); Component instantiation
p1:
p1: process
process (CLK,
(CLK, A)A)
begin
begin
if
if (clk’event
(clk’event and and clk
clk == ‘1’)
‘1’) then
then
if
if (A(A == ‘1’)
‘1’) then
then Process
YY <=
<= data_in
data_in ;;
end
end if;
if;
end
end if if ;;
end
end process
process ;;
If an event occurs on A, then all
these statements will execute
at the same time (concurrently)
Concurrent Signal Assignment
Always used within an architecture
Change on the right-hand side causes immediate
reassignment to the left-hand side
Used in behavioral and structural descriptions
Signals are associated with TIME
With "after", the assignment is scheduled to a future
simulation time
Without "after", the assignment is scheduled at a DELTA
TIME after the current simulation time
Assignment operator is <=
target <= expression [ after time_expression ] ;

Signals with Multiple Drivers
Y <= A; -- in process1
and, Y <= B; -- in process2
Concept of a Resolution Function; attached to a signal or a
type, and is called every time the value of signal needs to be
determined -- that is every time a driver changes value
What is the value of the signal in such a case?

Conditional Signal Assignment
Concurrent Version of IF statement
Condition/expression except for last expression
One and only one of the expressions is used at a given time
Syntax:
Example: target
target <=
<= first_value
first_value when
when (condition1)
(condition1) else
else
second_value
second_value when
when (condition1)
(condition1) else
else
third_value;
third_value;
YY <=
<= IN1
IN1 when
when SS == ‘0’
‘0’ else
else
“else” clause is required
IN2
IN2 when
when SS == ‘1’
‘1’ else
else
‘0’;
‘0’;
YY <=
<= “00”
“00” when
when COUNT
COUNT >=
>= 88 else
else
“11”;
“11”;

Selected Signal Assignment
Concurrent Version of CASE Statement
Syntax:
with
with EXPRESSION
EXPRESSION
TARGET
TARGET <=
<= {expression
{expression when
when choices};
choices};
Example:
“with” selection must be a signal, not an expression
with
with DATAIN
DATAIN select
select --
-- selected
selected signal
signal assignment
assignment
YY <=
<= IN0
IN0 when
when “00”,
“00”,
Note that
commas are
IN1
IN1 when
when “01”,
“01”,
IN2
IN2 when
when “10”,
“10”, used here.
IN3
IN3 when
when others;
others;

When-Else Example: Tri-State Buffers
library
library ieee;
ieee;
use
entity
entity MY_TRI
MY_TRI is
is A(0) Y(0)
port(A:
port(A: in
downto 0);
0);
EN
EN:
EN: in
in std_logic;
std_logic;
Y:
Y: out
downto 0));
0)); A(1) Y(1)
end
end MY_TRI;
MY_TRI; EN
A(2) Y(2)
architecture
architecture BEHAVE
BEHAVE of
of MY_TRI
MY_TRI is
is
begin
begin EN
YY <=
<= AA when
when EN
EN == ‘1’
‘1’ else
else
A(3) Y(3)
(others
(others =>
=> ‘Z’)
‘Z’) ;;
end
end BEHAVE;
BEHAVE; EN
means Y <= “ZZZZ”;

With-Select Example: Truth Table
library
library ieee;
ieee;
use
A B C Y
entity
entity TRUTH_TABLE
TRUTH_TABLE is is
port(A,
port(A, B,B, C:
C: inin std_logic;
std_logic;
0 0 0 1
Y:
Y: out
out std_logic)
std_logic) ;;
0 0 1 0
end
end TRUTH_TABLE;
TRUTH_TABLE;
0 1 0 1
architecture
architecture BEHAVE
BEHAVE of
of TRUTH_TABLE
TRUTH_TABLE is
is
0 1 1 0
signal
signal S1:
downto 0);
0);
1 0 0 1
begin
begin
1 0 1 0
S1
S1 <=
<= AA && BB && C;
C; --
-- concatenate
concatenate A,
A, B,
B, CC
1 1 0 - with
with S1
S1 select
select
1 1 1 - YY <=
<= ‘1’
‘1’ when
when “000”
“000” || “010”
“010” || “100”
“100” ,,
‘0’
‘0’ when
when “001”
“001” || “011”
“011” || “101”,
“101”,
‘-’ means don’t care ‘-’
‘-’ when
when others;
others;
end
end BEHAVE;
BEHAVE;
“|” means OR only when
used in “with” or “case”

Block Statement
Used in synchronous descriptions
latch
latch :: block
block (( CLK
CLK == '1'
'1' ))
begin
begin
QQ <=
<= GUARDED
GUARDED DD ;;
end
end block
block latch
latch ;;
D Q
LATCH
CLK

Assertion Statement
If the condition is false, it reports a diagnostic message
Useful for detecting condition violation during simulation
Not used in synthesis
Syntax:
assert
assert condition
condition
[[ report
report error_message
error_message ]]
[[ severity
severity severity_level
severity_level ]] ;;

Process Statement
A Set of Sequential Statements
All processes in a design executes CONCURRENTLY
At a given time, ONLY ONE sequential statement executed
within each process
Communicates with the rest of a design through signals
Syntax:
[[ label
label :: ]] process
process [[ (( sensitivity_list
sensitivity_list )) ]]
{{ process_declarative_part
process_declarative_part }}
begin
begin
{{ sequential_statements
sequential_statements }}
end
end process
process [[ label
label ]] ;;

Process Statement (cont’d)
A Pseudo Infinite Loop
A Synchronization Mechanism is Needed
process
begin
sequential_statement_1 ;
sequential_statement_2 ;
-----------
sequential_statement_n ;
end process;
Sensitivity list or wait statement will be used

Process With Sensitivity List
Process label
(recommended) Sensitivity list
PQR:process (A, B, C)
begin
X <= A and B;
if (B = ‘1’) then
Statements
Y <= A xor C;
executed
else
sequentially
Y <= A xnor C;
end if;
end process PQR;
End statement matches process label

Process With Wait Statements
NOTE! No sensitivity list

AORB: process
begin
wait until rising_edge(clk); WAIT condition
if (B = ‘1’) then is on signals only
Y <= A xor C;
else Assignments execute
Y <= A xnor C; when their WAIT
end if ; condition is satisfied
end process AORB;

Sequential Statements in Processes
Executed line-by-line inside of a process or sub-program
Typically include:
WAIT statements
Signal and variable assignments
Conditionals like IF-THEN-ELSE, CASE, LOOP
Support other advanced statements

Variable Assignment Statement
Always executed in Zero Simulation Time
Used as temporary storages
Can not be seen by other concurrent statements
Syntax:
target_variable
target_variable :=
:= expression
expression ;;

Signal Assignment Statement
Defines a Driver of the Signal
Within a process, Only One driver for each signal
When assigned in multiple processes, it has Multiple
Drivers. A Resolution Function should be defined
Syntax:
target_signal
target_signal <=
<= [[ transport
transport ]] expression
expression [[ after
after time
time ]] ;;

Inertial & Transport Delay Models
Default mode is Inertial
Inertial is useful in modeling devices that ignore spikes on
the inputs

Inertial Delay Model
This is the default mode
It is useful in modeling devices that ignore spikes on the
inputs
signal S
signal S :: BIT
BIT :=
:= '0'
'0' ;; signal S
signal S :: BIT
BIT :=
:= '0'
'0' ;;
process
process process
process
SS <=
<= '1'
'1' after
after 55 ns
ns ;; SS <=
<= '0'
'0' after
after 10
10 ns
ns ;;
SS <=
<= '0'
'0' after
after 10
10 ns
ns ;; SS <=
<= '1'
'1' after
after 55 ns
ns ;;
end ;
end ; end ;
end ;
Overrides the first Overrides the first

assignment assignment

Transport Delay Model
Signals are propagated without filtering
signal S
signal S :: BIT
BIT :=
:= '0'
'0' ;; signal S
signal S :: BIT
BIT :=
:= '0'
'0' ;;
process
process process
process
SS <=
<= '1'
'1' after
after 55 ns
ns ;; SS <=
<= '0'
'0' after
after 10
10 ns
ns ;;
SS <=
<= '0'
'0' after
after 10
10 ns
ns ;; SS <=
<= '1'
'1' after
after 55 ns
ns ;;
end ;
end ; end ;
end ;
5 10 time 5 10 time

If-Then-Else Statement
if
if CONDITION
CONDITION then
then
--sequential
--sequential statements
statements
end
end if;
if;
if
if CONDITION
CONDITION then
then
--sequential
statements
else
else
--sequential
statements
end
end if;
if;
if
if CONDITION
CONDITION then
then
--sequential
statements
More than one elsif allowed elsif
elsif CONDITION
CONDITION then
then
“elsif” is one word --sequential
statements
elsif
elsif CONDITION
CONDITION then
then
--sequential
statements
Only one else allowed else
else
--
-- sequential
sequential statements
statements
“end if” is two words end
end if;
if;

If-Then-Else Example
library
library ieee;
ieee;
use
entity
entity IF_MUX
IF_MUX is is
port IF implies Priority
port (C,
(C, D,D, E,
E, FF :: in
in std_logic;
std_logic;
SS :: in
downto 0);
0);
POUT
POUT :: out
out std_logic);
std_logic);
end
end IF_MUX;
IF_MUX;
architecture
architecture BEHAVE
BEHAVE ofof IF_MUX
IF_MUX is
is f
begin
begin
ONE:
ONE: process
process (S,(S, C,
C, D,
D, E,
E, F)
F) e
begin
begin
if
if (S
(S == “00”)
“00”) then
then d pout
POUT
POUT <=<= C;
C; s = 10 c
elsif
elsif (S(S == “01”)
“01”) then
then
POUT
POUT <=<= D;
D;
elsif
elsif (S(S == “10”)
“10”) then
then s = 01
POUT
POUT <=<= E;
E;
else
else POUT
POUT <=
<= F;
F; s = 00
end
end if
if ;;
end
end process
process ONE;
ONE;
end
end BEHAVE;
BEHAVE;

Case Statement
case
case (SELECTOR)
(SELECTOR) is
is
when
when value
value =>
=>
--sequential
statements
when
when value1
value1 || value2
value2 || value3
value3 =>
=>
--sequential
statements
when
when value1
value1 to
to value2
value2 =>
=>
--sequential
statements
when
when others
others =>
=>
--sequential
statements
end
end case;
case;
‘when SELECTOR = value, then ...’

‘when SELECTOR = value1 OR value2 OR value 3, then …’’
‘when SELECTOR falls within the range from value1 to value2, then ...’’
‘when SELECTOR = any other value, then …’

Case Example: 4-to-1 Mux
library
library ieee;
ieee;
use
entity
entity CASE_MUX
CASE_MUX is is
port
port (C,
(C, D,D, E,
E, F:
F: in
in std_logic;
std_logic; 4:1 Multiplexer
SS :: in
downto 0);
0);
MUX_OUT
MUX_OUT :: out
out std_logic
std_logic );
);
end
end CASE_MUX;
CASE_MUX;
architecture
architecture BEHAVE
BEHAVE of
of CASE_MUX
CASE_MUX is
is C
begin
begin D MUX_OUT
mux1:
mux1: process
process (S,
(S, C,
C, D,
D, E,
E, F)
F) E
begin
begin F
case
case SS is
is
when
when “00”
“00” =>
=> MUX_OUT
MUX_OUT <=
<= C;
C;
when
when “01”
“01” =>
=> MUX_OUT
MUX_OUT <=
<= D;
D; S(1:0)
when
when “10”
“10” =>
=> MUX_OUT
MUX_OUT <=
<= E;
E;
when
when others
others =>
=> MUX_OUT
MUX_OUT <=
<= F;
F;
end
end case;
case;
end
end process
process mux1;
mux1;
end
end BEHAVE;
BEHAVE;

Case Example: Bi-Directional Buffers
library
library ieee;
ieee;
use
entity
entity BIBUF
BIBUF isis
port
port (A,
(A, E:E: in
in std_logic;
std_logic;
YY :: inout
inout std_logic;
std_logic;
BB :: out
out std_logic
std_logic ););
end
end BIBUF
BIBUF ;; E
architecture
architecture BEHAVE
BEHAVE ofof BIBUF
BIBUF is
is
begin
begin A Y
ONE:process
ONE:process (A,E)
(A,E)
begin
begin B
case
case EE isis
when
when ‘1’
‘1’ =>
=> YY <=
<= A;
A;
when
when ‘0’
‘0’ =>
=> YY <=
<= ‘Z’;
‘Z’;
when
when others
others =>=> YY <=
<= ‘X’;
‘X’;
end
end case;
case;
end
end process
process ONE;
ONE;
BB <=
<= Y;
Y;
end
end BEHAVE;
BEHAVE;

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2065-15

Advanced Training Course on FPGA Design and VHDL for Hardware

26 October - 20 November, 2009

FPGA Architectures & VHDL

 Programmable logic & FPGA architectures

 Emerging technologies and future opportunities.

Actel Corporation Confidential © 2009 2

A standard HDL from the System

Actel Corporation Confidential © 2009 3

Actel Corporation Confidential © 2009 4

Actel Corporation Confidential © 2009 5

Actel Corporation Confidential © 2009 6

Abstraction Levels VHDL Architectures

Behavioral How it works

Gate Structural How it is connected

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EX: C language assignment EX: VHDL signal assignment

X = A & B; X <= A and B;

X is computed out of A and A PERMANENT link is created

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EX: C language assignment EX: VHDL signal assignment

X = A & B; X <= A and B;

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Required entity entity_name is

Required end [entity_name];

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Actel Corporation Confidential © 2009 15

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architecture architecture_name of entity_name is

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Actel Corporation Confidential © 2009 20

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Actel Corporation Confidential © 2009 25

Actel Corporation Confidential © 2009 26

STD Library Always visible! - no

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Is this a structural or behavioral description ?

Actel Corporation Confidential © 2009 29

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Actel Corporation Confidential © 2009 36

Actel Corporation Confidential © 2009 37

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The data type of two signals (current_state and

Actel Corporation Confidential © 2009 39

Programmable logic & FPGA architectures

Emerging technologies and future opportunities.

Supported by most VHDL simulators and synthesis tools

Sensitivity list or wait statement will be used