36 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 35, NO.

1, JANUARY/FEBRUARY 1999

Multilevel Converters for Large Electric Drives

Leon M. Tolbert, Senior Member, IEEE, Fang Zheng Peng, Senior Member, IEEE,
and Thomas G. Habetler, Senior Member, IEEE

Abstract—This paper presents transformerless multilevel con- the dc voltage to variable frequency and variable voltage for
verters as an application for high-power and/or high-voltage motor speed control.
electric motor drives. Multilevel converters: 1) can generate near- Motor damage and failure have been reported by industry
sinusoidal voltages with only fundamental frequency switching;
2) have almost no electromagnetic interference or common-mode as a result of some ASD inverters’ high-voltage change rates
voltage; and 3) are suitable for large voltampere-rated motor , which produced a common-mode voltage across the
drives and high voltages. The cascade inverter is a natural fit for motor windings. High-frequency switching can exacerbate the
large automotive all-electric drives because it uses several levels problem because of the numerous times this common mode
of dc voltage sources, which would be available from batteries voltage is impressed upon the motor each cycle. The main
or fuel cells. The back-to-back diode-clamped converter is ideal
where a source of ac voltage is available, such as in a hybrid problems reported have been “motor bearing failure” and
electric vehicle. Simulation and experimental results show the “motor winding insulation breakdown” because of circulat-
superiority of these two converters over two-level pulsewidth- ing currents, dielectric stresses, voltage surge, and corona
modulation-based drives. discharge [2]–[4].
Index Terms—Cascade inverter, common-mode voltage, diode- Only recently have motor insulation failures become a
clamped inverter, electric vehicle, motor drive, multilevel con- problem with some ASD’s because the increased switching
verter, multilevel inverter. speed of contemporary power semiconductor devices causes
steep voltage wavefronts to appear at the motor terminals. The
I. INTRODUCTION voltage change rate sometimes can be high enough
to induce corona discharge between the winding layers.
Present power semiconductors can be turned on and off
A. Background within 1 s for 600 V and higher voltages which can generate
broadband electromagnetic interference (EMI). These high-
D ESIGNS FOR heavy-duty electric and hybrid-electric
vehicles (EV’s) that have large electric drives will require
advanced power electronic inverters to meet the high power
speed semiconductor switches allow faster PWM carrier fre-
quencies. Although the high-frequency switching can increase
demands ( 250 kW) required of them. Development of large the motor running efficiency and is well above the acoustic
electric drive trains for these vehicles will result in increased noise level, the associated dielectric stresses between
fuel efficiency, lower emissions, and likely better vehicle insulated winding turns are also greatly increased.
performance (acceleration and braking). Some PWM-controlled inverters can also cause large in-
Transformerless multilevel inverters are uniquely suited stantaneous common-mode voltages to appear at the motor
for this application because of the high voltampere ratings terminals. These common-mode voltages appear across the
possible with these inverters [1]. For EV’s, a cascaded H- motor shaft to ground and induce bearing currents, which lead
bridges inverter can be used to drive the traction motor from to erosion of the bearing material and early mechanical failure.
a set of batteries or fuel cells. Where generated ac voltage Multilevel inverters overcome these problems because their
is available, such as from an alternator or generator, a back- individual devices have a much lower per switching,
to-back diode-clamped converter can convert this source to and they operate at high efficiencies because they can switch
variable-frequency ac voltage for the driven motor. at a much lower frequency than PWM-controlled inverters.
Multilevel inverters also solve problems with some present
two-level pulsewidth modulation (PWM) adjustable-speed B. Multilevel Inverters
drives (ASD’s). ASD’s usually employ a front-end diode The multilevel voltage source inverters’ unique structure
rectifier to convert utility ac voltage to dc voltage and an allows them to reach high voltages with low harmonics without
inverter with PWM-controlled switching devices to convert the use of transformers or series-connected synchronized-
switching devices. The general function of the multilevel
Paper IPCSD 98–68, presented at the 1998 IEEE Applied Power Electronics inverter is to synthesize a desired voltage from several levels
Conference and Exposition, Anaheim, CA, February 15–19, and approved of dc voltages. For this reason, multilevel inverters can easily
for publication in the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by provide the high power required of a large electric drive.
the Industrial Drives Committee of the IEEE Industry Applications Society.
Manuscript released for publication September 8, 1998. As the number of levels increases, the synthesized output
L. M. Tolbert and F. Z. Peng are with Oak Ridge National Laboratory, Oak waveform has more steps, which produces a staircase wave
Ridge, TN 37831-8038 USA. that approaches a desired waveform. Also, as more steps are
T. G. Habetler is with the School of Electrical and Computer Engineering,
Georgia Institute of Technology, Atlanta, GA 30332-0250 USA. added to the waveform, the harmonic distortion of the output
Publisher Item Identifier S 0093-9994(99)00454-5. wave decreases, approaching zero as the number of levels in-
0093–9994/99$10.00  1999 IEEE

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TOLBERT et al.: MULTILEVEL CONVERTERS FOR LARGE ELECTRIC DRIVES 37

creases. As the number of levels increases, the voltage that can

be spanned by summing multiple voltage levels also increases.
The structure of the multilevel inverter is such that no voltage
sharing problems are encountered by the active devices.
Researchers have proposed three main types of trans-
formerless multilevel inverters thus far, the diode-clamped
inverter, the flying-capacitor inverter, and the cascade inverter.
Proposed uses for these converters have included static var
compensation [5]–[12], back-to-back high-voltage intertie
[13]–[15], and ASD’s [15]–[20].
Using multilevel inverters as drives for electric motors is a
much different application than for the utility applications for
which they were originally developed. Only reactive power
flows between the converter and the system in static var
compensation, whereas the converter must handle bidirectional
real power flow in the case of motor drives.
Three-, four-, and five-level rectifier-inverter drive systems
that have used some form of multilevel PWM as a means to
control the switching of the rectifier and inverter sections have
been investigated in the literature [16]–[20]. Multilevel PWM
has lower than that experienced in some two-level
PWM drives because switching is between several smaller Fig. 1. Single-phase structure of a multilevel cascaded H-bridges inverter.
voltage levels. However, switching losses and voltage total
harmonic distortion (THD) are still relatively high for these inverter with five SDSC’s and five full bridges is shown in
proposed schemes; the output voltage THD was reported to Fig. 2. The phase voltage .
be 19.7% for a four-level PWM inverter without any output The output voltage of the inverter is almost sinusoidal, and
filters [19]. it has less than 5% THD with each of the H-bridges switching
This paper proposes two multilevel inverter configurations only at fundamental frequency. Each H-bridge unit generates
where devices are switched only at the fundamental frequency a quasi-square waveform by phase shifting its positive and
and the inverter output line voltage THD is 5% without the use negative phase legs’ switching timings. Fig. 2(b) shows the
of any filtering components. In addition, a control scheme will switching timings to generate a quasi-square waveform. Note
be demonstrated in the multilevel diode-clamped converter that that each switching device always conducts for 180 (or 1/2
obtains well-balanced voltages across the dc-link capacitors. cycle), regardless of the pulsewidth of the quasi-square wave.
This switching method makes all of the active devices’ current
II. CASCADED H-BRIDGES INVERTER stress equal.
For a stepped waveform such as the one depicted in Fig. 2
with steps, the Fourier transform for this waveform is as
A. General Structure and Operation
follows:
A cascaded multilevel inverter consists of a series of H-
bridge (single-phase full-bridge) inverter units. The general
function of this multilevel inverter is to synthesize a desired
voltage from several separate dc sources (SDCS’s), which may where (1)
be obtained from batteries, fuel cells, or solar cells. Fig. 1
shows a single-phase structure of a cascade inverter with From (1), the magnitudes of the Fourier coefficients when
SDCS’s [6]. Each SDCS is connected to a single-phase full- normalized with respect to are as follows:
bridge inverter. Each inverter level can generate three different
voltage outputs, , and , by connecting the dc
source to the ac output side by different combinations of the where (2)
four switches, , and . To obtain , switches The conducting angles can be chosen such that
and are turned on. Turning on switches and yields the voltage total harmonic distortion is a minimum. Normally,
. By turning on and or and , the output these angles are chosen so as to cancel the predominant lower
voltage is . frequency harmonics [6], [12]. For the 11-level case in Fig. 2,
The ac outputs of each of the different level full-bridge the 5th, 7th, 11th, and 13th harmonics can be eliminated with
inverters are connected in series such that the synthesized the appropriate choice of the conducting angles. One degree of
voltage waveform is the sum of the inverter outputs. The freedom is used so that the magnitude of the output waveform
number of output phase voltage levels in a cascade inverter is corresponds to the reference amplitude modulation index
defined by , where is the number of dc sources. which is defined as , where is the amplitude
An example phase voltage waveform for an 11-level cascaded command of the inverter output phase voltage, and

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38 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 35, NO. 1, JANUARY/FEBRUARY 1999

The set of nonlinear transcendental equations (3) can be

solved by an iterative method such as the Newton–Raphson
method. For example, using a modulation index of 0.8
obtains

This means that, if the inverter output is symmetrically

switched during the positive half cycle of the fundamental
voltage to at 6.57 , at 18.94 , at 27.18 ,
at 45.14 , and at 62.24 , and similarly in the
negative half cycle to at 186.57 , at 198.94 ,
at 207.18 , at 225.14 , and at 242.24 ,
the output voltage of the 11-level inverter will not contain the
5th, 7th, 11th, and 13th harmonic components.
From Fig. 2, note that the duty cycle for each of the voltage
levels is different. If this same pattern of duty cycles is used
on a motor drive continuously, then the level-1 battery (or
other SDCS) is cycled on for a much longer duration than
the level-5 battery. This means that the level-1 battery will
discharge much sooner than the level-5 battery. However, by
(a) using a switching pattern-swapping scheme among the various
levels every 1/2 cycle, as shown in Fig. 3, all batteries will be
equally used (discharged) or charged.
The combination of the 180 conducting method [Fig. 2(b)]
and the pattern-swapping scheme (Fig. 3) make the cascade
inverter’s voltage and current stresses the same and keeps
the batteries’ charge state balanced. Identical H-bridge in-
verter units can be utilized, thus improving modularity and
manufacturability and greatly reducing production costs.

B. Three-Phase Motor Drive

For a three-phase system, the output voltages of three single-
phase cascaded inverters can be connected in either a wye or
delta configuration. Fig. 4 illustrates the connection diagram
for a wye-configured 11-level converter using cascaded invert-
ers with five SDCS’s per phase. In the motoring mode, power
flows from the batteries through the cascade inverters to the
motor. In the charging mode, the cascade converters act as
rectifiers, and power flows from the charger (ac source) to the
batteries.
(b) Fig. 5 shows the system configuration and control block
Fig. 2. Waveforms and switching method of the 11-level cascade inverter. diagram of an ASD using an 11-level cascade inverter. The
duty cycle lookup table contains switching timings to generate
is the maximum attainable amplitude of the converter, i.e., the desired output voltage, as shown in Fig. 2. The five
[15]. Let the equations from (2) be as follows: switching angles are calculated off-line
to minimize harmonics for each modulation index, .
A prototype three-phase 11-level wye-connected cascaded
inverter has been built using insulated gate bipolar transistors
(IGBT’s) as the switching devices. A battery bank of 15
SDCS’s of 48 Vdc each fed the inverter (5 SDCS’s per phase).
The control of the inverter was via a 32-bit digital signal
processor. The switching timing angles
were calculated off-line for the following modulation indexes:
. A table of ten switching patterns
(3) corresponding to these modulation indexes was stored in

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TOLBERT et al.: MULTILEVEL CONVERTERS FOR LARGE ELECTRIC DRIVES 39

Fig. 3. Switching pattern swapping of the 11-level cascade inverter for balancing battery charge.

Fig. 4. System configuration of an EV motor drive using a cascade inverter.

Fig. 5. System configuration of an ASD using the cascade inverter.

the controller as 1024 states per cycle. A constant volt- III. BACK-TO-BACK DIODE-CLAMPED CONVERTER DRIVE
age/frequency control technique was applied to the motor drive
system. As a user interface, a potentiometer was adjusted While cascade inverters are ideal where separate dc sources
to apply an external 0–3-V signal to the controller. The are available, in most instances, an ac voltage source is the
0–3-V signal mapped directly to a 0–60-Hz fundamental only convenient power supply. For these cases, a multilevel
frequency for the gate signals sent to the inverter. Also, back-to-back diode-clamped converter can best interface with
the switching patterns corresponding to the various modula- the source of ac power and yet still meet the high-power and/or
tion indexes were mapped from the 0–3-V external control high-voltage requirements of the driven motor.
signal. Two six-level diode-clamped inverters connected back-to-
Fig. 6 shows experimental waveforms of the 11-level back are shown in Fig. 7. The dc bus for these two in-
battery-fed cascade inverter prototype driving a 208-V three- verters consists of a series of electric energy storage de-
phase induction motor at 50% and 80% rated speed using the vices—batteries or capacitors. The voltage across each storage
aforementioned fundamental frequency switching scheme. As device is . The voltage stress across each switching device
can be seen from the waveforms, both the line–line voltage is limited to through the clamping diodes.
and current are almost sinusoidal. EMI and common-mode
voltage are also much less than what would result from a A. General Structure and Operation
two-level PWM inverter because of the inherently low Table I lists the voltage output levels possible for one phase
(21 times less than a two-level drive) and sinusoidal voltage of the diode-clamped inverter using the negative dc rail as
output. a reference voltage. State condition 1 means the corresponding

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40 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 35, NO. 1, JANUARY/FEBRUARY 1999

such that each blocking diode has the same voltage rating
as the active switches, will require diodes in series;
consequently, the number of diodes required for each phase
is . Thus, the number of blocking diodes
are quadratically related to the number of levels in a diode-
clamped converter [13]–[15].

B. Experimental Results
A six-level back-to-back 10-kW diode-clamped converter
prototype that was designed to operate at a three-phase line
voltage of 208 V has been built and experimentally tested as an
ASD for an induction motor load. The controllable switching
devices used for the converter were 100-V 100-A MOSFET’s.
Each internal dc level of the converter had a capacitance of
6.72 mF.
Fig. 9 shows the source voltage , the source current
(a)
, drawn by the converter, the inverter output load voltage
, and the load current , drawn by a 5-hp induction
motor operating at 75% rated speed. This prototype diode-
clamped rectifier drew a source current that had a THD of 3%
and could be controlled such that the input power factor was
1.0. The output voltage at the motor terminals had a THD that
varied between 4.5%–5.3%, and the converter output current
had a THD of 3%.
Additionally, the experiment shows that the output line
voltage is reduced by 11 times with the six-level
converter as compared to a traditional two-level PWM drive.
The dramatic reduction in by one order in magnitude
and two orders in repetition (switching frequency) can prevent
motor windings and bearings from failure. This 11-step stair-
case output voltage waveform approaches a sinewave, thus
having no common-mode voltage and no voltage surge to the
motor windings.
(b)
Fig. 6. Experimental waveforms of a battery-fed cascade inverter prototype C. Efficiency
driving an induction motor at (a) 50% rated speed and (b) 80% rated speed.
To compare the efficiencies of a multilevel inverter oper-
ating with fundamental frequency switching and a two-level
switch is on, and 0 means the switch is off. Note that each inverter using PWM, the losses in the two inverters have to
active device is only switched once per cycle. Each phase be characterized.
has five complementary switch pairs such that turning on one The losses in an inverter can be described by
of the switches of the pair requires that the other switch be
turned off. The complementary switch pairs for phase leg (4)
are , and where is the conducting loss and is the switching loss.
. In the fundamental frequency-controlled multilevel inverter,
Fig. 8 shows the voltage waveform for one phase of a six- the switching power losses can be approximated by
level inverter. The line voltage consists of a phase-leg
voltage and a phase-leg voltage. The resulting line voltage - (5)
is an 11-level staircase waveform. This means that an -level
diode-clamped inverter has an -level output phase voltage where is the frequency of the modulation, or reference,
and a -level output line voltage [15]. waveform. The switching power losses in a two-level PWM
Although each active switching device is only required to inverter can be approximated by
block a voltage level of , the clamping diodes require (6)
-
different voltage ratings for reverse voltage blocking. Using
phase of Fig. 7 as an example, when all the lower switches where is the frequency of the PWM carrier waveform [21].
– are turned on, must block four voltage levels, If and are assumed to be the same for the active devices
or . Similarly, must block , must block in the multilevel inverter and two-level PWM inverter, the
, and must block . If the inverter is designed difference in (5) and (6) is the factor , which is known as

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TOLBERT et al.: MULTILEVEL CONVERTERS FOR LARGE ELECTRIC DRIVES 41

Fig. 7. Six-level diode-clamped back-to-back converter structure for adjustable-speed motor drive system.

TABLE I
DIODE-CLAMPED SIX-LEVEL CONVERTER VOLTAGE
LEVELS AND CORRESPONDING SWITCH STATES

Fig. 9. Experimental voltage and current waveforms at the input and output
of the back-to-back diode-clamped converter prototype.

The on-state voltage drops of the IGBT and diode,

and , consist of voltage drops at zero-current condition,
and , and the voltage drops because of the device
current flowing through resistive elements and .
These device-dependent parameters can be obtained from
manufacturers’ data sheets [22].
Fig. 8. Voltage waveform for six-level diode-clamped inverter.
In a three-phase full-bridge two-level PWM inverter, the
conduction losses, for one active switching device and one
the frequency modulation index . Therefore, the switching antiparallel diode, respectively, are given by
losses in a two-level PWM inverter would be times the
switching losses in a comparable multilevel inverter using
fundamental frequency switching techniques. -
A simplified model of the solid-state devices is used in the (9)
derivation of the conduction losses in the two inverters. The
model assumes that a constant voltage drop in series with a -
linear resistive element represents the device. These simplified
models for an IGBT and diode, respectively, are given in (7) (10)
and (8) as
where is the displacement power factor of the current with
(7) respect to the fundamental of the inverter’s output voltage.
(8) The amplitude modulation index and in (9) and (10)

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42 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 35, NO. 1, JANUARY/FEBRUARY 1999

Fig. 10. Plot of inverter efficiency as a function of rated output power.

Fig. 11. Internal dc-bus voltage levels of the prototype diode-clamped

affect the percentage of current that flows through the active back-to-back converter operating at an output frequency of 32 Hz.
devices and the percentage that flows through the diodes in a
two-level inverter. The total conduction loss for all six devices underestimate the losses of the two inverters near full load and
in the full-bridge inverter can then be calculated from overestimate the losses of the inverters when they are lightly
loaded. However, the equations did fairly accurately predict
- - - (11)
the actual losses in the two inverters.
The unique structure of a multilevel inverter allows it to The multilevel converter has an efficiency greater than or
use active devices with lower voltage ratings. If the clamping equal to 96% for loads greater than 10% rated power, whereas
diodes are assumed to have the same lower voltage rating as the PWM inverter did not achieve 90% efficiency until it
the active switches, the conduction losses are approximately was loaded to greater than 30% rated power. The multilevel
converter had an efficiency greater than 98% for loads greater
- - - (12) than 40% rated power, but the PWM inverter had a maximum
efficiency of 95.6% which was achieved at a loading factor of
The amplitude modulation index and the power factor affect 95%. The efficiency for a single multilevel inverter is greater
how many clamping diodes and how many active devices than 99% over most of its operating range.
the current is flowing through on average for the multilevel
inverter.
Equation (12) for the multilevel inverter under fundamental D. Capacitor Voltage Balance
frequency switching control has an additional factor One of the keys to using multilevel converters is balancing
that (11) for the two-level PWM inverter does not have. the voltage across the series-connected dc-bus capacitors.
However, a comparison of the conducting losses for the two Capacitors will tend to overcharge or completely discharge,
inverters is largely dependent on the specific devices used in at which condition the multilevel converter will revert to a
each because the saturation voltage and diode forward three-level converter unless an explicit control is devised to
voltage are device dependent. Because the multilevel balance the capacitor charge. The method used to accomplish
inverter can use switches and diodes with lower voltage voltage balancing in this back-to-back configuration was to
ratings, these two values will usually be lower in the multilevel use proportional switching patterns for the rectifier and the
inverter. In general, the conducting losses in the two different inverter portions of the converter. Thus, the real power flow
inverters with the same power ratings will be similar in into a capacitor was the same as the real power flow out of
magnitude. the capacitor, and the net charge on the capacitor over one
Fig. 10 shows a graph comparing the efficiency of the cycle remained the same.
back-to-back multilevel converter to a typical industry PWM If the dc capacitors start to have an unbalance in their
inverter (operating with a carrier frequency of 3 kHz) as voltage levels, a modification to the previously described
a function of their fraction of rated output power. Using control scheme can be implemented, as shown by the dashed
(4)–(11) and IGBT and MOSFET manufacturers’ data sheets, lines in Fig. 5. By monitoring the voltages of each of the
the theoretical efficiency for the two different inverters was dc-link levels, minor adjustments can be made to either the
calculated at several different operating points from no load to inverter switching angles or the rectifier switching angles,
full load. The actual efficiency for each of these two inverters, which will transfer a net charge into or out of a particular
which was calculated from measured test data, was also plotted voltage level to adjust the voltage level.
in Fig. 10. The actual efficiency for the multilevel converter, in The output of the inverter was connected to a 5-hp 208-V
fact, was for two multilevel inverters connected back-to-back. three-phase induction motor. Three of the dc voltage levels are
In this instance, the theoretical equations tended to slightly shown in Fig. 11 for an output frequency of 32 Hz with the

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TOLBERT et al.: MULTILEVEL CONVERTERS FOR LARGE ELECTRIC DRIVES 43

3) Power factor is close to unity for multilevel inverters

used as a rectifier to convert generated ac to dc.
4) No EMI problem or common-mode voltage/current
problem exists.
5) No charge unbalance problem results when the convert-
ers are in either charge mode (rectification) or drive
mode (inversion).

REFERENCES
[1] L. M. Tolbert and F. Z. Peng, “Multilevel inverters for large automotive
drives,” in Conf. Rec. All Electric Combat Vehicle 2nd Int. Conf.,
Dearborn, MI, June 8–12, 1997, vol. 2, pp. 209–214.
[2] S. Bell and J. Sung, “Will your motor insulation survive a new adjustable
frequency drive?,” IEEE Trans. Ind. Applicat., vol. 33, pp. 1307–1311,
Sept./Oct. 1997.
[3] J. Erdman, R. Kerkman, D. Schlegel, and G. Skibinski, “Effect of PWM
inverters on AC motor bearing currents and shaft voltages,” IEEE Trans.
Fig. 12. Internal dc-bus voltage levels as diode-clamped converter output Ind. Applicat., vol. 32, pp. 250–259, Mar./Apr. 1996.
frequency is varied between 30–60 Hz. [4] A. H. Bonnett, “A comparison between insulation systems available for
PWM-Inverter-Fed Motors,” IEEE Trans. Ind. Applicat., vol. 33, pp.
1331–1341, Sept./Oct. 1997.
converter operating without active dc-bus voltage control. The [5] D. Divan, “Low-stress switching for efficiency,” IEEE Spectrum, vol.
33, pp. 33–39, Dec. 1996.
waveforms show that the overall bus voltage remains fairly [6] F. Z. Peng, J. S. Lai, J. W. McKeever, and J. VanCoevering, “A
constant over a cycle, and the internal bus voltages vary only multilevel voltage-source inverter with separate dc sources for static
slightly. The figure shows that, if the prototype multilevel var generation,” IEEE Trans. Ind. Applicat., vol. 32, pp. 1130–1138,
Sept./Oct. 1996.
converter is applied to loads with speed that does not change [7] F. Z. Peng and J. S. Lai, “Dynamic performance and control of a
often or rapidly, the 6.72 mF of capacitance is sufficient for static var generator using cascade multilevel inverters,” IEEE Trans.
Ind. Applicat., vol. 33, pp. 748–755, May/June 1997.
good dc-bus voltage regulation. [8] F. Z. Peng, J. W. McKeever, and D. J. Adams, “A power line conditioner
The inverter was controlled to deliver a continuously vary- using cascade multilevel inverters for distribution systems,” in Conf.
ing frequency between 30–60 Hz; it took approximately 35 s Rec. IEEE-IAS Annu. Meeting, Oct. 1997, pp. 1316–1321.
[9] N. S. Choi, G. C. Cho, and G. H. Cho, “Modeling and analysis of a static
to change between these frequency limits. Fig. 12 shows var compensator using multilevel voltage source inverter,” in Conf. Rec.
the same waveforms as Fig. 11 but for a period of 100 s. IEEE-IAS Annu. Meeting, Oct. 1993, pp. 901–908.
Without active dc-bus voltage control, the overall bus voltage [10] C. Hochgraf, R. Lasseter, D. Divan, and T. A. Lipo, “Comparison of
multilevel inverters for static var compensation,” in Conf. Rec. IEEE-IAS
varied from 258 to 304 Vdc. The internal dc voltage levels Annu. Meeting, Oct. 1994, pp. 921–928.
varied by as much as 16 Vdc. Deceleration of the motor by [11] F. Z. Peng and J. S. Lai “A static var generator using a staircase wave-
regenerative braking caused the voltage to increase from its form multilevel voltage-source converter,” in Conf. Rec. PCIM/Power
Quality Conf., Dallas, TX, Sept. 1994, pp. 58–66.
nominal value, and acceleration caused the voltage to decrease [12] R. W. Menzies and Y. Zhuang, “Advanced static compensation using
from its nominal value. The experimental results have shown a multilevel GTO thyristor inverter,” IEEE Trans. Power Delivery, vol.
10, pp. 732–738, Apr. 1995.
that active control of the dc-bus voltage by the converter or a [13] J. S. Lai and F. Z. Peng, “Power converter options for power system
larger capacitance is required for the dc voltage levels if the compatible mass transit systems,” in Conf. Rec. PCIM/Power Quality
motor speed is going to change fairly rapidly and less variation and Mass Transit System Compatibility Conf., Dallas, TX, Sept. 1994,
pp. 285–294.
in the overall dc-bus voltage is desired. [14] F. Z. Peng, J. S. Lai, J. McKeever, and J. VanCoevering, “A multilevel
voltage-source converter system with balanced dc voltages,” in Proc.
1995 IEEE Power Electronics Specialists Conf., pp. 1144–1150.
[15] J. S. Lai and F. Z. Peng, “Multilevel converters—A new breed of power
IV. CONCLUSION converters,” IEEE Trans. Ind. Applicat., vol. 32, pp. 509–517, May/June
1996.
A multilevel cascade inverter with separate dc sources and [16] J. K. Steinke, “Control strategy for a three phase ac traction drive with
a multilevel diode-clamped back-to-back converter have been three level GTO PWM inverter,” in Proc. IEEE PESC’88, 1988, pp.
431–438.
proposed for use in large electric drives. Simulation and [17] M. Klabunde, Y. Zhao, and T. A. Lipo, “Current control of a 3 level
experimental results have shown that, with a control strategy rectifier/inverter drive system,” in Conf. Rec. IEEE-IAS Annu. Meeting,
Oct. 1994, pp. 2348–2356.
that operates the switches at fundamental frequency, these [18] J. Zhang, “High performance control of a three level IGBT inverter fed
converters have low output voltage THD and high efficiency ac drive,” in Conf. Rec. IEEE-IAS Annu. Meeting, 1995, pp. 22–28.
and power factor. [19] G. Sinha and T. A. Lipo, “A four level rectifier-inverter system for
drive applications,” in Conf. Rec. IEEE-IAS Annu. Meeting, Oct. 1996,
In summary, the main advantages of using multilevel con- pp. 980–987.
verters for large electric drives include the following. [20] R. W. Menzies, P. Steimer, and J. K. Steinke, “Five-level GTO inverters
for large induction motor drives,” IEEE Trans. Ind. Applicat., vol. 30,
1) They are suitable for large voltampere-rated and/or high- pp. 938–944, July/Aug. 1994.
voltage motor drives. [21] Y. Ikeda, J. Itsumi, and H. Funato, “The power loss of the PWM
2) These multilevel converter systems have higher effi- voltage-fed inverter,” in Conf. Rec. IEEE PESC’88, 1988, pp. 277–283.
[22] J. S. Lai, R. W. Young, and J. W. McKeever, “Efficiency consideration
ciency because the devices can be switched at minimum of DC link soft-switching inverters for motor drive applications,” in
frequency. Conf. Rec. IEEE PESC’94, 1994, pp. 1003–1010.

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44 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 35, NO. 1, JANUARY/FEBRUARY 1999

Leon M. Tolbert (S’88–M’91–SM’98) received the Thomas G. Habetler (S’83–M’83–SM’92) re-

B.E.E. and M.S. degrees in electrical engineering in ceived the B.S.E.E. and M.S. degrees in electrical
1989 and 1991, respectively, from Georgia Institute engineering from Marquette University, Milwaukee,
of Technology, Atlanta, where he is currently work- WI, and the Ph.D. degree from the University of
ing towards the Ph.D. degree. Wisconsin, Madison, in 1981, 1984, and 1989,
He joined the Engineering Division of Lockheed respectively.
Martin Energy Systems in 1991 and has worked on From 1983 to 1985, he was with the Electro-
several electrical distribution projects at the three Motive Division, General Motors Corporation, as
U.S. Department of Energy plants in Oak Ridge, a Project Engineer. While there, he was involved
TN. Since 1997, he has been a Research Engineer in the design of switching power supplies and
in the Power Electronics and Electric Machinery voltage regulators for locomotive applications. He
Research Center at the Oak Ridge National Laboratory. He has published ten is currently an Associate Professor of Electrical Engineering, Georgia Institute
refereed technical papers in the areas of power quality, multilevel converters, of Technology, Atlanta. His research interests are in switching converter
and motor drives. technology and electric machine protection and drives.
Mr. Tolbert was the co-recipient of the 1991 Second Prize Paper Award of Dr. Habetler was co-recipient of the 1989 First Prize Paper Award and the
the Industrial Drives Committee of the IEEE Industry Applications Society. 1991 Second Prize Paper Award of the Industrial Drives Committee, and the
He is a Registered Professional Engineer in the State of Tennessee. 1994 Second Prize Paper Award of the Electric Machines Committee of the
IEEE Industry Applications Society. He is an Associate Editor of the IEEE
TRANSACTIONS ON POWER ELECTRONICS, and also serves as Publications Chair
of the IEEE Power Electronics Society.
Fang Zheng Peng (M’92–SM’96) was born in
Hubei Province, China. He received the B.S. degree
in electrical engineering from Wuhan University
of Hydraulic and Electrical Engineering, Wuhan,
China, in 1983 and the M.S. and Ph.D. degrees
in electrical engineering from Nagaoka University
of Technology, Nagaoka, Japan, in 1987 and 1990,
respectively.
From 1990 to 1992, he was a Research Scientist
with Toyo Electric Manufacturing Company, Ltd.,
where he was engaged in research and development
of active power filters, FACTS applications, and motor drives. From 1992 to
1994, he was an Assistant Professor at Tokyo Institute of Technology, where
he initiated a multilevel inverter project for FACTS applications and a speed-
sensorless vector control project. From 1994 to 1997, he was a Research
Assistant Professor at the University of Tennessee, Knoxville, working with
the Oak Ridge National Laboratory, Oak Ridge, TN. Since 1997 he has been
a Senior Scientist in the Power Electronics and Electric Machinery Research
Center, Oak Ridge National Laboratory.
Dr. Peng was co-recipient of the 1991 First Prize Paper Award of the
IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, the 1995 Second Prize Paper
Award and the 1996 First Prize Paper Award of the Industrial Power Converter
Committee of the IEEE Industry Applications Society. He is an Associate
Editor of the IEEE TRANSACTIONS ON POWER ELECTRONICS.

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