000-1-AN109 Standard
000-1-AN109 Standard
000-1-AN109 Standard
AN109
Microprocessor-compatible DACs
1988 Dec
Philips Semiconductors Application note
DAC products are designed to convert a digital code to an analog The internal bandgap reference (1.23V) is buffered and amplified to
signal. Since a common source of digital signals is the data bus of a provide the 5V reference output. Providing a VREF ADJ (Pin 12)
microprocessor, DAC circuits that are bus compatible ease the allows easy trimming of the reference output (Pin 13). Use of a 10k
design engineer’s interface problems. pot and series resistor, as shown in Figure 3, adjusts the gain of the
buffer amplifier, therefore varying the output reference voltage level.
This network can then be used as a full-scale output adjust. A
WHAT FEATURES MAKE A DEVICE variation in the VREF OUT of ~ 0.8V, results in a corresponding 1.6V
BUS-COMPATIBLE? variation in the full-scale output. This is more than adequate since
The five conditions which determine processor bus compatibility are: the untrimmed VREF OUT is typically within 200mV of the nominal 5V.
• Inputs must present low bus load The VREF OUT will provide a maximum of 5mA drive and can be
used as a reference voltage for other system components, if
• Addressing must be provided required.
• Inputs must be latched DATA BUS
• Logic thresholds must be compatible
• Timing requirements should be adequate (<1µs) M
Processor RAM ROM NE5018 NE5118
Philips Semiconductors’ microprocessor-compatible DACs, the
NE5018 series, meet these requirements. In addition, they provide
an internal reference source. The NE5018 provides a scaled voltage ANALOG
output, eliminating the need for an external op amp. The NE5118 is ADDRESS BUS VOLTAGE
OUT
identical to the NE5018, except it provides the user with a current LE ANALOG
I/O CURRENT
output. Figure 1 shows a typical microprocessor system with analog CONTROL LINES OUT
LOGIC LE
output using the NE5018 to provide a programmable voltage and an SELECT
SL00715
NE5118 to provide a programmable current.
Figure 1. Interfacing to a Microprocessor
The following discussions detail the operation of the NE5018 and
NE5118 series DACs.
LATCH CIRCUIT
The latch circuits of the NE5018 and NE5118 are identical. Both the
data inputs and latch enable (LE) input feature ultra-low loading for
ease of interfacing. The 8-bit data latch, controlled by the latch
enable input, is static and level sensitive. When (LE) is low, all the
latches become transparent and the output changes as the bit
SL00701
pattern changes on the data bus. When the latch enable returns to
its high state, the last set of inputs are held by the latch and a Figure 2. Latch Enable (LE) Timing Diagram for the
unique output corresponding to the binary word in the latch is NE5018 and NE5118
produced. While the latch enable is high, the latch inputs represent a Since a potential need exists to use the NE5018 and NE5118 as
high impedance load on the data bus and changes on the data bus multiplying DACs, the VREF is not connected internally, allowing the
have no effect on the DAC output. use of external reference sources. To utilize the internal reference,
The digital logic input for the NE5018 and NE5118 series DACs the VREF OUT (Pin 13) must be jumper-connected to the VREF IN (Pin
utilize a differential input logic system with a threshold level of +1.4V 14). This also makes it possible to use a common reference for
with respect to the voltage level on the digital ground pin (Pin 1). To other D/A or A/D circuits in a system.
be compatible with microprocessors, the DAC should respond in as
short a period as possible to insure full utilization of the
microprocessor and I/O data bus lines. Figure 2 gives the typical INPUT AMPLIFIER OF THE NE5018
timing requirements of the latch circuits in the NE5018 and NE5118. The DAC reference amplifier has been designed to eliminate the
need for compensation when operating from the internal reference
The voltage levels on the data bus should be stable for
or from an external reference which is buffered by an op amp or low
approximately 150ns before latch enable returns to high level. The
impedance source. Compensation is required, however, when
timing diagram shows 100ns is required for setup time and the
operating from a high impedance source. The addition of an external
information on the data lines should remain valid for another 50ns.
resistance reduces the phase margin of the amplifier making it less
stable. Compensation, when required, is a single capacitor from Pin
16 to ground.
REFERENCE INTERFACE
The NE5018 and NE5118 contain an internal bandgap voltage Figure 4 details the input reference amplifier and current ladder. The
reference which is designed to have a very low temperature voltage-to-current converter of the DAC amp will generate a 1mA
coefficient and excellent long-term stability characteristics. reference current through QR with a 5V VREF. This current sets the
1988 Dec 2
Philips Semiconductors Application note
input bias to the ladder network. Data bit 7 (DB7) Q7, when turned capacitor from VOUT to the sum node (CFF) to insure stability of the
on, will mirror this current and will contribute 1mA to the output. DB6 op amp. Typical values of CFF range from 15 to 22pF. The rated load
(Q6) will contribute of that value or 0.5mA, and so on. If all bits are of the op amp is ~ 2kΩ. For stability, the load capacitance should be
on, the output current will be minimized (50pF max).
2mA-1 LSB. The full-scale VOUT will be (IOUTRF) or 2mA-1
LSB×5k)=(10V-1 LSB)=9.961V. The overall input/output expression
for the NE5018 is:
NOTE:
DAC compensation may be required if VREF resistance exceeds 10kΩ. SL00703
Figure 4. R-2R Ladder Network Develops a Scaled Reference Current Value Into the DAC Switching Network
1988 Dec 3
Philips Semiconductors Application note
Note that the bipolar offset pin could not be used when using the NOTE:
DAC in a multiplier application since the VOUT would reflect an The absolute maximum input current should be limited to 5mA to prevent damage to the
inverted input signal. input reference amplifier.
SL00704
SL00705
1988 Dec 4
Philips Semiconductors Application note
(19)
VCC+
INT
VREF +
(13) OUT – VREF
15k
VREF (1)
(12) ADJ (10) (9) (8) (7) (6) (5) (4) (3) (2) DIGITAL
5k LE DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 GND
5k MSB LSB
LATCHES AND
SWITCH DRIVERS
(20) SUM
NODE
DAC SWITCHES
VREF 5k
(14)
IN
5k +
–
DAC
(15) BIPOLAR
OFFSET (16) COMP
VCC–
(17)
SL00199
SL00706
1988 Dec 5
Philips Semiconductors Application note
CIRCUIT EXAMPLES feature of both devices direct connection to a data bus, using
Now that the basics of the NE5018 and the NE5118 have been address decoding. These devices greatly reduced the total
discussed, let’s examine some specific circuits. Figure 14 is a component count required to perform this operation.
microprocessor-controlled programmable gain amplifier, using the The reference voltage is common to both DACs, being provided by
NE5018. The VREF output is fed to the non-inverting input to a the NE5018. The bipolar offset resistor of the NE5018 provides the
differential amplifier. R1+R2 places 2.5VDC bias on the VREF input. 1mA current reference for the NE5118. Using the internal resistor of
R2 can be made adjustable to precisely control the DC reference the NE5018 to develop the reference current enhances the thermal
input. The analog input is fed to the inverting input of the differential tracking since the current-to-voltage resistor of the output op amp is
amplifier with a gain of unity. An input range of 0 to 2.5V will produce also in the NE5018. Both DACs can be addressed by a
an output of 10V to 5V full-scale. VREF IN will vary from 5V to 2.5V. microprocessor using an address decoder to select DAC A or DAC
The current ladder is always kept in the linear operating range and B.
the output will not become distorted.
Figure 16 is a schematic of the NE5118 and a NE527 as a
No compensation is required for the DAC reference amplifier since high-speed programmable limit sensor (or A/D converter). A 4.8V
the VREF IN is fed from a low impedance source. With a zener diode is used on the comparator input to insure the input
compensation cap of 33pF on the output amplifier, the frequency voltage range of the comparator is not exceeded. The outputs of the
response of the output is linear to at least 20kHz with less than 0.1% NE527 comparator are complementary, easing the logic interface
distortion with an input amplitude of 1VP-P. The NE5018 is seen by requirement. If the strobe function is not used, the strobe inputs
the microprocessor as an I/O device. should be tied high, through a 10kΩ resistor.
In Figure 15, the N5018 and NE5118 provide a method of summing
two digital words and generating a voltage output. The latch enable
SL00707
SL00708
1988 Dec 6
Philips Semiconductors Application note
SL00709
SL00710
a. +10 to 0V b. 0 to –10V
SL00711
Figure 13.
1988 Dec 7
Philips Semiconductors Application note
SL00712
SL00713
1988 Dec 8
Philips Semiconductors Application note
SL00714
1988 Dec 9