000-1-AN109 Standard

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INTEGRATED CIRCUITS

AN109
Microprocessor-compatible DACs

1988 Dec

 
 
 
Philips Semiconductors Application note

Microprocessor-compatible DACs AN109

DAC products are designed to convert a digital code to an analog The internal bandgap reference (1.23V) is buffered and amplified to
signal. Since a common source of digital signals is the data bus of a provide the 5V reference output. Providing a VREF ADJ (Pin 12)
microprocessor, DAC circuits that are bus compatible ease the allows easy trimming of the reference output (Pin 13). Use of a 10k
design engineer’s interface problems. pot and series resistor, as shown in Figure 3, adjusts the gain of the
buffer amplifier, therefore varying the output reference voltage level.
This network can then be used as a full-scale output adjust. A
WHAT FEATURES MAKE A DEVICE variation in the VREF OUT of ~ 0.8V, results in a corresponding 1.6V
BUS-COMPATIBLE? variation in the full-scale output. This is more than adequate since
The five conditions which determine processor bus compatibility are: the untrimmed VREF OUT is typically within 200mV of the nominal 5V.
• Inputs must present low bus load The VREF OUT will provide a maximum of 5mA drive and can be
used as a reference voltage for other system components, if
• Addressing must be provided required.
• Inputs must be latched DATA BUS
• Logic thresholds must be compatible
• Timing requirements should be adequate (<1µs) M
Processor RAM ROM NE5018 NE5118
Philips Semiconductors’ microprocessor-compatible DACs, the
NE5018 series, meet these requirements. In addition, they provide
an internal reference source. The NE5018 provides a scaled voltage ANALOG
output, eliminating the need for an external op amp. The NE5118 is ADDRESS BUS VOLTAGE
OUT
identical to the NE5018, except it provides the user with a current LE ANALOG
I/O CURRENT
output. Figure 1 shows a typical microprocessor system with analog CONTROL LINES OUT
LOGIC LE
output using the NE5018 to provide a programmable voltage and an SELECT
SL00715
NE5118 to provide a programmable current.
Figure 1. Interfacing to a Microprocessor
The following discussions detail the operation of the NE5018 and
NE5118 series DACs.

LATCH CIRCUIT
The latch circuits of the NE5018 and NE5118 are identical. Both the
data inputs and latch enable (LE) input feature ultra-low loading for
ease of interfacing. The 8-bit data latch, controlled by the latch
enable input, is static and level sensitive. When (LE) is low, all the
latches become transparent and the output changes as the bit
SL00701
pattern changes on the data bus. When the latch enable returns to
its high state, the last set of inputs are held by the latch and a Figure 2. Latch Enable (LE) Timing Diagram for the
unique output corresponding to the binary word in the latch is NE5018 and NE5118
produced. While the latch enable is high, the latch inputs represent a Since a potential need exists to use the NE5018 and NE5118 as
high impedance load on the data bus and changes on the data bus multiplying DACs, the VREF is not connected internally, allowing the
have no effect on the DAC output. use of external reference sources. To utilize the internal reference,
The digital logic input for the NE5018 and NE5118 series DACs the VREF OUT (Pin 13) must be jumper-connected to the VREF IN (Pin
utilize a differential input logic system with a threshold level of +1.4V 14). This also makes it possible to use a common reference for
with respect to the voltage level on the digital ground pin (Pin 1). To other D/A or A/D circuits in a system.
be compatible with microprocessors, the DAC should respond in as
short a period as possible to insure full utilization of the
microprocessor and I/O data bus lines. Figure 2 gives the typical INPUT AMPLIFIER OF THE NE5018
timing requirements of the latch circuits in the NE5018 and NE5118. The DAC reference amplifier has been designed to eliminate the
need for compensation when operating from the internal reference
The voltage levels on the data bus should be stable for
or from an external reference which is buffered by an op amp or low
approximately 150ns before latch enable returns to high level. The
impedance source. Compensation is required, however, when
timing diagram shows 100ns is required for setup time and the
operating from a high impedance source. The addition of an external
information on the data lines should remain valid for another 50ns.
resistance reduces the phase margin of the amplifier making it less
stable. Compensation, when required, is a single capacitor from Pin
16 to ground.
REFERENCE INTERFACE
The NE5018 and NE5118 contain an internal bandgap voltage Figure 4 details the input reference amplifier and current ladder. The
reference which is designed to have a very low temperature voltage-to-current converter of the DAC amp will generate a 1mA
coefficient and excellent long-term stability characteristics. reference current through QR with a 5V VREF. This current sets the

1988 Dec 2
Philips Semiconductors Application note

Microprocessor-compatible DACs AN109

input bias to the ladder network. Data bit 7 (DB7) Q7, when turned capacitor from VOUT to the sum node (CFF) to insure stability of the
on, will mirror this current and will contribute 1mA to the output. DB6 op amp. Typical values of CFF range from 15 to 22pF. The rated load
(Q6) will contribute of that value or 0.5mA, and so on. If all bits are of the op amp is ~ 2kΩ. For stability, the load capacitance should be
on, the output current will be minimized (50pF max).
2mA-1 LSB. The full-scale VOUT will be (IOUTRF) or 2mA-1
LSB×5k)=(10V-1 LSB)=9.961V. The overall input/output expression
for the NE5018 is:

V OUT  2V REF x DB7


2

DB6
4

DB5
8


DB4 DB3 DB2 DB1 DB0


   
16 32 64 128 256
The minimum current for the ladder network to be operative in the
SL00702
linear region is 500µA. Therefore, the minimum VREF input is 2.5V.
The slew rate of the reference amplifier is typically 0.7V/µs without Figure 3. Reference Adjust Circuit
compensation. The input structure of the NE5118 is slightly different
and will be discussed in greater detail later. QT provides a
termination for the R-2R ladder network and does not contribute to MODES OF OPERATION OF THE NE5018
IOUT. The NE5018 has two basic modes of operation: unipolar and bipolar.
When operating in the unipolar mode, the output range is 0 to +10V.
To change from unipolar to bipolar operation, the bipolar offset pin is
OUTPUT INTERFACE OF THE NE5018 connected to the summing node. This provides the 5V offset
The NE5018 has an internal op amp which provides a voltage required for this mode of operation. The output now will have a
output, while the NE5118 is a current output device. The NE5018 range from -5 to +5V. Figure 6 details the connection of the NE5018
output op amp is a two-stage design with feed-forward in the bipolar mode of operation.
compensation. Having a slew rate of 10V/µs, it provides a voltage
With the bipolar offset, Pin 15, connected to the sum node, Pin 20, it
output from 0 to 10V (±0.2%) typically within 2µs (the time allowed
forms a unity gain inverter with an input of +VREF. The bipolar offset
for the output voltage to settle to within LSB). Compensation must
develops an IREF current through the internal 5k resistor. This
be provided externally as shown in Figure 5.
current is then fed to the sum node of the output amplifier where it is
The addition of the optional diode between the summing node (Pin summed with the current output of the DAC ladder network. Assume
20) and ground prevents the DAC current switches from driving the for the moment that the current output of the ladder network is 0mA.
op amp into saturation during large-signal transitions which would With a VREF equal to +5V, IREF is 1mA and the output of the op amp
increase the settling time. is converted to -5V. If the DAC switches are now set to full-scale, the
current from the DAC ladder is 2mA. This is summed against the
Zero adjust circuits, such as the one shown in Figure 5, may also be
1mA IREF and causes the output of the op amp to swing from -5V to
connected to the summing node to provide a means to zero the
+5V.
output when all zeros are present on the input. Not all applications
require a zero adjust circuit since the untrimmed zero-scale is (IDAC-IREF)5k=(2mA-1mA)5k=+5V
typically less than 5mV. Excess stray capacitance at the sum node
Since the bipolar offset resistor is monolithic, tracking with the 5k
of the output op amp may necessitate the use of a feedback
feedback resistor of the output amplifier is excellent.

NOTE:
DAC compensation may be required if VREF resistance exceeds 10kΩ. SL00703

Figure 4. R-2R Ladder Network Develops a Scaled Reference Current Value Into the DAC Switching Network

1988 Dec 3
Philips Semiconductors Application note

Microprocessor-compatible DACs AN109

Note that the bipolar offset pin could not be used when using the NOTE:
DAC in a multiplier application since the VOUT would reflect an The absolute maximum input current should be limited to 5mA to prevent damage to the
inverted input signal. input reference amplifier.

Figure 8 shows the basic operating mode of the NE5118 using an


external current reference resistor (R1) and a positive reference
NOTES ON THE NE5118 CURRENT OUTPUT DAC voltage.
The basic operation of the NE5118 current output DAC is the same
as the NE5018. The current output structure allows the user to This voltage can be provided by either an internal or external
provide a programmable current sink (IOUT max of 2mA). Several reference voltage. Figure 9 shows a typical connection using a
jumper options provide a variety of operational modes. Figure 7 is a voltage input directly via Pin 15.
block diagram of the NE5118. The input logic and VREF portions are Besides a reduced parts count, use of the internal RREF provides
identical to the NE5018. excellent tracking characteristics with the ROUT resistor (Pin 20)
when developing a high slew rate voltage output. The negative VREF
input must be returned to ground directly or through R2. R2 is
REFERENCE INPUT AMPLIFIER optional and is used to cancel minor errors developed by the input
The characteristics of the reference input amplifier are identical to bias currents of the reference amplifier (R2=R1 in Figure 8). A
the NE5018; however, extended versatility of the input structure negative voltage can be the reference by using the -VREF input pin
allows for both current (via Pin 14) or voltage (via Pin 15) reference as shown in Figure 10.
inputs.
The positive VREF is returned to ground via RIN (Pin 15). As with the
The maximum DAC output current is 2mA. The DAC has an internal NE5018, a compensation capacitor on Pin 16 is not required if the
gain of 2, limiting the maximum usable input current to 1mA. VREF is supplied by a low impedance source.

SL00704

Figure 5. Zero-Scale Adjust

SL00705

Figure 6. Bipolar Output

1988 Dec 4
Philips Semiconductors Application note

Microprocessor-compatible DACs AN109

OUTPUT STRUCTURE An alternate method of bipolar output operation is shown in Figure


The output of the NE5118 is a current sink with a capacity of 2mA 12. The RREF and ROUT set up a current-to-voltage converter while
(full-scale) capable of settling to 0.2% in 200ns. Internal bias and two (2) external resistors provide a bipolar offset. REXT1 and REXT2
feedback resistors are also made available to ease the designer’s should have similar thermal tracking characteristics.
task of interfacing. The NE5118 can provide a voltage output directly when driving a
Figure 11 shows the NE5118 using a current-to-voltage converter at high impedance load as shown in Figure 13. With a full-scale current
the output to provide a high slew rate voltage output. Using the of 2mA, Pin 20 tied to +10V and a digital input of zero, the high
NE538 as shown can provide 60V/µs slew rate output. The diode at impedance load will see +10V. For a full-scale digital input, the load
the inverting node of the op amp improves the response time by will see 0V. Since the load and the internal resistor form a voltage
preventing saturation of the op amp during large signal transitions. divider, their ratio determines full-scale accuracy.
The feedback resistor ROUT1 (Pin 20) is provided internally, By connecting the ROUT resistor (Pin 20) to ground (Figure 13), the
providing excellent thermal tracking characteristics with the RREF at output voltage seen by the load ranges from 0V as zero-scale to
the input. -10V as full-scale. Only a few of the many possible output
configurations have been shown to demonstrate the NE5118
Bipolar operation can be accomplished by connecting the VREF OUT flexibility.
(Pin 12) to the ROUT resistor (Pin 20) (Figure 12). The principal is
the same as the NE5018 bipolar operation. The internal resistors
exhibit excellent thermal tracking characteristics.

(19)
VCC+
INT
VREF +
(13) OUT – VREF

15k
VREF (1)
(12) ADJ (10) (9) (8) (7) (6) (5) (4) (3) (2) DIGITAL
5k LE DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 GND
5k MSB LSB

LATCHES AND
SWITCH DRIVERS
(20) SUM
NODE

(18) VOUT + DAC CURRENT


– OUTPUT
(21) AMP 5k
COMP
(22) ANALOG
GND

DAC SWITCHES
VREF 5k
(14)
IN
5k +

DAC
(15) BIPOLAR
OFFSET (16) COMP

VCC–
(17)
SL00199

Figure 7. Block Diagram

SL00706

Figure 8. Positive IREF

1988 Dec 5
Philips Semiconductors Application note

Microprocessor-compatible DACs AN109

CIRCUIT EXAMPLES feature of both devices direct connection to a data bus, using
Now that the basics of the NE5018 and the NE5118 have been address decoding. These devices greatly reduced the total
discussed, let’s examine some specific circuits. Figure 14 is a component count required to perform this operation.
microprocessor-controlled programmable gain amplifier, using the The reference voltage is common to both DACs, being provided by
NE5018. The VREF output is fed to the non-inverting input to a the NE5018. The bipolar offset resistor of the NE5018 provides the
differential amplifier. R1+R2 places 2.5VDC bias on the VREF input. 1mA current reference for the NE5118. Using the internal resistor of
R2 can be made adjustable to precisely control the DC reference the NE5018 to develop the reference current enhances the thermal
input. The analog input is fed to the inverting input of the differential tracking since the current-to-voltage resistor of the output op amp is
amplifier with a gain of unity. An input range of 0 to 2.5V will produce also in the NE5018. Both DACs can be addressed by a
an output of 10V to 5V full-scale. VREF IN will vary from 5V to 2.5V. microprocessor using an address decoder to select DAC A or DAC
The current ladder is always kept in the linear operating range and B.
the output will not become distorted.
Figure 16 is a schematic of the NE5118 and a NE527 as a
No compensation is required for the DAC reference amplifier since high-speed programmable limit sensor (or A/D converter). A 4.8V
the VREF IN is fed from a low impedance source. With a zener diode is used on the comparator input to insure the input
compensation cap of 33pF on the output amplifier, the frequency voltage range of the comparator is not exceeded. The outputs of the
response of the output is linear to at least 20kHz with less than 0.1% NE527 comparator are complementary, easing the logic interface
distortion with an input amplitude of 1VP-P. The NE5018 is seen by requirement. If the strobe function is not used, the strobe inputs
the microprocessor as an I/O device. should be tied high, through a 10kΩ resistor.
In Figure 15, the N5018 and NE5118 provide a method of summing
two digital words and generating a voltage output. The latch enable

SL00707

Figure 9. Positive VREF

SL00708

Figure 10. Using a Negative IREF

1988 Dec 6
Philips Semiconductors Application note

Microprocessor-compatible DACs AN109

SL00709

Figure 11. High Slew Rate Voltage Outputs

SL00710

Figure 12. Bipolar Options of the NE5118

a. +10 to 0V b. 0 to –10V
SL00711

Figure 13.

1988 Dec 7
Philips Semiconductors Application note

Microprocessor-compatible DACs AN109

SL00712

Figure 14. Programmable Gain Amplifier

SL00713

Figure 15. Analog Summation With Digital Inputs

1988 Dec 8
Philips Semiconductors Application note

Microprocessor-compatible DACs AN109

SL00714

Figure 16. Programmable Limit Comparator

1988 Dec 9

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