EE2012 - Course Outline - 2022-02-10

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EE2012 - COMPUTER ORGANIZATION & ARCHITECTURE

NATIONAL UNIVERSITY OF COMPUTER & EMERGING SCIENCES, FAST-NU

Course Title Computer Organization & Architecture Course Code EE2012


Department Department of Electrical Engineering (DEE) Campus Lahore
Knowledge Profile Engineering Specialization (WK4) Credit Hrs. 3+1
Knowledge Area Computer Engineering (KA01) Grading Scheme Relative
HEC Knowledge Area Depth Electives Applicable From Fall 2021
Pre-requisite(s) EL105, EE105

The goal of this course is to develop a clear understanding of the basic organization of
computing systems. It covers logical basis of computer structure, machine representation
Course Objective
of instructions and data, flow of control and basic machine instructions. It also includes
processor pipeline designs and memory hierarchy systems.

No. Assigned Program Learning Outcome (PLO)


An ability to apply knowledge of mathematics, science, engineering fundamentals and an engineering
1
specialization to the solution of complex engineering problems.
I = Introduction, R = Reinforcement, E = Evaluation, A = Assignment, Q = Quiz, M = Midterm, F=Final, L =
Lab, P = Project, W = Written Report.

Assessment Taxonomy
No. Course Learning Outcome (CLO) Statements PLO
Tools Levels
1 Identify Components/Blocks of a computer. Q1, M1 C1 01.1M
2 Compare elements of a memory system. A1, M1 C2 01.1M
3 Analyze components of computer arithmetic. Q2, M2, F C4 01.1M
4 Appraise characteristics of machine instructions. Q3, F C4 01.1M
5 Appraise construction of central processing unit. A2, F C4 01.1M

EE. Dept. Lahore Page 1 of 2 v.00.01.1


EE2012 - COMPUTER ORGANIZATION & ARCHITECTURE
NATIONAL UNIVERSITY OF COMPUTER & EMERGING SCIENCES, FAST-NU

Title Computer Organization and Architecture 9th Edition


Text Books Author William Stallings
Publisher Pearson Education, Inc., 2013
Structured Computer Organization 5th Edition © 2006 Pearson
Title
Education, Inc.
Reference Books
Author Andrew S. Tanenbaum
Publisher

Week Course Contents/Topics Chapter* CLO*


Introduction: organization and architecture, structure and function, Computer
1.1-1.2, 3.1 –
01-02 components and computer functions, Interconnection Structures, Bus 1
3.4
Interconnection
03 Main Memory, Error Correction, DRAM Organization 5.1 – 5.3 2
4.1 – 4.3, 4.5.1
04 Cache Memory Principles, Elements of Cache Design 2
(Ref 1)
6.1 – 6.3, 2.3
05 Magnetic Disk, RAID 2
(Ref 1)
10.1 – 10.5,
ALU, Integer Representation and Arithmetic (Addition, Subtraction, and
06-07 Appendix B , 3
Multiplication),Floating Point Representation and Arithmetic
(Ref 1)
12.1, 12.2,
08 Machine Instructions, Types of Operands and Operations 12.4, 5.5 (Ref 4
1)
13.1, 13.3, 5.4
09 Addressing Modes, Instruction Formats 4
(Ref 1)
Processor Organization, Register Organization, Instruction Cycle, Instruction
10-11 14.1 – 14.4 5
Pipelining
RISC, Instruction Execution Characteristics, Register Files, Architecture,
12-13 15.1 – 15.5 5
Pipelining, RISC vs. CISC
14-16 Instruction-Level Parallelism and Superscalar Processors 16.1 – 16.2 05
*Reference book chapters are given in brackets

Assessment Tools Weightage


Quizzes + Assignments 20.0%
Midterms (I+II) 30.0%
Final Exam 50.0%

EE. Dept. Lahore Page 2 of 2 v.00.01.1

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