UP/DOWN

Switch̲State Input̲Pin̲State Switch̲State Input̲Pin̲State

Open(Not Pressed) Undefined Open(Not Pressed) Undefined

Closed (Pressed) High (Equal to VCC) Closed (Pressed) Low (Equal to GND)
 Switch̲State Input̲Pin̲State Switch̲State Input̲Pin̲State

Open(Not Pressed) Low Open(Not Pressed) High

Closed (Pressed) High (Equal to VCC) Closed (Pressed) Low (Equal to GND)
INTERRUPT
 INTERRUPT
Interrupts preempt normal code execution
• Interrupt code runs in the foreground
• Normal (e.g. main()) code runs in the background
Interrupts can be enabled and disabled
• Globally
• Individually on a per-peripheral basis
• Non-Maskable Interrupt (NMI)
The occurrence of each interrupt is unpredictable
• When an interrupt occurs
• Where an interrupt occurs
Interrupts are associated with a variety of on-chip and off-chip
peripherals.
• Timers, Watchdog, D/A, Accelerometer etc..
Interrupts are commonly used for urgent tasks which are highest
priority than main code
Interrupt Flags

• Each interrupt has a flag that is raised (set) when the

interrupt occurs.
• Each interrupt flag has a corresponding enable bit–
setting this bit allows a hardware module to request an
interrupt.
• Most interrupts are maskable, which means they can
only interrupt if
1) enabled and
2) the general interrupt enable (GIE) bit is set in the
status register (SR).
 Interrupt Vector

• The CPU must know where to fetch the

next instruction following an interrupt.

• The address of an ISR is defined in an

interrupt vector.

• The MSP430 uses vectored interrupts

here each ISR has its own vector stored
in a vector table located at the end of
program memory
Interrupt Service Routines
• Look superficially like a subroutine.
• However, unlike subroutines
→ISR’s can execute at unpredictable times.
→Must return using reti rather than ret.
• ISR must handle interrupt in such a way that the interrupted code can be
resumed without error
• Interrupt-related runtime problems can be exceptionally hard to debug
Returning from ISR

• MSP430 requires 6 clock cycles before the ISR begins executing

• The time between the interrupt request and the start of the ISR is called latency (plus
time to complete the current instruction, 6 cycles, the worst case)
• An ISR always finishes with the return from interrupt instruction (reti) requiring 5
cycles
 MASKING OF INDIVIDUAL BITS

A pattern used for selecting bits is called a mask and has all zeroes except for a 1 in the position that
we want to select.

if ((P1IN & BIT3) == 0) { // Test P1.3

// Actions for P1.3 == 0
} else {
// Actions for P1.3 != 0
}

Setting a bit is done using Inclusive OR operation- x|0 =x and x|1 =1

we could set (force to 1) bit 3 of port 1 with P1OUT = P1OUT | BIT3,
P1OUT| = BIT3;

Clearing a bit (to 0) is done using AND operation- x & 0 = 0 and x & 1 = x.
P1OUT &= ˜ BIT3

Bits can be toggled (changed from 0 to 1 or 1 to 0) using the exclusive-or

operation. For example, P1OUT ˆ= BIT3 toggles P1OUT.3.
 #include <msp430x20x3.h>
PORT1 void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
P1DIR |= 0x01; // Set P1.0 to output direction
P1IE |= 0x10; // P1.4 interrupt enabled
P1IES |= 0x10; // P1.4 Hi/lo edge
P1IFG &= ~0x10; // P1.4 IFG cleared
_BIS_SR(LPM4_bits + GIE); // Enter LPM4 w/interrupt
}
// Port 1 interrupt service routine
#pragma vector=PORT1_VECTOR
__interrupt void Port_1(void)
{
P1OUT ^= 0x01; // P1.0 = toggle
P1IFG &= ~0x10; // P1.4 IFG cleared
}
 #include <msp430x20x3.h>
TIMER void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P1DIR |= 0x01; // P1.0 output
TACTL = TASSEL_2 + MC_2 + TAIE; // SMCLK, contmode, interrupt
_BIS_SR(LPM0_bits + GIE); // Enter LPM0 w/ interrupt
}
// Timer_A3 Interrupt Vector (TAIV) handler
#pragma vector=TIMERA1_VECTOR
__interrupt void Timer_A(void)
{
switch( TAIV )
{
case 2: break; // CCR1 not used
case 4: break; // CCR2 not used
case 10: P1OUT ^= 0x01; // overflow
break;
}
}
 WATCHDOG TIMER
▪ Function is to perform Controlled system restart after encountering a s/w problem
▪ It can also be configured as “Interval Timer” if not used as watchdog timer

Features:
➢ 8 S/w selectable time intervals
➢ Two modes: Watchdog & Interval Timer
➢ available as WDT & WDT+
➢ WDTCTL register access is password protected
➢ can be stopped to conserve power
➢ clock fail safe feature
 WATCHDOG
Supervision (Watchdog)mode
• Ensure correct working of software program
• Configured with 32ms reset interval using SMCLK
• Writing wrong password or expiration of time interval performs PUC
• Generate interrupt when counter overflows
Interval timer
▪ Provides periodic interrupts
▪ Independent timer generates standard interrupt when counter overflows
periodically
WatchDog
#include <io430x11x1.h> // Specific device
Timer // Pins for LEDs and button
EXAMPLE #define LED1 P2OUT_bit.P2OUT_3
#define LED2 P2OUT_bit.P2OUT_4
#define B1 P2IN_bit.P2IN_1
// Watchdog config: active , ACLK /32768 -> 1s interval; clear counter
#define WDTCONFIG (WDTCNTCL|WDTSSEL)
// Include settings for _RST/NMI pin here as well
void main (void)
{
WDTCTL = WDTPW | WDTCONFIG; // Configure and clear watchdog
P2DIR = BIT3 | BIT4; // Set pins with LEDs to output
P2OUT = BIT3 | BIT4; // LEDs off (active low)
for (;;) { // Loop forever
LED2 = ˜IFG1_bit.WDTIFG; // LED2 shows state of WDTIFG
if (B1 == 1) { // Button up
LED1 = 1; // LED1 off
} else { // Button down
WDTCTL = WDTPW | WDTCONFIG; // Feed/pet/kick/clear watchdog
LED1 = 0; // LED1 on
}
}
}
 CLOCK Heart beat of our system

Operating modes ---- BOR → POR → PUC → Active (AM)

What Clocks Do You Need?

➢ Fast Clocks CPU, Communications, Burst Processing

➢ Low-power RTC, Remote, Battery, Energy Harvesting
➢ Accurate Stable over ⁰/V, Communications, RTC, Sensors
➢ Failsafe Robust–keeps system running in case of failure
➢ Cheap …
… or some combination of these features?

MSP430's rich clock ecosystem provides three internal clocks from a variety of clock sources.
VLO :
Very Low-frequency Oscillator (VLO)
extremely low-power
Ex: reading a sensor
REFO:
REFerance Oscillator (REFO)
common "watch crystal" frequency
Ex:RTC
XT1 and XT2
External clock inputs
Not all devices provide both
Ex:RTC,USB
DCO:
Digitally Controlled Oscillator (DCO)
fast start-up time
Ex:CPU & many high-speed peripherals
MODOSC:
MODuale OSCillator (MODOSC)
Didicated to ADC
 LOW POWER MSP430
Main features of the MSP430 families:
• Low power consumption (around 1 mW/MIPS or less)
• Battery operated embedded systems devices.
This goal can only be accomplished using a design utilizing
low power operating modes.

The total power consumption depends on several

factors:

• Clock frequency
• ambient temperature
• supply voltage
• Peripheral selection
• input/output usage
• memory type.
MODE
▪ Active Mode: All Clocks are active
▪ LPM0: CPU, MCLK Disabled
ACLK, SMCLK,FLL loop control are active
▪ LPM1: CPU, MCLK, FLL loop control are Disabled
ACLK, SMCLK are active
▪ LPM2: CPU, MCLK, FLL loop control, DCO clock are Disabled
DCO’s DC generator is enabled and ACLK is active
▪ LPM3: CPU, MCLK, FLL loop control, DCO clock, DCO’s DC generator are Disabled
ACLK is active
▪ LPM4: CPU, MCLK, FLL loop control, DCO clock, DCO’s DC generator, ACLK are Disabled.
Crystal Oscillator is stopped
RAM retention mode and complete data retention
This mode is used for externally generated interrupts
▪ LPM4.5: Internal regulator is disabled, No data retention and wakeup from NMI/RST
▪ BOR, POR, and PUC are a special type of a non-maskable interrupt with restart behavior of
the complete system.
BROWN OUT RESET(BOR): device reset generated by the following events:
❑Reset when there is a significant drop in the power supply output voltage
▪ Powering up the device
▪ A low signal on the 𝑅𝑆𝑇/NMI pin when configured in the reset mode
▪ A wakeup event from LPMx.5 (LPM3.5 or LPM4.5) modes
▪ A S/w BOR event

POWER ON RESET (POR): device reset generated by the following events:

❑Reset when power is applied to the device
▪ A BOR Signal
▪ Powering up the device
▪ A low signal on the 𝑅𝑆𝑇/NMI pin when configured in the reset mode
POWER UP CLEAR:
“A PUC only resets the CPU and starts over with program execution”.
A PUC is followed by a POR generation. The following events trigger a PUC
▪ A POR signal
▪ Watchdog timer expiration when in watchdog mode only
▪ Watchdog timer password violation
▪ A Flash memory security key violation
Low power modes
Principles For ULP Applications

MSP430 is inherently low-power, but your design has a big impact on power
efficiency

◆ Use interrupts to control program flow

◆ Maximize the time in LPM3
◆ Replace software with peripherals
◆ Configure unused pins properly
◆ Power manage external devices
◆ Efficient code makes a difference

Every unnecessary instruction executed is a portion of the battery

that’s wasted and gone forever
ACTIVE STAND-BY
FRAM FLASH
❖ Ferroelectric RAM (FRAM) is similar to Dynamic RAM (DRAM) – except that FRAM uses
ferroelectric capacitors – as opposed to traditional (dielectric) capacitors
❖ The ferroelectric crystal contains a dipole whose atom can be moved into an up or down state
based upon the application of a field.
❖ The atoms position can then be sensed, allowing us to read its value.
❖ The processes of setting the dipole’s state can be done with as little as 1.5 Volts-no charge
pump required
▪ The Real-Time Clock module configured as - a clock with calendar
- a general purpose counter.
RTCBCD Real-time clock BCD select. Applies to calendar mode (RTCMODE = 1) only
0 - Binary/hexadecimal code selected
1 - BCD code selected
RTCHOLD Real-time clock hold
0 - Real-Time Clock is operational
1 - In counter mode (RTCMODE = 0) only the 32-bit counter is stopped.
RTCMODE Real-time clock mode
0 - 32-bit counter mode
1 - Calendar mode
RTCRDY Real-time clock ready
0 - RTC time values in transition (calendar mode only).
1 - RTC time values safe for reading (calendar mode only)
RTCSSEL Real-time clock source select. 00 ACLK
01 - SMCLK
10 - Output from RT1PS
11 - Output from RT1PS
RTCTEV Real-time clock time event
TIMERS
▪ This module is formed by two independent 8-bit timers:
Basic timer1 counter1 (BTCNT1) and Basic timer1 Counter2 (BTCNT2)
▪ Cascaded to form a 16 bit timer

Features:
➢ Clock for LCD module
➢ Suitable for RTC implementation
➢ Basic interval timer
➢ Simple interrupt capability
BTCNT1: Generates frame frequency for LCD Controller
Clock source: ACLK
BTCNT2: Used as programmable frequency divider with interrupt capability to
provide periodic CPU interrupts and RTC
Clock sources: ACLK,SMCLK, ACLK/256
D.Aswani,Assistent Professor,SVEW
▪ Counter and clock input are the fundamental hardware elements in timer
▪ Counter is incremented for every clock pulse applied at its clock input
Ex: A 16-bit timer counts from 0x0000 to 0xFFFF (0 to 64K)
▪ Counter overflows When it reaches its maximum value (returns to 0 and starts counting)
▪ Generates an interrupt upon overflow
TACTL,
Timer_
A
Control
Registe
r
TACCTL
x,
Timer_A
Capture
/
Compar
e
Control
Register
Output (mode 0): In which output is controlled directly by the OUT bit in TACCRn
Toggle (mode 4): Provides a simple way of switching a load on and off for equal times (50% duty cycle)
Used in UP & Up/Down modes
Disadvantage: Toggles once per timer cycle, So frequency is halved and time period is
doubled
Set (mode 1) and Reset (mode 5): Typically used for single changes in the output, usually in the
Continuous mode.
Reset/Set (mode 7) and Set/Reset (mode 3): Typically used for periodic, edge aligned PWM in Up mode
of the counter 1. When TAR=TACCRn 2. When TAR=0

Toggle/Reset (mode 2) and Toggle/Set (mode 6): Typically used for center-aligned PWM in Up/Down
mode
1. TAR=TACCRn 2. TAR=TACCR0 (to fix waveform sign)
Output
Modes
Output mode Up mode Continuous mode Up/Down mode

1: Set

2: Toggle/Reset

3: Set/Reset

4: Toggle

5: Reset

6: Toggle/Set

7: Reset/Set
▪ Successive Approximation ADC: Fast ADC
Two Versions- ADC10 (10 bits of Output) & ADC12 (12 bits of Output)

▪ Sigma Delta ADC - Higher Resolution but low speed

▪ Resolution - No.of Distinct outputs are produced or Minimum change in output
with change in input
▪ Simple and cheap module that cannot perform a conversion by itself
▪ Used with TIMER-A to measure time constant of an external RC circuit
▪ Two versions- Comparator_A and Comparator_A+