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1s IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems (ICPEICES-2016)

Optimized Design and Performance Analysis of

Johnson Counter using 45 nm Technology

Manish Kumar Soniland Rajesh Mehra2

,,2Department of Electronics
& Communication Engineering,
National Institute of Technical Teachers' Training & Research Chandigarh, U T, India
E-mail: .manishsoniforu@gmail.com.2rajeshmehra@yahoo.com

Abstract-Sequential circuits largely contribute to the circuits must be designed effectively and efficiently. Low
power dissipation and propagation delay in a digital system.
power and area efficient design are key goals for a
Low power, less delay and area efficient sequential circuit
developer. Adopting proper architecture can lead to
design has been the major concern for VLSI designers. The
selection of optimized design technology plays a key role in
designing of a low power circuit with minimum number of
achieving the above parameters. A counter is a sequential CMOS logic gates. The selection of design technology and
circuit having wide application area in microcontroller flip flops used play key role in power reduction [2].
circuits including PLL, Digital to Analog converters, signal Johnson counter is one of very useful counters in
generators, signal synthesizers etc. In this paper a low power,
computer design which generates a specific data pattern in
high speed and cost efficient 4 bit Johnson counter is
synchronous manner. This data pattern is used in various
proposed. Deployed flip flop circuit uses 14 transistors to
realize the negative edge triggered master slave D flip flop logic designs to implement desired logic functions.
operation. Performance and cost of the proposed counter is Conventional Johnson counter is designed using shift
compared against the conventional counter. The proposed register where all the flip flops are provided with the same
design is found 48.86 % faster with having 43.22 % lesser dock pulse for synchronous operation. Conventional D
power dissipation than conventional design. The transistor
flip flops are made up of NAND gates and an inverter. In
requirements in the proposed counter is also 69.5 % lesser
making it an optimized design in terms of area.
the design of Johnson counter inverted output of least
Keywords-Johnson Counter; Master Slave D flip flop; significant bit flip flop is connected to the input of the
VLSI; Power Dissipation; Low Power CMOS Design; CMOS most significant bit flip flop. All other flip flops derive
Technology their inputs from the output of next higher significant bit
flip flop. [3]. In the proposed Johnson counter master
I. INTRODUCTION
slave D flip flops with less transistors are used in place of
Counters are important part of digital systems which conventional master slave D flip flops, which reduces the
are required to generate different form of sequences transistor count in addition to enhancing the speed of
synchronously. A digital counter comprises of a set of flip design. Low transistor design in turn reduces the power
flops that change their states in a specific manner to dissipation in the circuit. The proposed Johnson counter is
generate a particular pattern sequence. This pattern designed using Cadence EDA tool. The contribution and
sequence could be associated with the number of times an outline of this paper is as folIows:
event occurs or controlling a digital system. A counter has Section n describes the design considerations in the
wide application area in microcontroller circuits induding CMOS circuit implementation. Section III presents the
frequency divider in PLL, Digital to Analog converters, Johnson counter circuit design. Section IV details the
signal generators and processing circuits, frequency proposed schematic design. Section V takes up the
synthesizers, digital memories, digital timing and dock discussion on the simulations and resuIts obtained from
circuits etc. [ 1]. The output patterns of O's and 1's that are the schematic of 4 bit Johnson counter in Cadence EDA
stored in various flip flops of counters are referred to as its tool and fmally section VI condudes the paper.
states. The total number of states in a counter is called its
n. DESIGN CONSIDERATIONS
modulus count and the manner in which a counter passes
through these states is referred to as its counting sequence. One of the design goals in VLSI has been to reduce
In VLSI designing, sequential circuits are integrated the power consumption in CMOS logic circuits. In various
along with combinational circuits in small area of a chip. applications, power consumption in CMOS logic designs
Sequential digital circuits induding registers and counters has increased due to the use of continuously increased
are used to perform all arithmetic, logical and memory dock frequency. Even when used at lower supply voItages
processes in a computer system. So for the best these designs exhibit higher power dissipation. Power
performance of the computer systems these sequential consumption in CMOS logic circuits consists of a static

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component resulting from leakage of inactive devices, III. JOHNSON COUNTER DE SIGN
gate tunneling current, threshold conduction through
In sequential logic circuits the basic memory element
inactive transistors, contention current etc. [4]. The sub­
is flip flop. It can store data on rising edge or falling edge
threshold current can be expressed as:
Vgs-Vt Vds
of the dock pulse. Flip flop that operates on rising edge of
Ids Idsoe ---nv;::- (1 e -VT)
= - ( 1) dock pulse is referred to as positive edge triggered flip
Where Idso Jieff' cox'
=
ef).
vi (2)
flop and one that operated on falling edge is called
negative edge triggered flip flop [2]. A conventional
Jieff refers to the effective charge carrier mobility, master slave D flip flop is designed using 8 NAND gates
Cox is gate capacitance per unit area, � L
is width to length and an inverter as shown in Fig. 1. The first stage of
ratio of the channel, Vt represents threshold voItage, VT is master slave flip flop is called the master which is directly
thermal voItage, n refers to sub threshold swing applied with external dock pulse signal and the second
coefficient and Vgs and Vds represent gate to source and stage which is referred to as slave is applied with the
drain to source voItages respectively [5]. inverted dock. The master is sensitive to the positive level
Dynamic power dissipation arises because of of the dock while the slave to the negative level.
charging and discharging of load capacitance and short
circuit current that flows while the switching of CMOS
transistor takes place. The finite nonzero load capacitance
gets charged when PMOS is on and as soon as NMOS
gets activated it gets itself discharged by providing current
through itself to ground. The power dissipation due to
charging and discharging of load capacitance is expressed
as:
P = 0.5 CL V5D fclk Esw (3)
Where CL is the load capacitance, VDD is the supply
voItage, fclk is the dock frequency and Esw refers to the Fig. I: Conventional Master Slave D Flip Flop [II
average switching activity i.e. average number of output When external dock signal is at high level, master is
transitions per dock cyde. Since dock frequency in high operational and it follows the D input. SimuItaneously the
speed applications has increased, it has resuIted in high slave is deactivated and therefore holds its previous value.
switching frequency of CMOS devices resulting in higher When dock transition takes place to logic 0 from logic 1,
dynamic power dissipation [6]. the master latch sampIes its output value and passes it to
Sequential circuit largely contributes to the power slave. The slave is activated for low dock signal level and
dissipation of a digital system. Sequential circuit changes hence it passes the stored value to its output. During
its present state synchronously with the dock transitions negative level of dock the master is deactivated and hence
according to the specified logic. These state changes can is unaffected from the input applied to it. Here an area
occur either during positive or negative edge transitions of efficient and low power Master Slave flip flop is used
dock. Clock transitions from high to low and low to high, which is negatively edge triggered i.e. Slave output is
are themselves big contributors to the power dissipation. updated at the low dock signal level [8].
In CMOS designing while dock transition occurs, both In the proposed Johnson counter a negative edge
NMOS and PMOS can be activated for a fraction of time
triggered master slave D flip flop with less transistor count
because of non-zero rise time and fall time. It creates an
is used. The transistor level implementation of the above
electrical path from VDD to ground and current flows
mentioned flip flop is as shown in Fig. 2 [9]. It has a
through the circuit. This current is referred to as Short
transistor count of 10 which is lesser than the conventional
circuit current or thorough current which appear as a spike
master slave D flip flop. However, the shown master slave
during dock transition [6]. This short circuit current leads
to a major portion of dynamic power loss which is referred D flip flop cannot be used in counter circuits as there is no
to as short circuit power dissipation and is expressed as provision to reset it. Therefore it is further associated with
folIows: 2 additional NMOS transistors which are used to reset its
Psc Isc· Vdd· ts' Esw
= (4 ) state. This takes the transistor count to 12 but provides
where, Isc is short circuit current and ts is the much required reset operation for counter applications.
switching delay [5]. These two above described The transistor count of the proposed master slave D flip
phenomena account for dynamic power dissipation in flop still remains lesser than the conventional master slave
sequential circuits which heavily depend upon dock D flip flop.
switching frequency. It has been shown that dock signals Johnson counter, conventionally, is based on
even account for 15 to 45 % of total power dissipation [7]. synchronous timing principle where the state of each flip

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flop is evaluated at every triggering edge of clock. The

modulus count of Johnson counter is 2n where n is the
number of flip flops used in its design. The block diagram
of 4 bit Johnson counter and its count sequence are shown
in Fig. 3 and Table 1 respectively.
In 4 bit Johnson counter the modulus count is 8.
Initially the state of the counter is reset to 0000. It then
follows the count sequence as 1000, 1100, 1110, 1111,
0111,0011, 0001 and then back to 0000. Johnson counter
is also called as twisted ring counter because instead of
connecting the least significant flip flop output to most
significant flip flop input, as is done in ring counter, the Master memory cell Slave memory cell

inverted output of least significant flip flop is connected to Fig. 2: Negative Edge Triggered Master Slave O. Flip Flop [9]
the input of most significant input [7].

D2 Q2 �
I D2 Q2
I D1 Ql �
I Do Qo
�
CLK CLK
P
CLK CLK

Fig. 3: 4 Bit Johnson Counter

TABLE 1: STATE TABLE OF 3 BIT JOHNSON COUNTER TABLE 2: NMOS AND PMOS SPECIFICATlONS
Clock Q3 Q2 Ql Qo Parameter NMOS Transistor PMOS Transistor
0 0 0 0 0 Length 45 nm 45 nm
1 1 0 0 0 Width 120 nm 240 nm
2 1 1 0 0 Finger width 120 nm 240 nm
3 1 1 1 0 Fingers 1 1
S/O metal 400 nm 400 nm
4 1 1 1 1
Threshold 800 nm 800 nm
5 0 1 1 1
6 0 0 1 1 U sing the transistors of above mentioned specifications,
7 0 0 0 1 less transistor count master slave D flip flop is designed as
8 0 0 0 0 shown in Fig. 4. It employs 10 transistors to execute the
performance of master slave D flip-flop. An inverter cell is
IV. PROPOSEO SCHEMATIC DESIGN created with same transistor specifications and is directly
used in the schematic. 2 additional NMOS transistors are
The proposed circuit of Johnson counter has been
used in the circuit for reset operation. A cell of the designed
simulated and implemented for 45nm technology in flip flop is created so as to use it as an instance in the
Cadence EDA tool. The transistor level schematic is Johnson counter designing.
designed in Cadence Virtuoso schematic editor [9]. The Subsequently, the proposed 4 bit Johnson counter is
circuit is implemented progressively by creating instances designed using the instances of master slave D flip-flop.
of various components in the design and then putting them The implemented design is shown in Fig. 5 which is then
together to get the desired response of Johnson counter. simulated and analyzed using Cadence analog design
The PMOS and NMOS transistors used to build the environment. In the design, 4 instances of the created flip­
flop cell are used in cascade where the input of a flip-flop
schematic diagram are selected as per the specifications
is derived from the output of next most significant flip
tabled in Table 2.

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flop. The input of most significant flip flop is derived from

the inverted output of least significant flip flop. There is a
provision of same dock pulse to realize the functioning of
Johnson counter. A common reset pulse is also connected
to all the flip flops in parallel to reset the state of the
counter to zero whenever required.
A 4 bit Johnson counter using conventional master
slave D flip flops is also designed and implemented. The
conventional master slave D flip flop with 8 NAND gates
and an inverter is designed using PMOS and NMOS of
same specifications and is as shown in Fig. 6. The
schematic shows the internal configuration of
conventional master slave D flip flop in terms of NMOS Fig. 6: Conventional Master Slave D Flip Flop
and PMOS transistors. 2 input and 3 input NAND gates
are realized and are then connected as per the gate level
schematic design of conventional master slave D flip flop.
A cell of this conventional D flip flop is created which is
used to implement the design of 4 bit conventional
Johnson counter as shown in Fig. 7. The schematic of 4 bit ·t
conventional Johnson counter is created in the similar
manner as in proposed design. 4 instances of the
conventional D flip flop cells are used and connected in
shift register mode with the inverted output of least
significant flip flop connected to the input of most
significant flip flop.
Fig. 7: 4 Bit Conventional Johnson Counter

V. RESULT SIMULATIONS AND DISCUSSIONS

The implemented designs of proposed and

11 -cf � 1 1 -cfJ. -d I
conventional Johnson counter are then simulated and
analyzed using Cadence Analog Design Environment. The
I transient responses of the proposed and conventional
T
L
designs are shown in Fig. 8 and Fig. 9 respectively. Fig. 8
shows the transient response of proposed 4 bit Johnson
I � counter. The count sequence can be easily verified as per
Table 1 where Q3 represents the output to the most
significant flip flop and Qo represents the output of least
significant flip flop. The dock frequency used has been
set to 10 ns for both the design simulations. Similarly the
Fig. 4: Master Slave D Flip Flop with Less Transistor Count response of the conventional Johnson counter is verified
as per Table 1. The transient responses of the two designs
are then used to calculate the delay and power dissipation.
Cadence Analog Design Environment also gives the count
of transistors used in the design.
·M'

Fig. 8: Transient Response of Proposed 4 Bit Johnson Counter

Fig. 5: Proposed 4 bit Johnson Counter

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From the above table and bar graph it can be seen that
· �:n� the power dissipation in 4 bit Johnson counter with
· �:[I proposed design is 207.9 pW as compared to 366.18 pW
·
�': I -, �� � -----' with conventional design. This accounts for 43.22 %
reduction in power dissipation making the proposed circuit
· �;� L J'--� S--� -,r--- suitable to operate in the applications where low power
�'�I�
__ __ __

· I constraint is an issue. The propagation delay in proposed

• ��!;:::;:�
::;::;: ��:::;::;::;:::;::;:���:;:::;:
::;:::I::;: :, design is 43.21 ps compared to 84.5 ps in conventional
�o ml
-" design which leads to 48.86% fall in the delay of the
Fig. 9: Transient Response of Conventional 4 bit Johnson Counter counter response. This reduction in delay in turn makes
the proposed design 48.86% faster than the conventional
Performance and comparative analysis of the
design. In high frequency applications where the counter
proposed Johnson counter design with respect to the
response needs to be faster than the clock time period, the
conventional design, in terms of power dissipation, delay
proposed design offers a better solution. The transistor
and transistor count is done in Table 3. All the parameters
count reduces to 56 in proposed design from 184 in
are then graphically compared with the help of bar charts.
conventional design which shows a 69.5% reduction. This
Fig. 10 shows the comparison of the proposed counter
reduction in the number of transistors would lead to area
with conventional counter in terms of power dissipation
optimized design of Johnson counter. Hence the proposed
and delay. Fig. 11 shows the comparison of the two
counter fmds its application in the field of small area, low
designs in terms of transistor count.
power and energy efficient VLSI designs. The proposed
TABLE 3: PERFORMANCE AND COST ANALYSIS
design of Johnson counter may further be effectively
Design Power Delay (ns) Transistor employed in the designing of efficient microcontroller
Dissipation (nW) Count circuits like Digital to analog converters, PLLs, digital
Conventional Johnson 0.36618 0.0845 184
memories, timing and control circuits etc.
Counter
Proposed Johnson 0.2079 0.04321 56
VI. CONCLUSION
Counter
In this paper a 4 bit Johnson counter using less
0.4
transistor count, negative edge triggered master slave D
0.35 flip flop has been proposed. The performance and cost
0.3
• analysis of the proposed counter has been done in terms of
0.25
• power dissipation, delay and transistor count. The
0.2
• • Conventional Johnson
proposed design is compared with the conventional design
of Johnson counter. After analyzing the resuIts, it can be
0.15
• Counter
concluded that the proposed counter design has superior
.Proposed Johnson
0.1
• Counter performance to the conventional design. The proposed
0.05 • design is found to have better performance both in terms
o
· - of power dissipation and propagation delay. The power
dissipation in the proposed design has reduced to 0.2079
Power Dissipation Delay (ns)
(nW) nW compared to 0.36618 nW in conventional design. The
delay in the proposed counter is found to be 0.04321 ns as
Fig. 10: Comparative Analysis in Terms of Power Dissipation and Delay
against 0.0845 ns in conventional design. The cost
analysis of the two designs shows that the proposed
200 counter requires 56 transistors compared to 184 as
180 required in conventional counter which makes the
160 proposed design highly cost efficient.
140

120 REFERENCES
100

80
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o
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