Laboratory Exercise Dig8

Figure 1 shows a digital system that contains a number of 16-bit registers, a multiplexer, an adder/subtracter unit,
a counter, and a control unit. Data is input to this system via the 16-bit DIN input. This data can be loaded through
the 16-bit wide multiplexer into the various registers, such as R0, . . . , R7 and A. The multiplexer also allows data
to be transferred from one register to another. The multiplexer’s output wires are called a bus in the figure because
this term is often used for wiring that allows data to be transferred from one location in a system to another.
Addition or subtraction is performed by using the multiplexer to first place one 16-bit number onto the bus
wires and loading this number into register A. Once this is done, a second 16-bit number is placed onto the bus,
the adder/subtracter unit performs the required operation, and the result is loaded into register G. The data in G
can then be transferred to one of the other registers as required.
The system can perform different operations in each clock cycle, as governed by the control unit. This unit
determines when particular data is placed onto the bus wires and it controls which of the registers is to be loaded
with this data. For example, if the control unit asserts the signals R0 out and Ain , then the multiplexer will place
the contents of register R0 onto the bus and this data will be loaded by the next active clock edge into register A.

16

16 16 16 16
A in
R0 in R7 in
R0 R7 A

Clock
16 AddSub
DIN Addsub

16
Multiplexers G in
G
8
16
9 bits
Bus

DIN[15:7]
G out DIN out
R0 out } R7 out
IR in

IR

9
Control unit

Run
Resetn

2
Clear Done
Counter

Figure 1. A digital system.

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 A system like this is often called a processor. It executes operations specified in the form of instructions.
Table 1 lists the instructions that the processor has to support for this exercise. The left column shows the name
of an instruction and its operand. The meaning of the syntax RX ← [RY] is that the contents of register RY are
loaded into register RX. The mv (move) instruction allows data to be copied from one register to another. For
the mvi (move immediate) instruction the expression RX ← D indicates that the 16-bit constant D is loaded into
register RX.

Operation Function performed

mv Rx,Ry Rx ← [Ry]
mvi Rx,#D Rx ← D
add Rx, Ry Rx ← [Rx] + [Ry]
sub Rx, Ry Rx ← [Rx] − [Ry]

Table 1. Instructions performed in the processor.

Each instruction can be encoded and stored in the IR register using the 9-bit format IIIXXXYYY, where III
represents the instruction, XXX gives the RX register, and YYY gives the RY register. Although only two bits
are needed to encode our four instructions, we are using three bits because other instructions will be added to the
processor in later parts of this exercise. Hence IR has to be connected to nine bits of the 16-bit DIN input, as
indicated in Figure 1. For the mvi instruction the YYY field has no meaning, and the immediate data #D has to be
supplied on the 16-bit DIN input after the mvi instruction word is stored into IR.
Some instructions, such as an addition or subtraction, take more than one clock cycle to complete, because
multiple transfers have to be performed across the bus. The control unit uses the two-bit counter shown in Figure 1
to enable it to “step through” such instructions. The processor starts executing the instruction on the DIN input
when the Run signal is asserted and the processor asserts the Done output when the instruction is finished. Table
2 indicates the control signals that can be asserted in each time step to implement the instructions in Table 1. Note
that the only control signal asserted in time step 0 is IR in , so this time step is not shown in the table.

T1 T2 T3
(mv): I0 RYout , RXin ,
Done
(mvi): I1 DINout , RXin ,
Done
(add): I2 RXout , Ain RYout , Gin Gout , RXin ,
Done
(sub): I3 RXout , Ain RYout , Gin , Gout , RXin ,
AddSub Done

Table 2. Control signals asserted in each instruction/time step. Note that I0 is the mv instruction
code for the III field of the IR and has the value 000, similarly I1=001, I2=010 and I3=011.

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Part I

Design and implement the processor shown in Figure 1 using Verilog code as follows:
1. Create a new Quartus II project for this exercise.
2. Generate the required Verilog file, include it in your project, and compile the circuit. A suggested skeleton
of the Verilog code is shown in Figure 2a, and some subcircuit modules that can be used in this code appear
in Figure 2b.

3. Use functional simulation to verify that your code is correct. An example of the output produced by a
functional simulation for a correctly-designed circuit is given in Figure 3. It shows the value (2000) 16 =
0010 0000 0000 0000 and the top 9 bits are loaded into IR (giving III = 001=I1) from DIN at time 30 ns.
This pattern represents the instruction mvi R0,#D, where the value D = 5 is loaded into R0 on the clock
edge at 50 ns. The simulation then shows the instruction mv R1,R0 at 90 ns, add R0,R1 at 110 ns, and sub
R0,R0 at 190 ns. Note that the simulation output shows DIN as a 4-digit hexadecimal number (each hex
digit is 4 bits), and it shows the contents of IR as a 3-digit octal number (each oct digit is 3 bits).

4. Create a new Quartus II project which will be used for implementation of the circuit on the Altera DE2
board. This project should consist of a top-level module that contains the appropriate input and output ports
for the Altera board. Instantiate your processor in this top-level module. Use switches SW 15−0 to drive the
DIN input port of the processor and use switch SW 17 to drive the Run input. Also, use push button KEY 0 for
Resetn and KEY1 for Clock. Connect the processor bus wires to LEDR 15−0 and connect the Done signal to
LEDR17.
5. Add to your project the necessary pin assignments for the DE2 board. Compile the circuit and download it
into the FPGA chip.

6. Test the functionality of your design by toggling the switches and observing the LEDs. Since the processor’s
clock input is controlled by a push button switch, it is easy to step through the execution of instructions and
observe the behavior of the circuit.

Off campus students: The skeleton code has been included in the Dig8part1_tb.v testbench code available
on Moodle. This testbench does not have automatic error detection since this is to be checked by the
student manually. In the testbench the following instructions are executed with the same timing as shown
Figure 3 below:

mvi R0, #5
mv R1, R0
add R0, R1
sub R0, R0
You should be able to complete the register contents and BusWires values from your understanding of the
instructions and implementation.

Complete your code and debug your work using ModelSim. Once you are satisfied everything is correct,
show ModelSim with the matching simulation of Figure 3 with all the same signals to your demonstrator.

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module proc (DIN, Resetn, Clock, Run, Done, BusWires);
input [15:0] DIN;
input Resetn, Clock, Run;
output Done;
output [15:0] BusWires;

. . . declare variables

wire Clear = . . .
upcount Tstep (Clear, Clock, Tstep Q);
assign I = IR[8:6];
dec3to8 decX (IR[5:3], 1’b1, Xreg);
dec3to8 decY (IR[2:0], 1’b1, Yreg);

always @(Tstep Q or I or Xreg or Yreg)

begin
. . . specify initial values
case (Tstep Q)
2’b00: // store DIN in IR in time step 0
begin
IRin = 1’b1;
end
2’b01: //define signals in time step 1
case (I)
...
endcase
2’b10: //define signals in time step 2
case (I)
...
endcase
2’b11: //define signals in time step 3
case (I)
...
endcase
endcase
end

regn reg 0 (BusWires, Rin[0], Clock, R0);

. . . instantiate other registers and the adder/subtracter unit

. . . define the bus

endmodule

Figure 2a. Skeleton Verilog code for the processor.

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module upcount(Clear, Clock, Q);
input Clear, Clock;
output [1:0] Q;
reg [1:0] Q;

always @(posedge Clock)

if (Clear)
Q <= 2’b0;
else
Q <= Q + 1’b1;
endmodule

module dec3to8(W, En, Y);

input [2:0] W;
input En;
output reg [7:0] Y;

always @(W, En)

begin

if (En)
case (W)
3’b000: Y = 8’b00000001;
3’b001: Y = 8’b00000010;
3’b010: Y = 8’b00000100;
3’b011: Y = 8’b00001000;
3’b100: Y = 8’b00010000;
3’b101: Y = 8’b00100000;
3’b110: Y = 8’b01000000;
3’b111: Y = 8’b10000000;
endcase
else
Y = 8’b00000000;
end
endmodule

module regn(R, Rin, Clock, Q);

parameter N = 16;
input [N-1:0] R;
input Rin, Clock;
output [N-1:0] Q;
reg [N-1:0] Q;

always @(posedge Clock)

if (Rin)
Q <= R;
endmodule

Figure 2b. Subcircuit modules for use in the processor.

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DIN in hex:

IR in Octal:

Figure 3. Simulation of the processor.