NGD15N41CL,

NGB15N41CL,
NGP15N41CL
Preferred Device

Ignition IGBT
15 Amps, 410 Volts
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N−Channel DPAK, D2PAK and TO−220
This Logic Level Insulated Gate Bipolar Transistor (IGBT) features 15 AMPS
monolithic circuitry integrating ESD and Over−Voltage clamped 410 VOLTS
protection for use in inductive coil drivers applications. Primary uses VCE(on) 3 2.1 V @
include Ignition, Direct Fuel Injection, or wherever high voltage and
high current switching is required. IC = 10 A, VGE . 4.5 V
Features C
• Ideal for Coil−on−Plug Applications
• DPAK Package Offers Smaller Footprint and Increased Board Space
• Gate−Emitter ESD Protection G RG
• Temperature Compensated Gate−Collector Voltage Clamp Limits
Stress Applied to Load RGE
• Integrated ESD Diode Protection
• New Design Increases Unclamped Inductive Switching (UIS) Energy E
Per Area
• Low Threshold Voltage to Interface Power Loads to www.DataSheet4U.com
Logic or 4 DPAK
Microprocessor Devices CASE 369C
• Low Saturation Voltage 1 2 STYLE 2
3
• High Pulsed Current Capability
• Optional Gate Resistor (RG) and Gate−Emitter Resistor (RGE)
• Pb−Free Packages are Available 4 D2PAK
CASE 418B
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) 1 2 STYLE 4
Rating Symbol Value Unit 3

Collector−Emitter Voltage VCES 440 VDC

4
Collector−Gate Voltage VCER 440 VDC
Gate−Emitter Voltage VGE 15 VDC
Collector Current−Continuous IC 15 ADC TO−220AB
@ TC = 25°C − Pulsed 50 AAC CASE 221A
STYLE 9
ESD (Human Body Model) ESD kV
R = 1500 Ω, C = 100 pF 8.0
1
ESD (Machine Model) R = 0 Ω, C = 200 pF ESD 800 V 2
3
Total Power Dissipation @ TC = 25°C PD 107 Watts
Derate above 25°C 0.71 W/°C
ORDERING INFORMATION
Operating and Storage Temperature Range TJ, Tstg −55 to °C See detailed ordering and shipping information in the package
+175 dimensions section on page 8 of this data sheet.

Stresses exceeding Maximum Ratings may damage the device. Maximum DEVICE MARKING INFORMATION
Ratings are stress ratings only. Functional operation above the Recommended See general marking information in the device marking
Operating Conditions is not implied. Extended exposure to stresses above the section on page 8 of this data sheet.
Recommended Operating Conditions may affect device reliability.
Preferred devices are recommended choices for future use
and best overall value.

© Semiconductor Components Industries, LLC, 2006 1 Publication Order Number:

May, 2006 − Rev. 7 NGD15N41CL/D
 NGD15N41CL, NGB15N41CL, NGP15N41CL

UNCLAMPED COLLECTOR−TO−EMITTER AVALANCHE CHARACTERISTICS (−55° ≤ TJ ≤ 175°C)

Characteristic Symbol Value Unit
Single Pulse Collector−to−Emitter Avalanche Energy EAS mJ
VCC = 50 V, VGE = 5.0 V, Pk IL = 16.6 A, L = 1.8 mH, Starting TJ = 25°C 250
VCC = 50 V, VGE = 5.0 V, Pk IL = 15 A, L = 1.8 mH, Starting TJ = 125°C 200
THERMAL CHARACTERISTICS
Characteristic Symbol Value Unit
Thermal Resistance, Junction to Case RθJC 1.4 °C/W
Thermal Resistance, Junction to Ambient DPAK (Note 1) RθJA 100
D2PAK (Note 1) RθJA 50
TO−220 RθJA 62.5
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 5 seconds TL 275 °C

ELECTRICAL CHARACTERISTICS
Characteristic Symbol Test Conditions Temperature Min Typ Max Unit
OFF CHARACTERISTICS
Collector−Emitter Clamp Voltage BVCES IC = 2.0 mA TJ = −40°C to 380 410 440 VDC
150°C
IC = 10 mA TJ = −40°C to 380 410 440
150°C

Zero Gate Voltage Collector Current ICES TJ = 25°C − 2.0 20 μADC

VCE = 350 V,
TJ = 150°C − 10 40*
VGE = 0 V
TJ = −40°C − 1.0 10
Reverse Collector−Emitter Leakage Current IECS TJ = 25°C − 0.7 2.0 mA
VCE = −24 V
TJ = 150°C − 12 25*
TJ = −40°C − 0.1 1.0
Reverse Collector−Emitter Clamp Voltage BVCES(R) TJ = 25°C 27 33 37 VDC
IC = −75 mA
TJ = 150°C 30 36 40
TJ = −40°C 25 31 35
Gate−Emitter Clamp Voltage BVGES IG = 5.0 mA TJ = −40°C to 11 13 15 VDC
150°C
Gate−Emitter Leakage Current IGES VGE = 10 V TJ = −40°C to 384 640 1000 μADC
150°C
Gate Resistor RG − TJ = −40°C to − 70 − Ω
150°C
Gate Emitter Resistor RGE − TJ = −40°C to 10 16 26 kΩ
150°C
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage VGE(th) TJ = 25°C 1.1 1.4 1.9 VDC
IC = 1.0 mA,
TJ = 150°C 0.75 1.0 1.4
VGE = VCE
TJ = −40°C 1.2 1.6 2.1*
Threshold Temperature Coefficient − − − − 3.4 − mV/°C
(Negative)
1. When surface mounted to an FR4 board using the minimum recommended pad size.
2. Pulse Test: Pulse Width v 300 μS, Duty Cycle v 2%.
*Maximum Value of Characteristic across Temperature Range.

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 NGD15N41CL, NGB15N41CL, NGP15N41CL

ELECTRICAL CHARACTERISTICS (continued)

Characteristic Symbol Test Conditions Temperature Min Typ Max Unit
ON CHARACTERISTICS (continued) (Note 3)
Collector−to−Emitter On−Voltage VCE(on) TJ = 25°C 1.0 1.6 1.8 VDC
IC = 6.0 A,
TJ = 150°C 0.9 1.5 1.8
VGE = 4.0 V
TJ = −40°C 1.1 1.65 1.9*
TJ = 25°C 1.3 1.8 2.0*
IC = 8.0 A,
TJ = 150°C 1.2 1.7 1.9
VGE = 4.0 V
TJ = −40°C 1.4 1.8 2.0*
TJ = 25°C 1.4 2.0 2.2
IC = 10 A,
TJ = 150°C 1.5 2.0 2.3*
VGE = 4.0 V
TJ = −40°C 1.4 2.0 2.2
TJ = 25°C 1.3 1.9 2.1
IC = 10 A,
TJ = 150°C 1.3 1.9 2.1
VGE = 4.5 V
TJ = −40°C 1.4 1.95 2.1*
Forward Transconductance gfs VCE = 5.0 V, IC = 6.0 A TJ = −40°C to 8.0 15 25 Mhos
150°C
DYNAMIC CHARACTERISTICS
Input Capacitance CISS 400 650 1000 pF
VCC = 25 V, VGE = 0 V TJ = −40°C to
Output Capacitance COSS 30 55 100
f = 1.0 MHz 150°C
Transfer Capacitance CRSS 3.0 4.5 8.0
SWITCHING CHARACTERISTICS
Turn−Off Delay Time (Inductive) td(off) VCC = 300 V, IC = 6.5 A TJ = 25°C − 4.0 10 μSec
RG = 1.0 kΩ, L = 300 μH
TJ = 150°C − 4.5 10
Fall Time (Inductive) tf VCC = 300 V, IC = 6.5 A TJ = 25°C − 6.0 12
RG = 1.0 kΩ, L = 300 μH
TJ = 150°C − 10 12
Turn−Off Delay Time (Resistive) td(off) VCC = 300 V, IC = 6.5 A TJ = 25°C − 3.0 10 μSec
RG = 1.0 kΩ, RL = 46 Ω,
TJ = 150°C − 3.5 10
Fall Time (Resistive) tf VCC = 300 V, IC = 6.5 A TJ = 25°C − 8.0 15
RG = 1.0 kΩ, RL = 46 Ω,
TJ = 150°C − 12 15
Turn−On Delay Time td(on) VCC = 10 V, IC = 6.5 A TJ = 25°C − 0.7 4.0 μSec
RG = 1.0 kΩ, RL = 1.5 Ω
TJ = 150°C − 0.7 4.0
Rise Time tr VCC = 10 V, IC = 6.5 A TJ = 25°C − 4.0 7.0
RG = 1.0 kΩ, RL = 1.5 Ω
TJ = 150°C − 5.0 7.0
3. Pulse Test: Pulse Width v 300 μS, Duty Cycle v 2%.
*Maximum Value of Characteristic across Temperature Range.

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 NGD15N41CL, NGB15N41CL, NGP15N41CL

TYPICAL ELECTRICAL CHARACTERISTICS (unless otherwise noted)

60 60
VGE = 10 V VGE = 10 V
IC, COLLECTOR CURRENT (AMPS)

IC, COLLECTOR CURRENT (AMPS)

5V 4.5 V
50 50
4.5 V 5V
40 40 4V
4V
30 TJ = 25°C 30 TJ = −40°C 3.5 V
3.5 V

20 20
3V 3V

10 10
2.5 V 2.5 V
0 0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS)

Figure 1. Output Characteristics Figure 2. Output Characteristics

60 30

IC, COLLECTOR CURRENT (AMPS)

VCE = 10 V
IC, COLLECTOR CURRENT (AMPS)

VGE = 10 V
50 5V 25

4.5 V
40 TJ = 150°C 20
4V
30 3.5 V 15

3V
20 10 TJ = 25°C
2.5 V
10 5
TJ = 150°C
TJ = −40°C
0 0
0 1 2 3 4 5 6 7 8 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS) VGE, GATE TO EMITTER VOLTAGE (VOLTS)

Figure 3. Output Characteristics Figure 4. Transfer Characteristics

VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS)

COLLECTOR TO EMITTER VOLTAGE (VOLTS)

4.0 3
VGE = 5 V TJ = 25°C
3.5 IC = 25 A 2.5 IC = 15 A
3.0
IC = 20 A
2 IC = 10 A
2.5
IC = 15 A
IC = 5 A
2.0 1.5
IC = 10 A
1.5 IC = 5 A
1
1.0
0.5
0.5

0.0 0
−50 −25 0 25 50 75 100 125 150 3 4 5 6 7 8 9 10
TJ, JUNCTION TEMPERATURE (°C) GATE TO EMITTER VOLTAGE (VOLTS)

Figure 5. Collector−to−Emitter Saturation Figure 6. Collector−to−Emitter Voltage versus

Voltage versus Junction Temperature Gate−to−Emitter Voltage

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 NGD15N41CL, NGB15N41CL, NGP15N41CL

COLLECTOR TO EMITTER VOLTAGE (VOLTS)

3 10000

IC = 15 A TJ = 150°C
2.5 1000 Ciss

C, CAPACITANCE (pF)
2 IC = 10 A
100 Coss
1.5 IC = 5 A

10
Crss
1

1
0.5

0 0
3 4 5 6 7 8 9 10 0 20 40 60 80 100 120 140 160 180 200
GATE TO EMITTER VOLTAGE (VOLTS) VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS)

Figure 7. Collector−to−Emitter Voltage versus Figure 8. Capacitance Variation

Gate−to−Emitter Voltage

2 30
1.8 VCC = 50 V
THRESHOLD VOLTAGE (VOLTS)

Mean + 4 σ Mean
25 VGE = 5 V
IL, LATCH CURRENT (AMPS)

1.6
RG = 1000 Ω
1.4
20
1.2 Mean − 4 σ L = 2 mH L = 3 mH

1 15
0.8
10
0.6
L = 6 mH
0.4
5
0.2
0 0
−50 −30 −10 10 30 50 70 90 110 130 150 −50 −25 0 25 50 75 100 125 150 175
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 9. Gate Threshold Voltage versus Figure 10. Minimum Open Secondary Latch
Temperature Current versus Temperature

30 12
VCC = 50 V VCC = 300 V
25 VGE = 5 V 10 VGE = 5 V
RG = 1000 Ω RG = 1000 Ω
IL, LATCH CURRENT (AMPS)

SWITCHING TIME (μs)

IC = 10 A
20 L = 2 mH 8 tf
L = 300 μH

15 6
L = 3 mH td(off)
10 4
L = 6 mH
5 2

0 0
−50 −25 0 25 50 75 100 125 150 175 −50 −30 −10 10 30 50 70 90 110 130 150
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 11. Typical Open Secondary Latch Figure 12. Inductive Switching Fall Time
Current versus Temperature versus Temperature

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 NGD15N41CL, NGB15N41CL, NGP15N41CL

10
R(t), TRANSIENT THERMAL RESISTANCE (°C/Watt)

Duty Cycle = 0.5

0.2
1
0.1

0.05

0.02

0.1 0.01 D CURVES APPLY FOR POWER

P(pk)
PULSE TRAIN SHOWN
Single Pulse t1 READ TIME AT T1

t2 TJ(pk) − TA = P(pk) RθJA(t)

RθJC ≅ R(t) for t ≤ 0.2 s
DUTY CYCLE, D = t1/t2

0.01
0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
t,TIME (S)

Figure 13. Transient Thermal Resistance

(Non−normalized Junction−to−Ambient mounted on
fixture in Figure 14)

1.5″

4″
4″

0.125″
4″

Figure 14. Test Fixture for Transient Thermal Curve

(48 square inches of 1/8, thick aluminum)

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 NGD15N41CL, NGB15N41CL, NGP15N41CL

100 100

COLLECTOR CURRENT (AMPS)

COLLECTOR CURRENT (AMPS)

DC
10 10 DC
100 μs
1 ms 100 μs
1 1
10 ms
1 ms
100 ms
0.1 0.1 10 ms
100 ms

0.01 0.01
1 10 100 1000 1 10 100 1000
COLLECTOR−EMITTER VOLTAGE (VOLTS) COLLECTOR−EMITTER VOLTAGE (VOLTS)

Figure 15. Single Pulse Safe Operating Area Figure 16. Single Pulse Safe Operating Area
(Mounted on an Infinite Heatsink at TA = 255C) (Mounted on an Infinite Heatsink at TA = 1255C)

100 100
t1 = 1 ms, D = 0.05 COLLECTOR CURRENT (AMPS)
COLLECTOR CURRENT (AMPS)

t1 = 1 ms, D = 0.05
t1 = 2 ms, D = 0.10 t1 = 2 ms, D = 0.10
10 10
t1 = 3 ms, D = 0.30
t1 = 3 ms, D = 0.30

1 1
I(pk)
I(pk)
t1 t1
0.1 0.1
t2 t2
DUTY CYCLE, D = t1/t2 DUTY CYCLE, D = t1/t2
0.01 0.01
1 10 100 1000 1 10 100 1000
COLLECTOR−EMITTER VOLTAGE (VOLTS) COLLECTOR−EMITTER VOLTAGE (VOLTS)

Figure 17. Pulse Train Safe Operating Area Figure 18. Pulse Train Safe Operating Area
(Mounted on an Infinite Heatsink at TC = 255C) (Mounted on an Infinite Heatsink at TC = 1255C)

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 NGD15N41CL, NGB15N41CL, NGP15N41CL

ORDERING INFORMATION
Device Package Type Shipping †
NGD15N41CLT4 DPAK 2500/Tape & Reel
DPAK
NGD15N41CLT4G (Pb−Free) 2500/Tape & Reel
NGB15N41CLT4 D2PAK 800/Tape & Reel
D2PAK
NGB15N41CLT4G (Pb−Free) 800/Tape & Reel
NGP15N41CL TO−220 50 Units/Rail
TO−220
NGP15N41CLG (Pb−Free) 50 Units/Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.

MARKING DIAGRAMS

DPAK D2PAK TO−220AB

CASE 369C CASE 418B CASE 221A
STYLE 7 STYLE 4 STYLE 9
4
Collector
4
1 Collector
Gate

YWW 4 NGB NGP

2
GD Collector 15N41CLG 15N41CLG
Collector AYWW
15N41G AYWW

3 1 3
1 3
Emitter Gate Emitter
Gate 2 Emitter
Collector
2
Collector

A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Device

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 NGD15N41CL, NGB15N41CL, NGP15N41CL

PACKAGE DIMENSIONS

DPAK
CASE 369C−01
ISSUE O

−T− SEATING
PLANE
B C
INCHES MILLIMETERS
V R E DIM MIN MAX MIN MAX
A 0.235 0.245 5.97 6.22
B 0.250 0.265 6.35 6.73
4 C 0.086 0.094 2.19 2.38
Z D 0.027 0.035 0.69 0.88
A E 0.018 0.023 0.46 0.58
S F 0.037 0.045 0.94 1.14
1 2 3 G 0.180 BSC 4.58 BSC
U H 0.034 0.040 0.87 1.01
K J 0.018 0.023 0.46 0.58
K 0.102 0.114 2.60 2.89
L 0.090 BSC 2.29 BSC
F J R 0.180 0.215 4.57 5.45
L S 0.025 0.040 0.63 1.01
H U 0.020 −−− 0.51 −−−
V 0.035 0.050 0.89 1.27
D 2 PL Z 0.155 −−− 3.93 −−−
G 0.13 (0.005) M T STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN

SOLDERING FOOTPRINT*

6.20 3.0
0.244 0.118
2.58
0.101

5.80 1.6 6.172

0.228 0.063 0.243

SCALE 3:1 ǒinches

mm Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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 NGD15N41CL, NGB15N41CL, NGP15N41CL

PACKAGE DIMENSIONS

D2PAK
CASE 418B−04
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING
C PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E 3. 418B−01 THRU 418B−03 OBSOLETE,
V NEW STANDARD 418B−04.
−B−
W INCHES MILLIMETERS
4 DIM MIN MAX MIN MAX
A 0.340 0.380 8.64 9.65
B 0.380 0.405 9.65 10.29
C 0.160 0.190 4.06 4.83
A D 0.020 0.035 0.51 0.89
S E 0.045 0.055 1.14 1.40
1 2 3
F 0.310 0.350 7.87 8.89
G 0.100 BSC 2.54 BSC
H 0.080 0.110 2.03 2.79
−T− K J 0.018 0.025 0.46 0.64
SEATING W K 0.090 0.110 2.29 2.79
PLANE L 0.052 0.072 1.32 1.83
G J M 0.280 0.320 7.11 8.13
N 0.197 REF 5.00 REF
H P 0.079 REF 2.00 REF
D 3 PL R 0.039 REF 0.99 REF
0.13 (0.005) M T B M S 0.575 0.625 14.60 15.88
V 0.045 0.055 1.14 1.40

STYLE 4:
VARIABLE PIN 1. GATE
CONFIGURATION 2. COLLECTOR
ZONE N P 3. EMITTER
R U
4. COLLECTOR

L L L

M M M

F F F

VIEW W−W VIEW W−W VIEW W−W

1 2 3

SOLDERING FOOTPRINT*
8.38
0.33

10.66 1.016 6.096

0.42 0.04 0.24

3.05
0.12
17.02
0.67
SCALE 3:1 ǒinches
mm Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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 NGD15N41CL, NGB15N41CL, NGP15N41CL

PACKAGE DIMENSIONS

TO−220
CASE 221A−09
ISSUE AB
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
SEATING
−T− PLANE 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
B F C BODY AND LEAD IRREGULARITIES ARE
T ALLOWED.
S
INCHES MILLIMETERS
4 DIM MIN MAX MIN MAX
A 0.570 0.620 14.48 15.75
Q A B 0.380 0.405 9.66 10.28
C 0.160 0.190 4.07 4.82
1 2 3 U D 0.025 0.035 0.64 0.88
F 0.142 0.147 3.61 3.73
H G 0.095 0.105 2.42 2.66
H 0.110 0.155 2.80 3.93
K J 0.018 0.025 0.46 0.64
Z K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
N 0.190 0.210 4.83 5.33
L R Q 0.100 0.120 2.54 3.04
R 0.080 0.110 2.04 2.79
V J S 0.020 0.055 0.508 1.39
T 0.235 0.255 5.97 6.47
G U 0.000 0.050 0.00 1.27
V 0.045 −−− 1.15 −−−
D Z −−− 0.080 −−− 2.04
N STYLE 9:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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