MJD41C(NPN),

MJD42C(PNP)

Complementary Power
Transistors
DPAK for Surface Mount Applications
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Designed for general purpose amplifier and low speed switching
applications.
SILICON
Features
POWER TRANSISTORS
• Lead Formed for Surface Mount Applications in Plastic Sleeves
6 AMPERES
(No Suffix)
• Straight Lead Version in Plastic Sleeves (“1” Suffix) 100 VOLTS, 20 WATTS
• Electrically Similar to Popular TIP41 and TIP42 Series
COMPLEMENTARY
• Epoxy Meets UL 94 V−0 @ 0.125 in
• NJV Prefix for Automotive and Other Applications Requiring COLLECTOR
2, 4
COLLECTOR
2, 4
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant 1 1
BASE BASE

MAXIMUM RATINGS 3 3
Rating Symbol Max Unit EMITTER EMITTER

Collector−Emitter Voltage VCEO 100 Vdc

4
Collector−Base Voltage VCB 100 Vdc
Emitter−Base Voltage VEB 5 Vdc 4
Collector Current − Continuous IC 6 Adc
1
Collector Current − Peak ICM 10 Adc 1 2 2
3 3
Base Current IB 2 Adc DPAK IPAK
Total Power Dissipation PD W CASE 369C CASE 369D
@ TC = 25°C 20 W/°C STYLE 1 STYLE 1
Derate above 25°C 0.16

Total Power Dissipation (Note 1) PD W

MARKING DIAGRAMS
@ TA = 25°C 1.75
Derate above 25°C 0.014 W/°C

Operating and Storage Junction TJ, Tstg −65 to +150 °C AYWW AYWW
Temperature Range J4xCG J4xCG
ESD − Human Body Model HBM 3B V
ESD − Machine Model MM C V DPAK IPAK
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be A = Assembly Location
assumed, damage may occur and reliability may be affected. Y = Year
1. These ratings are applicable when surface mounted on the minimum pad WW = Work Week
sizes recommended.
J4xC = Device Code
x = 1 or 2
G = Pb−Free Package

ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.

© Semiconductor Components Industries, LLC, 2016 1 Publication Order Number:

July, 2016 − Rev. 13 MJD41C/D
 MJD41C (NPN), MJD42C (PNP)

THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance, Junction−to−Case RqJC 6.25 °C/W
Thermal Resistance, Junction−to−Ambient (Note 2) RqJA 71.4 °C/W
2. These ratings are applicable when surface mounted on the minimum pad sizes recommended.

ELECTRICAL CHARACTERISTICS (TC = 25_C unless otherwise noted)

Characteristic Symbol Min Max Unit

OFF CHARACTERISTICS

Collector−Emitter Sustaining Voltage (Note 3) VCEO(sus) Vdc

(IC = 30 mAdc, IB = 0) 100 −

Collector Cutoff Current ICEO mAdc

(VCE = 60 Vdc, IB = 0) − 50

Collector Cutoff Current ICES mAdc

(VCE = 100 Vdc, VEB = 0) − 10

Emitter Cutoff Current IEBO mAdc

(VBE = 5 Vdc, IC = 0) − 0.5

ON CHARACTERISTICS (Note 3)

DC Current Gain hFE −

(IC = 0.3 Adc, VCE = 4 Vdc) 30 −
(IC = 3 Adc, VCE = 4 Vdc) 15 75

Collector−Emitter Saturation Voltage VCE(sat) Vdc

(IC = 6 Adc, IB = 600 mAdc) − 1.5

Base−Emitter On Voltage VBE(on) Vdc

(IC = 6 Adc, VCE = 4 Vdc) − 2

DYNAMIC CHARACTERISTICS

Current Gain − Bandwidth Product (Note 4) fT MHz

(IC = 500 mAdc, VCE = 10 Vdc, ftest = 1 MHz) 3 −

Small−Signal Current Gain hfe −

(IC = 0.5 Adc, VCE = 10 Vdc, f = 1 kHz) 20 −

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. fT = ⎪hfe⎪• ftest.

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 MJD41C (NPN), MJD42C (PNP)

TYPICAL CHARACTERISTICS
TA TC VCC
2.5 25 +30 V
PD, POWER DISSIPATION (WATTS)

2 20 RC
25 ms
+11 V SCOPE
RB
1.5 15 0
TC
-9 V 51 D1

1 10 TA SURFACE MOUNT
tr, tf ≤ 10 ns
-4 V
DUTY CYCLE = 1%
0.5 5 RB and RC VARIED TO OBTAIN DESIRED CURRENT LEVELS
D1 MUST BE FAST RECOVERY TYPE, e.g.:
0 0 MSB5300 USED ABOVE IB ≈ 100 mA
25 50 75 100 125 150 MSD6100 USED BELOW IB ≈ 100 mA
REVERSE ALL POLARITIES FOR PNP.
T, TEMPERATURE (°C)

Figure 1. Power Derating Figure 2. Switching Time Test Circuit

500 2
TJ = 25°C
300 VCE = 2 V 1 VCC = 30 V
200 TJ = 150°C IC/IB = 10
0.7
hFE, DC CURRENT GAIN

0.5
100 25°C
t, TIME (s)

70
μ

0.3 tr
50 0.2

30
-55°C 0.1
20
0.07 td @ VBE(off) ≈ 5 V
10 0.05
7 0.03
5 0.02
0.06 0.1 0.2 0.3 0.4 0.6 1 2 4 6 0.06 0.1 0.2 0.4 0.6 1 2 4 6

IC, COLLECTOR CURRENT (AMP) IC, COLLECTOR CURRENT (AMP)

Figure 3. DC Current Gain Figure 4. Turn−On Time

1.4 1.4
VBE(ON), BASE−EMITTER VOLTAGE (V)

VCE = 4 V IC/IB = 10
1.2 1.2
SATURATION VOLTAGE (V)
VBE(sat), BASE−EMITTER

1.0 1.0

0.8 −55°C 0.8 −55°C

−40°C −40°C
0.6 0.6
25°C 25°C
0.4 0.4 80°C
80°C
TA = 150°C
0.2 TA = 150°C 0.2

0 0
0.01 0.1 1 10 0.01 0.1 1 10
IC, COLLECTOR CURRENT (A) IC, COLLECTOR CURRENT (A)
Figure 5. Base Emitter Voltage vs. Collector Figure 6. Base Emitter Saturation Voltage vs.
Current Collector Current

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 MJD41C (NPN), MJD42C (PNP)

TYPICAL CHARACTERISTICS

1.0 5
TA = 150°C TJ = 25°C
0.9 IC/IB = 10 3
80°C VCC = 30 V
SATURATION VOLTAGE (V)

0.8 2 IC/IB = 10
VCE(sat), BASE−EMITTER

25°C ts IB1 = IB2

0.7
1

t, TIME (s)
0.6 0.7

μ
0.5 0.5
0.4 0.3
0.3 0.2
tf
0.2
0.1
0.1 −40°C
and −55°C 0.07
0 0.05
0.01 0.1 1 10 0.06 0.1 0.2 0.4 0.6 1 2 4 6
IC, COLLECTOR CURRENT (A) IC, COLLECTOR CURRENT (AMP)

Figure 7. Collector Emitter Saturation Voltage Figure 8. Turn−Off Time

vs. Collector Current
VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS)

2 300
TJ = 25°C TJ = 25°C
1.6 200
C, CAPACITANCE (pF)

IC = 1 A 2.5 A 5A Cib
1.2
100

0.8
70 Cob

0.4 50

0 30
10 20 30 50 100 200 300 500 1000 0.5 1 2 3 5 10 20 30 50
IB, BASE CURRENT (mA) VR, REVERSE VOLTAGE (VOLTS)

Figure 9. Collector Saturation Region Figure 10. Capacitance

1
0.7
r(t), EFFECTIVE TRANSIENT THERMAL

D = 0.5
0.5
RESISTANCE (NORMALIZED)

0.3 0.2
0.2 P(pk)
RqJC(t) = r(t) RqJC
0.1
RqJC = 6.25°C/W MAX
0.1 0.05 D CURVES APPLY FOR POWER
0.07 PULSE TRAIN SHOWN
0.02 t1
0.05 READ TIME AT t1 t2
TJ(pk) - TC = P(pk) qJC(t)
0.03 0.01 DUTY CYCLE, D = t1/t2
0.02 SINGLE PULSE

0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1 2 3 5 10 20 30 50 100 200 300 500 1000
t, TIME (ms)

Figure 11. Thermal Response

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4
 MJD41C (NPN), MJD42C (PNP)

10 There are two limitations on the power handling ability of

500ms 100ms
5 a transistor: average junction temperature and second
IC, COLLECTOR CURRENT (AMP)

3 1ms breakdown. Safe operating area curves indicate IC − VCE

2 dc
5ms limits of the transistor that must be observed for reliable
1 operation; i.e., the transistor must not be subjected to greater
0.5 WIRE BOND LIMIT dissipation than the curves indicate.
0.3 THERMAL LIMIT The data of Figure 12 is based on TJ(pk) = 150_C; TC is
SECOND BREAKDOWN LIMIT variable depending on conditions. Second breakdown pulse
0.1 CURVES APPLY BELOW RATED VCEO
limits are valid for duty cycles to 10% provided
0.05
TC = 25°C SINGLE PULSE
TJ(pk) v 150_C. TJ(pk) may be calculated from the data in
0.03 Figure 11. At high case temperatures, thermal limitations
TJ = 150°C MJD41C, 42C
will reduce the power that can be handled to values less than
0.01 the limitations imposed by second breakdown.
1 2 3 5 7 10 20 30 50 70 100
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)

Figure 12. Maximum Forward Bias

Safe Operating Area

ORDERING INFORMATION
Device Package Type Package Shipping†
MJD41CRLG DPAK 369C 1,800 / Tape & Reel
(Pb−Free)
MJD41CT4G DPAK 369C 2,500 / Tape & Reel
(Pb−Free)
NJVMJD41CT4G* DPAK 369C 2,500 / Tape & Reel
(Pb−Free)
MJD42CG DPAK 369C 75 Units / Rail
(Pb−Free)
MJD42C1G IPAK 369D 75 Units / Rail
(Pb−Free)
MJD42CRLG DPAK 369C 1,800 / Tape & Reel
(Pb−Free)
NJVMJD42CRLG* DPAK 369C 1,800 / Tape & Reel
(Pb−Free)
MJD42CT4G DPAK 369C 2,500 / Tape & Reel
(Pb−Free)
NJVMJD42CT4G* DPAK 369C 2,500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NJV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable

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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

IPAK
CASE 369D−01
ISSUE C
DATE 15 DEC 2010

B C NOTES:
SCALE 1:1 1. DIMENSIONING AND TOLERANCING PER
V R E ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.

INCHES MILLIMETERS
4 DIM MIN MAX MIN MAX
Z A 0.235 0.245 5.97 6.35
A B 0.250 0.265 6.35 6.73
S C 0.086 0.094 2.19 2.38
1 2 3
D 0.027 0.035 0.69 0.88
E 0.018 0.023 0.46 0.58
−T− F 0.037 0.045 0.94 1.14
SEATING G 0.090 BSC 2.29 BSC
PLANE K H 0.034 0.040 0.87 1.01
J 0.018 0.023 0.46 0.58
K 0.350 0.380 8.89 9.65
R 0.180 0.215 4.45 5.45
J S 0.025 0.040 0.63 1.01
F V 0.035 0.050 0.89 1.27
H
Z 0.155 −−− 3.93 −−−
D 3 PL
G 0.13 (0.005) M T
MARKING
DIAGRAMS
STYLE 1: STYLE 2: STYLE 3: STYLE 4: Integrated
PIN 1. BASE PIN 1. GATE PIN 1. ANODE PIN 1. CATHODE
2. COLLECTOR 2. DRAIN 2. CATHODE 2. ANODE Discrete Circuits
3. EMITTER 3. SOURCE 3. ANODE 3. GATE
4. COLLECTOR 4. DRAIN 4. CATHODE 4. ANODE
YWW xxxxx
STYLE 5: STYLE 6: STYLE 7:
xxxxxxxx ALYWW
PIN 1. GATE PIN 1. MT1 PIN 1. GATE
2. ANODE 2. MT2 2. COLLECTOR x
3. CATHODE 3. GATE 3. EMITTER
4. ANODE 4. MT2 4. COLLECTOR

xxxxxxxxx = Device Code

A = Assembly Location
lL = Wafer Lot
Y = Year
WW = Work Week

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON10528D Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: IPAK (DPAK INSERTION MOUNT) PAGE 1 OF 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

4 DPAK (SINGLE GAUGE)

CASE 369C
ISSUE G
1 2
3 DATE 31 MAY 2023
SCALE 1:1

GENERIC
MARKING DIAGRAM*

XXXXXXG AYWW
ALYWW XXX
XXXXXG

IC Discrete

XXXXXX = Device Code

A = Assembly Location
L = Wafer Lot
STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5: Y = Year
PIN 1. BASE PIN 1. GATE PIN 1. ANODE PIN 1. CATHODE PIN 1. GATE
2. COLLECTOR 2. DRAIN 2. CATHODE 2. ANODE 2. ANODE
WW = Work Week
3. EMITTER 3. SOURCE 3. ANODE 3. GATE 3. CATHODE G = Pb−Free Package
4. COLLECTOR 4. DRAIN 4. CATHODE 4. ANODE 4. ANODE
*This information is generic. Please refer to
STYLE 6: STYLE 7: STYLE 8: STYLE 9: STYLE 10: device data sheet for actual part marking.
PIN 1. MT1 PIN 1. GATE PIN 1. N/C PIN 1. ANODE PIN 1. CATHODE Pb−Free indicator, “G” or microdot “G”, may
2. MT2 2. COLLECTOR 2. CATHODE 2. CATHODE 2. ANODE
3. GATE 3. EMITTER 3. ANODE 3. RESISTOR ADJUST 3. CATHODE or may not be present. Some products may
4. MT2 4. COLLECTOR 4. CATHODE 4. CATHODE 4. ANODE not follow the Generic Marking.

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98AON10527D Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: DPAK (SINGLE GAUGE) PAGE 1 OF 1

onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
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