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New LFN and RTN analysis methodology in 28 and 14nm FD-SOI MOSFETs

Conference Paper · April 2015

DOI: 10.1109/IRPS.2015.7112833

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 New LFN and RTN analysis methodology
in 28 and 14nm FD-SOI MOSFETs
Christoforos G. Theodorou1, Eleftherios G. Ioannidis1, Sebastien Haendler2, Nicolas Planes2, Emmanuel
Josse2, Charalabos A. Dimitriadis3, Member, IEEE, and Gerard Ghibaudo1, Fellow IEEE
1
IMEP-LAHC, INPG, Minatec, BP 257, 38016 Grenoble, France
2
STMicroelectronics, 850, rue J. Monnet, BP 16, 38921 Crolles, France
3
Dpt of Physics, Aristotle University of Thessaloniki, 54124, Greece
E-mail: theodoch@minatec.inpg.fr, ioannidis.eleftherios@imep.grenoble-inp.fr

Abstract— A thorough investigation and statistical analysis of II. EXPERIMENTAL SETUP

the low-frequency (LFN) and random telegraph noise (RTN) in
28 and 14nm FD-SOI CMOS transistors is presented, for the first
Electrical measurements were performed on n- and p- MOS
time. It is shown that the 14nm technology node is improved in transistors fabricated using 28 and 14nm FD-SOI CMOS
terms of threshold voltage fluctuations when compared to the technologies [9, 10]. The channel length (L) of the measured
28nm one. A new analysis method that directly probes the RTN devices is the minimum for each technology node, while the
presence is also proposed. Finally, the LFN/RTN impact on the widths (W) range between 0.08 to 10ȝm, and 0.06 to 3ȝm, for
device dynamic variability is presented through CADENCE 28nm and 14nm technology nodes, respectively. Time domain
design suite circuit simulations. sampling measurements of the drain current Id(t) were
performed in saturation (Vdd=1V, 0.9V) with Agilent
I. INTRODUCTION B1500/1530 Semiconductor Device Analyzer, as described in
Device area scaling is one of the most effective methods for [11]. For a detailed study of the RTN behavior of the MOS
achieving better performance and higher speed in electronic transistor, we biased the device at different gate voltages from
circuits. To meet these requirements in CMOS technology and weak to strong inversion and at three different sampling rates,
to avoid additional oxide thickness and channel length scaling keeping the number of points constant, in order to cover the
related issues, new device architectures such as FinFET and noise spectrum frequency bandwidth from 0.5 up to 5×105 Hz
FDSOI have been proposed to replace the planar bulk CMOS and increase its resolution. We then repeated the measurements
technology [1-2]. Lower threshold voltage variability, better for minimum 45 dies for each device type and technology
control of the channel, and compatibility with standard planar node.
CMOS technology makes fully depleted silicon-on-insulator Fig. 1 shows a typical time domain signature of the
(FD-SOI) an attractive option [3-5]. measured drain current; actual appearance of RTN usually
However, device area scaling leads to statistical parameters depends on the sampling conditions. Fig. 2 illustrates the
variability [6], and to a substantial increase of low frequency corresponding spectra of the Id(t) from Fig. 1, confirming RTN
noise (LFN) and random telegraph noise (RTN) which can is observed at specific sampling frequencies, which gives
limit the performance of analog and digital circuits [7-8]. As a
result, a detailed study of RTN and its statistical variability in
advanced CMOS technologies is required.
In this work, we present a comprehensive analysis of the
LFN/RTN in 28 and 14nm FD-SOI MOSFET technologies.
First, we demonstrate that our noise measurement method
allows us to achieve higher resolution in both time and
frequency domains. Next, a drain current noise spectra
analysis, which enables us to characterize the CMOS
technology in terms of trap density, is presented. Afterwards, a
time domain analysis is used to study the LFN/RTN-induced
threshold voltage fluctuations and a new RTN and noise
variability analysis methodology is proposed. Finally, we
demonstrate the impact of the device noise on its dynamic
variability using CADENCE design suite simulations.
Fig. 1. Drain current Id(t) for 3 different sampling frequencies fS .

978-1-4673-7362-3/15/$31.00 ©2015 IEEE XT.1.1

 Fig. 2: Concatenated spectra of Fig. 1 signals
Fig. 4. Normalized drain current noise (symbols) and CNF model (lines) at
rise to a Lorentzian-like spectrum. A perfect noise level 10Hz.
agreement between the various sampling rates is also
demonstrated here.

III. RESULTS AND DISCUSSION

A. LFN analysis
Fig. 3 shows the device-to-device normalized noise spectra
variability for the minimum geometry transistors from 14 nm
technology node. The dispersion of the normalized noise level
at 10Hz is shown in Fig. 4, indicating that the average LFN
level generally follows the carrier number fluctuations model
[12,13]:
2
S Id § g m ·
= ¨ ¸ ⋅ SVfb (1) Fig. 5. Nt versus device area for n- and p- MOS from 14nm technology
I d ² ¨© I d ¸¹ node.

The flat band voltage spectral density SVfb, given by (2), allows volumetric interface trap density in cm-3/eV-1 and Cox the
the extraction of the slow oxide trap density Nt in the gate equivalent oxide capacitance.
dielectric:
As shown in Fig. 5, the state-of-the-art Nt values obtained
q ² kTλN t for the 14 nm FDSOI are slightly better than those obtained for
SVfb = (2)
WLCox ² f 28 nm FDSOI [14]. Fig. 6 shows the average wafer trap areal
where q is the elementary charge, kT is the thermal energy, Ȝ density, Dst (Eq. 3), and corresponding average absolute
is the tunnel attenuation distance (≈0.1 nm for SiO2), Nt is the number per device, Nst =Dst.(WL), as calculated from the
spectra integrals (Eq. 4). A clear gate voltage dependence due
to specific trap-induced RTN is revealed here.
2 2
W .L.C ox .σ Vth
Dst = (3)
q 2 kT
f max

σ Vth = ³
f = f min
S Vg df (4)

The method described above offers a more realistic

representation of the oxide trap density over the entire
frequency range, thereby covering the whole time constant
Fig. 3. Normalized drain current spectral density SId/Id2 versus frequency. space, too. In contrast, the standard analysis just extracts the

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 Fig. 8. Normalized RTN amplitude (symbols) and model (lines) versus drain
current.

Fig. 6. Full wafer mean trap areal density Dst and average absolute number
per device Nst (n-MOS 14 nm FD-SOI, W=60nm, L=20 nm)

Fig. 9. Ratio of RTN capture and emission time versus drain current.

σ Id (t )
σ Vth = (5)
gm
By this way, the device-to-device static variability is
Fig. 7. Absolute interface trap number versus gate voltage for all 85 dies. (n- rejected. This value was calculated per die, gate voltage and
MOS 14 nm FD-SOI, W=60nm, L=20 nm)
sampling rate, thus refers to the single device threshold voltage
dynamic variations and not to the device-to-device Vth static
volume trap density Nt from a pure flicker noise spectrum over
variability.
narrow frequency range e.g. around 10 Hz.
Figs. 10-11 show that the average Id(t) for three different
For pure 1/f noise, Dst=Nt.λ.ln(fmax/fmin), provides an average
sampling rates remains unchanged, but ıId(t) depends on both
value of Dst(Vg), as shown in Fig. 6 (lines). The average
bias and sampling rate. Fig. 12 presents the dispersion of ıVt
number of traps per nominal device, Nst, varies between 0.3
for all gate voltages and sampling rates, revealing a strong
and 1.2, depending on Vg. The small values around unity
dependence on the bias and sampling conditions, thereby
imply substantial RTN-induced variability in the smallest
supporting the usefulness of this quantity for noise analysis.
device area (60nm×20nm=0.0012ȝm2) as illustrated in Fig. 7.
B. Statistical analysis of RTN
Figs 8-9 show the amplitude and the time constants ratio
from standard RTN analysis [15] fora typical 28nm technology
node device. Here two traps are activated at different sampling
rates, following a different time constant dependency with gate
voltage. Due to the random nature of RTN, this methodology
is inadequate and cumbersome for statistical analysis involving
a large number of dies.
In contrast, we first calculate the standard deviation of the
threshold voltage, ıVth, which takes into account the overall
RTN amplitude variation. This quantity is defined as the
standard deviation of the drain current over time, ıId(t),
normalized by the transconductance gm: Fig. 10. Mean values of Id(t) versus gate voltage (1 die example).

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 Fig. 11. Standard deviation of Id(t) versus gate voltage (1 die example).

Fig. 14. Noise induced matching dynamic parameter Am(ıVth) versus

sampling time with standard deviation values.
not observe any difference between ıVth from linear and
saturation regions of operation. From this plot, as in static
mismatch analysis, a LFN/RTN matching dynamic parameter,
Am, can be deduced from the slope, normalizing the area
scaling. Fig. 14 shows the dependence of Am on the sampling
time for both technologies under study. It is observed that the
Am values are improved in 14nm technology node for both n-
and p-MOS devices , in agreement with the EOT scaling.
To complete the RTN analysis and quantify its impact on
the spectrum at each gate voltage and measured die,
irrespective of sampling rate, we propose a new RTN strength
indicator. This involves the analysis of standard deviation
Fig. 12. Standard deviation of Vth versus die number for all gate voltage ı(log(SVG.f)) vs frequency, where SVG= SId/gm2. Fig. 15 shows
values. that in presence of RTN over a certain bias range, log(SVG.f)
strongly deviates from the flat line that corresponds to 1/f-like
noise. This gives rise to the variation, ı(log(SVG.f)). The full
wafermap of Fig. 16 shows that ı(log(SVG.f)) is bias
dependent, due to the RTN trap activity, and randomly

Fig. 13. Mean value (45 dies) of ıVth versus 1/sqrt(W.L) for different
sampling times for n-MOS 28nm FD-SOI (linear Vd=50mV)

Fig. 13 shows that the average ıVth scales as the reciprocal

square root of device area for different sampling times (ts).
This is expected since LFN follows the same Pelgrom’s law
for area scaling, as static mismatch does [14, 16]. We also did
Fig. 15. log(SVg.f) for 1/f-like (red) and Lorentzian- like (black) spectra (n-
MOS 14 nm FD-SOI, W=60nm, L=20 nm)

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 by a specific number (in this case 4) of randomly distributed
additional RTN fluctuators over 6 frequency decades,
superimposed to a 1/f background spectrum. Note also in Fig.
17 that ı(log(SVG.f)) is highly sensitive to the number of RTN
per decade, demonstrating its RTN statistical probing
capability. Fig. 18 shows the full wafer cartography of the
mean values of ı(log(SVG.f)) for all gate voltages. It is clear
that they exhibit a smoother wafer distribution, confirming that
the average of many RTN-like spectra converges to a 1/f-
spectrum.
C. Dynamic variability simulations
Since dynamic fluctuations of threshold voltage depend on
sampling rate, the operating frequency of a real circuit can
influence device dynamic variability [9]. To assess the impact,
we simulated transient noise using Spectre in the Cadence
Virtuoso environment, using a 28nm FDSOI design kit with
flicker noise model. A ramped voltage was applied to the gate
Fig. 16. Colored wafer maps based on the values of ı(log(SVg.f)) (dec) for
with fixed number of steps but varying ramp rate (0 to 1V).
various gate voltage values (n-MOS 14nm FD-SOI, W=60nm, L=20nm).
ıVth was calculated from100 such repetitions as in presented in
[9]. Fig. 19 shows an example of ıVth calculation for 100
multiple runs. The drawback of transient noise analysis, as
shown in Fig. 20, is that the maximum noise bandwidth is
limited by the simulation duration and steps count. Fig. 21

Fig. 17. CDF of ı(log(SVG.f)) (dec) (measurements and model) (n-MOS 14

nm FD-SOI, W=60nm, L=20nm).

Fig. 19: Extraction of ǻVth from transient noise simulations (W=80nm,

L=30nm)

Fig. 18: Colored wafer map based on the mean values of ı(log(SVG.f)) (dec)
(n-MOS 14 nm FD_SOI, W=60nm, L=20nm)

distributed over the wafer map, revealing few RTN dominated

dies. Considering the cumulative distribution function (CDF)
for an arbitrarily selected gate voltage, Fig. 17 shows that the
Fig. 20. Calculation of ıVth from the spectrum integral (W=80nm, L=30nm).
statistical distribution of ı(log(SVG.f)) can be easily modeled

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